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* rockchip: add core px30 headersHeiko Stuebner2019-11-174-0/+249
| | | | | | | | Add headers needed by the upcoming px30 support, including two new dt-binding headers taken from the Linux kernel. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* spl: separate SPL_FRAMEWORK config for spl and tplHeiko Stuebner2019-11-177-4/+18
| | | | | | | | | | | | | | Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all cases, making the TPL bigger. There may be cases where the TPL is really size constrained due to its underlying ram size. Therefore introduce a new TPL_FRAMEWORK option and make the relevant conditionals check for both. The default is set to "y if SPL_FRAMEWORK" to mimic the previous behaviour where the TPL would always get the SPL framework if it was enabled in SPL. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Fix dram setting to make dram more stableYouMin Chen2019-11-171-21/+20
| | | | | | | | | | | | There are some code different with rockchip vendor code which may lead to different bugs, including: 1) Fix setting error about LPDDR3 dram size ODT. 2) Set phy io speed to 0x2. 3) Fix setting error about phy_pad_fdbk_drive. 4) Fix setting error about PI_WDQLVL_VREF_EN Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: update calculate_strideKever Yang2019-11-172-39/+128
| | | | | | | Update the calculation of the stride to support all the DRAM case. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Sync the io setting from Rockchip vendor codeKever Yang2019-11-171-30/+14
| | | | | | | | The io setting are updated after some bugfix in different rk3399 boards, sync the code from vendor. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: update lpddr4 timing for rk3399Kever Yang2019-11-172-9/+9
| | | | | | | | Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip vendor code; Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: add support detect capacityYouMin Chen2019-11-171-21/+215
| | | | | | | | Add capacity detect for rk3399 so that the driver able to detect the capacity automatically. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: update the function of sdram_initYouMin Chen2019-11-171-123/+296
| | | | | | | Clean up the sdram_init to keep sync with rockchip source code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: fix error about get_ddrc0_con reg addrYouMin Chen2019-11-171-1/+1
| | | | | | | Correct the register to its correct name. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Clean up codeYouMin Chen2019-11-171-83/+93
| | | | | | | Clean up rk3399 dram driver source code for more readable. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: migrate to use common codeYouMin Chen2019-11-1714-171/+179
| | | | | | | | For there are some structures and functions are common for all rockchip SoCs, migrate to use the common code so that we can clean up reduandent codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3328: use common sdram driverYouMin Chen2019-11-179-906/+295
| | | | | | | | RK3328 has a similar controller and phy with PX30, so we can use the common driver for it and remove the duplicate codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: px30: add sdram driverYouMin Chen2019-11-179-1/+1302
| | | | | | | | | | | | Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3. For TPL_BUILD, the driver implement full dram init and without DM support due to the limit of internal SRAM size. For SPL and U-Boot proper, it's a simple driver with dm for get dram_info like other SoCs. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: add common msch reg definitionKever Yang2019-11-171-0/+85
| | | | | | | | | The noc register bit definition may be the same for different SoC while the offset of the register may be different, add the struction definition as common code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: add phy driver code for PX30Kever Yang2019-11-173-0/+326
| | | | | | | | This sdram_phy_px30.c is based on PX30 SoC, the functions are common for phy, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: add controller code for PX30Kever Yang2019-11-172-0/+344
| | | | | | | | This sdram_pctl_px30.c is based on PX30 SoC, the functions are common for controller, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: Default enable DRAM debug infoKever Yang2019-11-171-0/+1
| | | | | | | The debug info for dram is main about the capacity related info which is very important the board init, so set this default enable. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: move sdram_debug function into sdram_commonKever Yang2019-11-173-148/+144
| | | | | | | The functions for dram info print are part of common code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: add common code for sdram driverKever Yang2019-11-174-0/+323
| | | | | | | | | There are some function like os_reg setting, capacity detect functions, can be used as common code for different Rockchip SoCs, add a sdram_common.c for all these functions. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: sdram: update the sys_reg to sys_reg2Kever Yang2019-11-171-16/+16
| | | | | | | | We are using sys_reg2 and sys_reg3 as ddr cap info, sync the variable name to what we real use to avoid confuse people. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: sdram: extend to use sys_reg3 for capacity infoKever Yang2019-11-173-47/+152
| | | | | | | | | | | | | Since we have new DRAM type and to support different DRAM size in different CS, we need more bits, so introduce sys_reg3 to record the info. Note that the info in sys_reg3 is extension to sys_reg2 and the info in sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as VERSION2. All the ENC macro are moved to sdram_common.h since the sdram.c only need to do the info decode. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: sdram: move cap structure and debug function to sdram_common.hKever Yang2019-11-174-48/+61
| | | | | | | | | The sdram.h suppose to be helper file for sdram.c which including dram size decode and some u-boot related dram init interface, and all structure and function for dram driver move to sdram_common.h Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: rename sdram_common.c/h to sdram.cKever Yang2019-11-1713-14/+14
| | | | | | | | | | rename sdram_common.c in arch/arm/mach-rockchip to sdram.c; so that we can use the file name sdram_common.c in dram driver for better understand the code; clean the related file who has use the header file at the same time. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: rename sdram.h to sdram_rk3288.hKever Yang2019-11-175-4/+3
| | | | | | | | The header file sdram.h is used for rk3288 and similar SoCs, rename it to make it more understandable. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* Merge branch '2019-11-12-migrate-SYS_REDUNDAND_ENVIRONMENT'Tom Rini2019-11-12204-70/+176
|\ | | | | | | | | | | | | - Migrate the symbol CONFIG_SYS_REDUNDAND_ENVIRONMENT to Kconfig. This is size neutral outside of two platforms with latent bugs being fixed now and they no longer have "ENV_IS_NOWHERE" set along with their intended location.
| * defconfigs: Migrate CONFIG_SYS_REDUNDAND_ENVIRONMENTTom Rini2019-11-12202-68/+174
| | | | | | | | | | | | | | | | Move this symbol to Kconfig. As part of this we can drop a UBI-specific symbol that was a stop-gap for not having this particular symbol in Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com>
| * pfla02: Migrate CONFIG_ENV_IS_IN_SPI_FLASH to defconfigTom Rini2019-11-122-1/+1
| | | | | | | | | | | | | | | | This board is setting CONFIG_ENV_IS_IN_SPI_FLASH in the header rather than defconfig, fix. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
| * evb-rk3128: Migrate CONFIG_ENV_IS_IN_MMC to defconfigTom Rini2019-11-122-1/+1
|/ | | | | | | | This board is setting CONFIG_ENV_IS_IN_MMC in the header rather than defconfig, fix. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'u-boot-imx-20191105' of ↵Tom Rini2019-11-1254-341/+5802
|\ | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191105 ------------------- i.MX8MN SoC support ROM API image download support i.MX8MM enet enabling
| * imx: imx8mm-evk: enable ethernetPeng Fan2019-11-054-0/+56
| | | | | | | | | | | | | | | | add phy-reset-gpios to reset phy Add board_phy_config to configure phy Enable DM_ETH Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * net: fec_mxc: support i.MX8M with CLK_CCFPeng Fan2019-11-052-15/+68
| | | | | | | | | | | | | | | | | | | | | | Add more clks for fec_mxc according to Linux Kernel 5.4.0-rc1 drivers/net/ethernet/freescale/fec_main.c. Since i.MX8MQ not support CLK_CCF, so add a check to restrict the code only effect when CONFIG_IMX8M and CONFIG_CLK_CCF both defined. Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * net: Kconfig: FEC: Add dependency on i.MX8MPeng Fan2019-11-051-1/+1
| | | | | | | | | | | | | | | | | | Make FEC driver could be used by i.MX8M when CONFIG_FEC_MXC defined in defconfig. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * arm: dts: imx8mm: drop assigned clocks for clk nodePeng Fan2019-11-051-0/+3
| | | | | | | | | | | | | | Drop assigned clocks for clk node, this will break boot on i.MX8MM EVK board. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx: imx8mm: add set_parent callbackPeng Fan2019-11-051-0/+19
| | | | | | | | | | | | | | | | | | Add set_parent callback, then assigned-clock-parents in dts could be work. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * clk: imx8mm: add enet clkPeng Fan2019-11-051-0/+27
| | | | | | | | | | | | | | | | | | Add enet ref/timer/PHY_REF/root clk which are required to make enet function well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
| * imx: imx8m: fix boot when CONFIG_$(SPL_)CLK not definedPeng Fan2019-11-051-6/+8
| | | | | | | | | | | | | | | | | | | | When CONFIG_$(SPL_)CLK not defined, the clock controller device not exist, so to avoid boot failure for platform not have CONFIG_$(SPL_)CLK, add a check. Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: add i.MX8MN DDR4 board supportPeng Fan2019-11-0513-3/+1956
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support pinctrl/clk/sdhc, include ddr4 timing data. Log: U-Boot SPL 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800) Normal Boot Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800) CPU: Freescale i.MX8MNano rev1.0 at 24 MHz Reset cause: POR Model: NXP i.MX8MNano DDR4 EVK board DRAM: 2 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: add dtsi for i.MX8MNPeng Fan2019-11-053-0/+1573
| | | | | | | | | | | | Add dtsi for i.MX8MN Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8m: add i.MX8MN ddr4 image cfg filePeng Fan2019-11-051-0/+17
| | | | | | | | | | | | Add cfg file for i.MX8MN DDR4 Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx: add i.MX8MN ccf driverPeng Fan2019-11-053-0/+433
| | | | | | | | | | | | | | | | | | Add i.MX8MM ccf driver support. Modifed from Linux Kernel 5.3.0-rc1, drop some entries that not used in U-Boot and adapt to U-Boot CCF style. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Lukasz Majewski <lukma@denx.de>
| * tools: imx8m_image: support ddr4 firmwarePeng Fan2019-11-051-0/+10
| | | | | | | | | | | | some boards use ddr4, not lpddr4, so we need to check ddr4 firmware. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * pinctrl: imx8m: support i.MX8MNPeng Fan2019-11-051-0/+1
| | | | | | | | | | | | Support i.MX8MN in imx8m pinctrl driver Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * tools: imx8mimage: add ROM VERSIONPeng Fan2019-11-052-2/+23
| | | | | | | | | | | | | | | | | | The IVT offset is changed on i.MX8MN. Use ROM_VERSION to pass the v1 or v2 to mkimage. v1 is for iMX8MQ and iMX8MM v2 is for iMX8M Nano (iMX8MN) Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mn: add get_boot_devicePeng Fan2019-11-051-0/+48
| | | | | | | | | | | | | | No ROM INFO structure on iMX8MN, use new ROM API to get boot device from ROM. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: cpu: restrict get_boot_devicePeng Fan2019-11-051-1/+1
| | | | | | | | | | | | | | i.MX8MN has its own get_boot_device, so restrict with i.MX8MQ and i.MX8MM. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: add rom api supportPeng Fan2019-11-054-0/+331
| | | | | | | | | | | | | | i.MX8MN support loading images with rom api, so we implement reuse board_return_to_bootrom to let ROM loading images. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: spl: use spl_board_boot_device for i.MX8MNPeng Fan2019-11-051-1/+1
| | | | | | | | | | | | i.MX8MN follow same logic as i.MX8MM, so use spl_board_boot_device Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mn: add pin headerPeng Fan2019-11-051-0/+763
| | | | | | | | | | | | Add pin header for i.MX8MN Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: add i.MX8MN PE propertyPeng Fan2019-11-051-1/+1
| | | | | | | | | | | | i.MX8MN does not have LVTTL, it has a PE property Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8mn: set BYPASS ID SWAP to avoid AXI bus errorsPeng Fan2019-11-051-1/+1
| | | | | | | | | | | | | | Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan <peng.fan@nxp.com>
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