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* ARC: HSDK: Add platform-specific commandsEugeniy Paltsev2018-04-0210-51/+1564
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support of hsdk platform-specific commands: hsdk_clock set - set clock from axi_freq, cpu_freq and tun_freq environment variables/command line arguments hsdk_clock get - save clock frequencies to axi_freq, cpu_freq and tun_freq environment variables hsdk_clock print - show CPU, AXI, DDR and TUNNEL current clock frequencies. hsdk_clock print_all - show all currently used clock frequencies. hsdk_init - setup board HW in one of pre-defined configuration (hsdk_hs34 / hsdk_hs36 / hsdk_hs36_ccm / hsdk_hs38 / hsdk_hs38_ccm / hsdk_hs38x2 / hsdk_hs38x3 / hsdk_hs38x4) hsdk_go - run baremetal application on hsdk configured by hsdk_init command. This patch changes default behaviour of 'bootm' command: now we are able to set number of CPUs to be kicked by setting 'core_mask' environment variable before 'bootm' command run. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* ARC: Bump ARC tools used in TravisCI to the most recent release arc-2017.09Alexey Brodkin2018-04-021-3/+3
| | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* ARC: AXS10x: DTS: Remove unused interrupt propertiesEugeniy Paltsev2018-04-021-5/+0
| | | | | | | | | | | | | Some device tree nodes (like ethernet, ohci, ehci) in axs10x_mb.dtsi were copied from linux device tree, so they have interrupts properties. As we don't use interrupts in uboot we don't have interrupt controller node in AXS10x device tree. In result we get warnings when we compile such device tree. So remove unused interrupts properties to get rid of this warnings. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* Merge git://git.denx.de/u-boot-marvellTom Rini2018-03-3016-92/+1088
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| * arm64: a37xx: defconfigs: enable PCI_CMD and E1000 driverKen Ma2018-03-302-0/+4
| | | | | | | | | | | | | | Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: dts: enable pcie portWilson Ding2018-03-303-0/+31
| | | | | | | | | | | | | | | | | | | | | | This patch enabled PCIe port on both devel-board and espressobin board. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Wilson Ding <dingwei@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: defconfigs: enable aardvark pcie driverWilson Ding2018-03-302-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: pci: add support for aardvark pcie driverWilson Ding2018-03-303-0/+701
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports X1 lane width. Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38725 Reviewed-by: Victor Gu <xigu@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: populate pcie memory regionWilson Ding2018-03-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch added a new region of 32MiB AT 0xe800.0000 to Armada37x0's memory map. This region is supposed to be mapped in MMU in order to enable the access to the PCI I/O or MEM resources. Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38724 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Victor Gu <xigu@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: remove old pinctrl implementationKen Ma2018-03-301-23/+0
| | | | | | | | | | | | | | | | | | | | Since the new pinctrl/gpio driver is used, so this patch removes the old board specific pin control settings. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * Revert "arm64: a37xx: dts: Add pin control nodes to DT"Ken Ma2018-03-301-14/+0
| | | | | | | | | | | | | | | | | | | | | | The commit "arm64: mvebu: Add pinctrl nodes for Armada 3700" has added new pinctrl nodes. This reverts commit f7cab0f95b05ec6a66fe4796b9ad44406d0cc864. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * doc: a37xx: Introduce pinctrl device tree bindingKen Ma2018-03-301-0/+186
| | | | | | | | | | | | | | | | | | | | | | Reviewed-on: http://vgitil04.il.marvell.com:8080/43289 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: dts: Correct mpp definitionsKen Ma2018-03-303-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corrects below mpp definitions for armada 3720 DB board and ESPRESSOBin board: - "smi" pins group is added and "smi" function is set for eth0; - Now pcie pins are used as gpio to implement PCIe function in hardware, so "pcie" group function is changed to "gpio". Reviewed-on: http://vgitil04.il.marvell.com:8080/43287 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: pinctrl: Correct mpp definitionsKen Ma2018-03-301-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corrects below mpp definitions: - The sdio_sb group is composed of 6 pins and not 5; - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6]; - Pin of group "pmic0" is mpp1[6] but not mpp1[16]; - Pin of group "pmic1" is mpp1[7] but not mpp1[17]; - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its bitmask is bit4; - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is bit5 | bit9 | bit10 but not bit4; - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to bit11 | bit12 | bit13. Reviewed-on: http://vgitil04.il.marvell.com:8080/43288 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: pinctrl: Fix gpio pin offset in registerKen Ma2018-03-301-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For armada_37xx_update_reg(), the parameter offset should be pointer so that it can be updated, otherwise offset will keep old value, and then when offset is larger than or equal to 32 the mask calculated by "BIT(offset)" will be 0 in gpio chip hook functions, it's an error, this patch set offset parameter of armada_37xx_update_reg() as pointer. Reviewed-on: http://vgitil04.il.marvell.com:8080/43287 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: pinctrl: Fix the pin 23 on south bridgeKen Ma2018-03-301-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin 23 on South bridge does not belong to the rgmii group. It belongs to a separate group which can have 3 functions. Due to this the fix also have to update the way the functions are managed. Until now each groups used NB_FUNCS(which was 2) functions. For the mpp23, 3 functions are available but it is the only group which needs it, so on the loop involving NB_FUNCS an extra test was added to handle only the functions added. The bug was visible when the gpio regulator used the gpio 23, the whole rgmii group was setup to gpio which broke the Ethernet support on the Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need the vqmmc) _and_ the Ethernet work again. Reviewed-on: http://vgitil04.il.marvell.com:8080/43284 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: dts: Fix the number of GPIO on south bridgeKen Ma2018-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of pins in South Bridge is 30 and not 29. There is a fix for the driver for the pinctrl, but a fix is also need at device tree level for the GPIO. Reviewed-on: http://vgitil04.il.marvell.com:8080/43286 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: pinctrl: Fix number of pin in south bridgeKen Ma2018-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | On the south bridge we have pin from 0 to 29, so it gives 30 pins (and not 29). Reviewed-on: http://vgitil04.il.marvell.com:8080/43285 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: dts: Add additional pinctrl definitionKen Ma2018-03-302-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mmc pins, pcie pins and sdio pins definition and do these pins' configuration for DB board and espressobin board; Add uart2 pins configuration for DB board. Reviewed-on: http://vgitil04.il.marvell.com:8080/40914 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: dts: Add pinctrl configuration for ESPRESSOBin boardKen Ma2018-03-301-0/+8
| | | | | | | | | | | | | | | | | | | | Reviewed-on: http://vgitil04.il.marvell.com:8080/40913 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: defconfig: Enable PINCTRL and GPIO support for ESPRESSOBin boardKen Ma2018-03-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch enable the PINCTRL and GPIO support, including the GPIO command on the Armada 3720 espressobin board. Reviewed-on: http://vgitil04.il.marvell.com:8080/40746 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: a37xx: dts: add gpio head file includingKen Ma2018-03-301-0/+1
| | | | | | | | | | | | | | Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: a8k: Add distro boot supportMark Kettenis2018-03-301-0/+19
| | | | | | | | | | | | | | | | | | The various load address values are taken from the a37xx configuration and match the dowstream 'u-boot-2017.03-armada-17.10' release where appropriate. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Stefan Roese <sr@denx.de>
| * kwbimage: Fix out of bounds accessAlexander Graf2018-03-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The kwbimage format is reading beyond its header structure if it misdetects a Xilinx Zynq image and tries to read it. Fix it by sanity checking that the header we want to read fits inside our file size. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * configs: clearfog: enable random random MAC addressBaruch Siach2018-03-301-0/+1
| | | | | | | | | | | | | | | | | | This makes the network devices usable when booting a blank board over UART, with no pre-configured MAC address stored in the environment area. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * dm: pcie: designware: add correct ATU handlingIgal Liberman2018-03-301-33/+58
| | | | | | | | | | | | | | | | | | | | | | | | Currently, ATU (address translation unit) implementation doesn't support translate addresses > 32 bits. This patch allows to configure ATU correctly for different memory accesses (memory, configuration and IO). The same approach is used in Linux Kernel. Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2018-03-305-8/+49
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| * | x86: zImage: Pass working device tree data to the kernelIvan Gorinov2018-03-302-2/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On x86 platforms, U-Boot does not pass Device Tree data to the kernel. This prevents the kernel from using FDT loaded by U-Boot. Read the working FDT address from the "fdtaddr" environment variable and add a copy of the FDT data to the kernel setup_data list. Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add #include <linux/libfdt.h> to zimage.c to fix build error] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: mmc: Fix mapping of BAR memoryBernhard Messerklinger2018-03-301-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use dm_pci_map_bar function for BAR mapping. This has the advantage of clearing BAR flags and and only accepting mapped memory. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | dm: pci: Avoid setting a PCI region that has 0 sizeBin Meng2018-03-301-2/+3
| | | | | | | | | | | | | | | | | | | | | It makes no sense to set a PCI region that has 0 size. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | dm: pci: Check board information pointer in decode_regions()Bin Meng2018-03-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI enumeration may happen very early on an x86 board. The board information pointer should have been checked in decode_regions() as its space may not be allocated yet. With this commit, Intel Galileo board boots again. Fixes: 664758c ("pci: Fix decode regions for memory banks") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | efi_stub: Fix GDT_NOTSYS checkAlexander Graf2018-03-301-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | The get_codeseg32() wants to know if a passed in descriptor has flag GDT_NOTSYS set (desc & GDT_NOTSYS), not whether desc and GDT_NOTSYS are not != 0 (desk && GDT_NOTSYS). This is an obvious typo. Fix it up. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge git://git.denx.de/u-boot-riscvTom Rini2018-03-3033-594/+347
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| * | riscv: ae250: Support DT provided by the board at runtimeRick Chen2018-03-304-9/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_OF_BOAD to support delivery dtb to u-boot at run time instead of embedded. There are two methods to delivery dtb. 1 Pass from loader: When u-boot boot from RAM, gdb or loader can pass dtb via a2 to u-boot dynamically. Of course gdb or loader shall be in charge of dtb delivery. 2 Configure CONFIG_SYS_FDT_BASE: It can be configured as RAM or ROM base statically, no mater u-boot boot from RAM or ROM. If it was configured as ROM base, dtb can be burned into ROM(spi flash) by spi driver. Meanwhile remove CONFIG_SKIP_LOWLEVEL_INIT which is useless in nx25-ae250 configuration. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | configs: Drop CONFIG_MMC_NDS32Rick Chen2018-03-303-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove CONFIG_MMC_NDS32 from the three config (adp-ae3xx_defconfig, adp-ag101p_defconfig, nx25-ae250_defconfig). Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | mmc: ftsdc010: Merge nds32_mmc to ftsdc010Rick Chen2018-03-305-165/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nsd32_mmc was created to support ftsdc010 dm. It is not necessary to separate both, so merge it to ftsdc010. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | mmc: ftsdc010: Migrate CONFIG_FTSDC010_SDIO to KconfigRick Chen2018-03-308-16/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert CONFIG_FTSDC010_SDIO to Kconfig. So CONFIG_FTSDC010_SDIO can also be removed from config_whitelist.txt. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | Drop CONFIG_FTSDC010_NUMBERRick Chen2018-03-304-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_FTSDC010_NUMBER was not used anymore, can be removed now. So CONFIG_FTSDC010_NUMBER can also be removed from config_whitelist.txt. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | Drop CONFIG_FTSDC010_BASERick Chen2018-03-304-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After drop non-dm code of ftsdc010, the sd register base definition can be droppped now. So CONFIG_FTSDC010_BASE and CONFIG_FTSDC010_BASE_LIST both can be removed from config_whitelist.txt Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | board: Drop ftsdc010 non-dm codeRick Chen2018-03-303-33/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove board_mmc_init() in adp-ag101p, adp-ae3xx and nx25-ae250 boards. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | mmc: ftsdc010: Drop non-dm codeRick Chen2018-03-302-103/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only three defconfig(adp-ag101p_defconfig, adp-ae3xx_defconfig, nx25-ae250_defconfig) set CONFIG_FTSDC010=y. And they all also enable CONFIG_DM_MMC. So the non-dm code of ftsdc010 can be dropped now. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
| * | nds32: dts: AG101P support sd High-Speed modeRick Chen2018-03-301-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable High-Speed mode with cap-sd-highspeed in dts Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
| * | riscv: dts: AE250 support sd High-Speed modeRick Chen2018-03-301-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable High-Speed mode with cap-sd-highspeed in dts. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
| * | mmc: ftsdc010: Support High-Speed modeRick Chen2018-03-301-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ftsdc010 dm driver has been disable High-Speed mode as default to work around Andes AE3XX platform's problem, because of it does not support High-Speed mode in commit id 73cd56b2df213c629191139e5c6705e069b6214f. But other platforms or SoCs maybe support this function. So High-Speed mode can be enabled from dts with cap-mmc-highspeed or cap-sd-highspeed property. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
| * | doc: ae250: Describe riscv-linux booting via u-bootRick Chen2018-03-301-5/+143
| | | | | | | | | | | | | | | | | | | | | | | | Simply record riscv-linux booting steps and messages from bbl via u-boot on QEMU in README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
| * | tools: mkimage: Support RISC-V archRick Chen2018-03-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add riscv uimage arch to support riscv-linux booting. It can Convert riscv-linux to image which can be booted by bootm command. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
| * | riscv: bootm: Remove ATAGSRick Chen2018-03-302-226/+2
| | | | | | | | | | | | | | | | | | | | | | | | ATAGS is not supported and will be replaced by DT in riscv-linux. So can be removed now. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
| * | riscv: bootm: Support to boot riscv-linuxRick Chen2018-03-301-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | riscv-linux should use BBL (Berkeley bootloader) for loading the Linux kernel. U-Boot can play as FSBL(first stage bootloader) to boot BBL and riscv-linux. In BBL's init_first_hart(), it will pass dtb with a1. So implement bootm to pass arguments to BBL correctly. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
| * | riscv: checkpatch: Fix static const char * array declarationsRick Chen2018-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is reported by checkpatch.pl WARNING: static const char * array should probably be static const char * const Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
| * | riscv: checkpatch: Fix missing a blank line after declarationsRick Chen2018-03-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | It is reported by checkpatch.pl WARNING: Missing a blank line after declarations. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com>
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