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* arm64: zynqmp: Enable MP by default via KconfigMichal Simek2018-10-1623-19/+4
| | | | | | | Simplify defconfig for ZynqMP but keep option not to enable it for mini targets. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Add new command for TCM initializationSiva Durga Prasad Paladugu2018-10-163-3/+43
| | | | | | | | | | | This patch adds new zynqmp command "zynqmp tcminit mode" to initialize TCM. TCM needs to be initialized before accessing to avoid ECC errors. This new command helps to perform the same. It also makes tcm_init() as global and uses it for doing the TCM initialization. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Move TCM initialization to a separate routineSiva Durga Prasad Paladugu2018-10-161-2/+8
| | | | | | | | | This patch moves TCM initialization to a separate routine to make it modular and can be reused if required. It also prints warning message now as it writes to TCM. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Add Xilinx Versal Virtual QEMU boardMichal Simek2018-10-163-0/+87
| | | | | | | | | Virtual QEMU board is generating DTB self and putting it to VERSAL_QEMU_DTB_ADDR address. Board is using CONFIG_OF_BOARD which ensures that u-boot is aligned with board created by QEMU. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Do not setup any clock for Xilinx SoC VersalMichal Simek2018-10-161-0/+4
| | | | | | | Xilinx SoC Versal is using fixed clock where setting rate is not supported. That's why workaround the driver till real clock driver is supported. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek2018-10-1619-7/+402
| | | | | | | | | | | | | | | | | | Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: gic: Do gicv3 secure initialization based on EL levelMichal Simek2018-10-161-7/+9
| | | | | | | Do gic cpu initialization based on EL level which u-boot enters. U-Boot can't access EL3 regs when runs in EL2/EL1, etc. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: zynqmp: Enable CDC ethernet gadget for zcu100/Ultra96Michal Simek2018-10-162-0/+10
| | | | | | | | | | | | | | | | | Ethernet is not present on this board that's why there are two other options how to wire the board to ethernet. The first is asix_eth usb host converter which is already enabled by default. The second option is to use USB CDC/RNDIS ethernet gadget. This patch is enabling CDC which is working with Linux. With new bind/unbind command there is no need to call usb_ether_init() from platform code and use for example these commands: bind /amba/usb0@ff9d0000/dwc3@fe200000 usb_ether dhcp unbind /amba/usb0@ff9d0000/dwc3@fe200000 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* xilinx: Sync defconfigs with current KconfigMichal Simek2018-10-163-3/+3
| | | | | | There are some inconsistencies which should be fixed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: Add efuse node for Zynq-7000S devicesMichal Simek2018-10-161-0/+5
| | | | | | Add access to efuse for Zynq-7000S device detection. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: Add support for DLC20 boardMichal Simek2018-10-164-0/+458
| | | | | | | | | Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB), USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each). Boards have mix of Winbond/ST QSPIs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: Enable FIT fpga loading in SPL for zc706Michal Simek2018-10-161-0/+4
| | | | | | Enable loading FPGA from FIT image in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* spl: fpga: Implement fpga bistream loading with fpga_loadMichal Simek2018-10-161-18/+16
| | | | | | | | | | | | | | | | This patch partially reverts: "spl: fit: Add support for loading FPGA bitstream" (sha1: 26a642238bdecc53527142dc043b29e21c5cc94c) There shouldn't be a need to call private spl_load_fpga_image function because the whole sequence should be already handled by fpga framework. If there is missing loading bistream by chunks it should be done via fpga framework instead of having private hooks. Also spl_load_fpga_image() weak function is not used anywhere and opening a way for not reviewed hacks out of mainline U-Boot is not the right way to go. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Prepare v2018.11-rc2v2018.11-rc2Tom Rini2018-10-151-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Revert "fdt: fdtdec_setup_memory_banksize() use livetree"Michal Simek2018-10-151-21/+23
| | | | | | | | | This reverts commit c35a7d375ec8f0a8ee343ae4868be3242172632e. This commit is breaking SPL on zc706. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrice Chotard <patrice.chotard@st.com> [on STM32F746-disco]
* Merge tag 'arc-more-updates-for-2018.11-rc2-2' of git://git.denx.de/u-boot-arcTom Rini2018-10-157-9/+72
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More fixes and improvements for ARC here: Fixes (this time included for real): * Take care of global uninitialized variables They used to be put right after .bss section and were never zeroed as they should be. Now merged with normal .bss Improvements: * Print more verbose CPU info for boards built on real silicon * Add support for SD-card detection on all ARC boards * Quite a few fixes for IoT DK - Support reset by command - Print of CPU freq on boot - Link for eFlash etc
| * ARC: Don't use COMMON section for global not-initialized variablesAlexey Brodkin2018-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default GCC puts global non-initialized variables in COMMON section. And we used to ignore existence of COMMON section in our linker scripts though smart LD silently appended it right after .bss. And the problem here is variables from COMMON section even though require zeroing in run-time were not zeroed as they were placed right after __bss_end symbol. It was a pure luck we never faced serious problem due to this, but now it is fixed. Now as for some other architectures we'll just force GCC to put those global variables in normal .bss section. This solution is much nicer than adding COMMON section to each and every linker script. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * iot_dk: Link for eFlashAlexey Brodkin2018-10-121-1/+1
| | | | | | | | | | | | | | | | | | That's what we'll have in production. But note it won't work for loading via JTAG as eFlash is not directly writable, one needs to use prebootloader to flash uboot.bin from SD-card into eFlash. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * axs10x/emdk/hsdk/iot_dk: Implement board_mmc_getcd()Alexey Brodkin2018-10-124-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So now we may detect MMC/SD-card existence and instead of completely misleading message on missing card: ------------------------>8----------------------- Loading Environment from FAT... Card did not respond to voltage select! ------------------------>8----------------------- we now get very clear one: ------------------------>8----------------------- Loading Environment from FAT... MMC: no card present ------------------------>8----------------------- Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * iot_dk: Save CPU clock value to gd->cpu_clkAlexey Brodkin2018-10-121-6/+8
| | | | | | | | | | | | | | Since gd->cpu_clk is a global item we may once populate it from .dtb ans use it then in other places like for printing CPU info etc. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * iot_dk: Add support of 136 MHz clockAlexey Brodkin2018-10-121-0/+8
| | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * iot_dk: Implement board resetAlexey Brodkin2018-10-121-0/+8
| | | | | | | | | | | | It is done by writing some magic sequence in a special register. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * iot_dk/hsdk: Implement its own print_cpuinfo()Alexey Brodkin2018-10-122-0/+16
| | | | | | | | | | | | | | | | | | ARC IDENTITY register only encodes major architecture type and version while for a particular board/silicon we may know better which template was used and so we may identify CPU more precise, which exactly we do here. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * ARC: make generic print_cpuinfo() weakAlexey Brodkin2018-10-121-1/+1
| | | | | | | | | | | | | | | | | | | | This allows board to override print_cpuinfo() because they might know better which ARChitect template was used. This way we may not only derive base architecture type and version but more meaningful things like "ARC EM7D" instead of simple "ARC EM", "ARC HS36" instead of "ARC HS". Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * iot_dk: Disable networking supportAlexey Brodkin2018-10-121-1/+1
| | | | | | | | | | | | | | | | | | | | There's no Ethernet controller on the board so no point in having networking support. This also saves us 5.5 kB of precious memory. | # bloat-o-meter u-boot.net u-boot.no_net_regex | tail -1 | Total: Before=127892, After=122334, chg -4.35% Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * iot_dk: Add localversion stringAlexey Brodkin2018-10-121-0/+1
| | | | | | | | Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Merge git://git.denx.de/u-boot-sunxiTom Rini2018-10-122-1/+8
|\ \ | | | | | | | | | | | | [trini: Convert da850evm_nand defconfig now to to SPL_DM] Signed-off-by: Tom Rini <trini@konsulko.com>
| * | sunxi: fix DRAM gate/reset sequence of H6Icenowy Zheng2018-10-101-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the DRAM bus gate and reset is changed at the same time in H6 DRAM initialization code, which disobeys the user manual's programming guide. Fix the sequence by follow the sequence suggested by the user manual (ungate the bus clock after release the reset signal). By some experiments it seems to fix the DRAM size detection failure that rarely happens. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2018-10-129-23/+87
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| * | | sf: Add MICRON manufacturer idAshish Kumar2018-10-122-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NOR flash name MT35X_QLKA and MT25Q_** used on NXP board has manufacturer id as 0x2C, which are rather for newer flashes after the split of Micron from ST. So macro for this micron manufacturer id. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [jagan: updated commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | board: da8xxevm: Add SPL DM for serial, spiJagan Teki2018-10-104-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add SPL DM support for da8xxevm boards with SPL serial, SPI drivers supported via platdata. Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Adam Ford <aford173@gmail.com> #da850evm
| * | | spi: davinci: Add platdata supportJagan Teki2018-10-102-19/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Davanci spi driver has DM support already, this patch add support for platdata so-that SPL can use it for low foot-print. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Adam Ford <aford173@gmail.com>
| * | | mtd: uboot: Fix hanging during mtd list commandAdam Ford2018-10-101-1/+8
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards (like omap3_logic) hang when trying to access address 0. This happens when executing the new 'mtd list' command. This patch enhances the checks for conditions that would preclude mtd_probe_devices() from operating. Fixes: 5db66b3aee6f ("cmd: mtd: add 'mtd' command") Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
* | | ldpaa_eth.c: Fix warning when PHYLIB is not enabledTom Rini2018-10-121-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | We need to #ifdef some variables to avoid warning about them being unused. Fixes: 1a048cd65645 ("driver: net: fsl-mc: Add support of multiple phys for dpmac") Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2018-10-1139-409/+1294
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| * | driver: net: fsl-mc: Add support of multiple phys for dpmacPankaj Bansal2018-10-107-109/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Till now we have had cases where we had one phy device per dpmac. Now, with the upcoming products (LX2160AQDS), we have cases, where there are sometimes two phy devices for one dpmac. One phy for TX lanes and one phy for RX lanes. to handle such cases, add the support for multiple phys in ethernet driver. The ethernet link is up if all the phy devices connected to one dpmac report link up. also the link capabilities are limited by the weakest phy device. i.e. say if there are two phys for one dpmac. one operates at 10G without autoneg and other operate at 1G with autoneg. Then the ethernet interface will operate at 1G without autoneg. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: fsl-mc: initialize dpmac irrespective of phyPankaj Bansal2018-10-101-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The dpmac initalization should not depend on phy. As the phy is not necessary to be present for dpmac to function. Therefore, remove dpmac initialization dependency from phy. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: fsl-mc: Modify the dpmac link detection methodPankaj Bansal2018-10-101-62/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when there is no phy present for a dpmac, a dummy phy device is created. when we move to multiple phy method, we need to create as many dummy phy devices. Change this method so that we don't need to create dummy phy devices. We always report linkup if no phy is present. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: fsl-mc: fix error handing in init_phyPankaj Bansal2018-10-101-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | if an error occurs during init_phy, we should free the phydev structure which has been allocated by phy_connect. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: fsl-mc: remove unused strcture elementsPankaj Bansal2018-10-104-28/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phydev structure is present in both ldpaa_eth_priv and wriop_dpmac_info. the phydev in wriop_dpmac_info is not being used As the phydev is created based on phy_addr and bus members of wriop_dpmac_info, it is appropriate to keep phydev in wriop_dpmac_info. Also phy_regs is not being used, therefore remove it Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: fsl-mc: modify the label namePankaj Bansal2018-10-101-4/+4
| | | | | | | | | | | | | | | | | | | | | The goto label name is misspelled it should be DPMAC not DPAMC Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: Consolidate UDP header functionsDuncan Hare2018-10-103-16/+32
| | | | | | | | | | | | | | | | | | | | | | | | Make it possible to add TCP versions of the same, while reusing IP portions. This patch should not change any behavior. Signed-off-by: Duncan Hare <DH@Synoia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: Don't overwrite waiting packets with asynchronous repliesJoe Hershberger2018-10-106-10/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Peter originally sent a fix, but it breaks a number of other things. This addresses the original reported issue in a different way. That report was: > U-Boot has 1 common buffer to send Ethernet frames, pointed to by > net_tx_packet. When sending to an IP address without knowing the MAC > address, U-Boot makes an ARP request (using the arp_tx_packet buffer) > to find out the MAC address of the IP addressr. When a matching ARP > reply is received, U-Boot continues sending the frame stored in the > net_tx_packet buffer. > > However, in the mean time, if U-Boot needs to send out any network > packets (e.g. replying ping packets or ARP requests for its own IP > address etc.), it will use the net_tx_packet buffer to prepare the > new packet. Thus this buffer is no longer the original packet meant > to be transmitted after the ARP reply. The original packet will be > lost. This instead uses the ARP tx buffer to send async replies in the case where we are actively waiting for an ARP reply. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reported-by: Tran Tien Dat <peter.trantiendat@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | test: eth: Add a test for the target being pingedJoe Hershberger2018-10-103-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The target will respond to pings while doing other network handling. Make sure that the response happens and is correct. This currently corrupts the ongoing operation of the device if it happens to be awaiting an ARP reply of its own to whatever serverip it is attempting to communicate with. In the test, add an expectation that the user operation (ping, in this case) will fail. A later patch will address this problem. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | test: eth: Add a test for ARP requestsJoe Hershberger2018-10-103-0/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This tests that ARP requests made to this target's IP address are responded-to by the target when it is doing other networking operations. This currently corrupts the ongoing operation of the device if it happens to be awaiting an ARP reply of its own to whatever serverip it is attempting to communicate with. In the test, add an expectation that the user operation (ping, in this case) will fail. A later patch will address this problem. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: sandbox: Add a priv ptr for tests to useJoe Hershberger2018-10-102-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Tests need to be able to pass their "unit test state" to the handlers where asserts are evaluated. Add a function that allows the tests to set this private data on the sandbox eth device. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: Add an accessor to know if waiting for ARPJoe Hershberger2018-10-102-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | This single-sources the state of the ARP. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: sandbox: Allow fake eth to handle more than 1 packet responseJoe Hershberger2018-10-102-15/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use up to the max allocated receive buffers so as to be able to test more complex situations. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: sandbox: Share the priv structure with testsJoe Hershberger2018-10-102-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | If tests want to implement tx handlers, they will likely need access to the details in the priv structure. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | net: sandbox: Make the fake eth driver response configurableJoe Hershberger2018-10-102-4/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the send handler registerable so tests can check for different things. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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