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* phy: marvell: add IGNORE COMPHY typeStefan Roese2017-05-094-2/+11
| | | | | | | | | | | | | | This type tells u-boot to preserve the COMPHY settings as is it is usefull in situations where the COMPHY was initialized by earlier firmware. Note that IGNORE is different from UNCONNECTED since setting UNCONNECTED type will disconnect the COMPHY in the COMPHY MUX which is a desired behaviour Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* phy: marvell: cp110: update utmi phy connection typeStefan Roese2017-05-094-8/+9
| | | | | | | | | | | UTMI_PHY_TO_USB_HOST was used in USB3 UTMI dts node only, but there will be USB2 UTMI dts node for some SoCs that have got USB2 controller, so rename TO_USB_HOST to TO_USB3_HOST to distinguish TO_USB2_HOST in later on patches. Signed-off-by: zachary <zhangzg@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* phy: marvell: cp110: add support for end point configurationStefan Roese2017-05-093-6/+13
| | | | | | | | | | | | The serdes was always configured in root complex mode. this patch add new entry in device tree (per serdes) which indicates whether the serdes is in end point mode. if so, it skips the root complex configuration. Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* phy: marvell: Replace PHY_TYPE_KR with PHY_TYPE_SFIStefan Roese2017-05-095-20/+20
| | | | | | | | Use correct naming as done in the latest Marvell U-Boot version as well. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* fix: mvebu_ comphy: Update COMPHY sequence numberKonstantin Porotchkin2017-05-091-1/+2
| | | | | | | | | | | | | | | | | Use local static counter for maintaining the COMPHY chip-ID upon its initialization. The dev->seq originally used as the COMPHY chip-ID depends on the device tree scan order and produces wrong results that breaks the deficated PHYs init flow, which in turn breaks the USB support. Change-Id: I4e3f7ec36590a7f95dc94d9269a3c47fb708c4a9 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: mvebu: Minor fixes in the AXP / A38x SERDES codeUwe Kleine-König2017-05-094-8/+5
| | | | | | | | | - Fix spelling error of SERDES_VERSION - Remove superfluous definition of this macro - Remove unnecessary include of i2c.h Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: a8k: Add NAND configuration parametersKonstantin Porotchkin2017-05-092-0/+83
| | | | | | | | | | | Add NAND configuration parameters to A8K shared config file. Add defconfig for db-88f7040 board with boot from NAND setup. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* arm64: a8k: dts: Add support for NAND devices on A8K platformKonstantin Porotchkin2017-05-094-0/+239
| | | | | | | | | | | | Add NAND to CP master device tree. Add armada-7040-db-nand device tree for the board configured with NAND boot device. Add comment about boot device ID to armada-7040-db DTS. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: a8k: Add support for NAND clock getKonstantin Porotchkin2017-05-091-0/+18
| | | | | | | | | | | Implement mvebu_get_nand_clock call for A8K family. This function is used by PXA3XX NAND driver. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: Trigger PCI devices scan at early init stageKonstantin Porotchkin2017-05-091-0/+6
| | | | | | | | | | | | | Add PCIe initialization at early init stage. This operation has a side effect of detecting all PCIe plug-in cards, so the operator is not obligated to issue "pci enum" command though CLI for this purpose. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* mvebu: dts: a80x0: Sync the DB DTS with standard config AKonstantin Porotchkin2017-05-091-107/+115
| | | | | | | | | | | | | | | | Sync the default configuration of Armada-8040-DB with Marvell u-boot-2015 standard configuration "A" for the same board. The standard configuration "A" enables 2 PCIe slots on CP0 and 3 PCIe slots on CP1. This is the main configuration used for u-boot and Linux tests. This patch also re-arranges the DTS file entries by grouping all nodes related to CP0 and CP1. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* fix: mvebu: pcie_dw: Allow probing empty PCIe slotsKonstantin Porotchkin2017-05-091-5/+5
| | | | | | | | | | | | | | | This patch allows probing all PCIe nodes defined in DTS even if there no device connected to such node (no link). Without this fix the driver returns -ENODEV when the PCIe link is down. As result the pci_init function stops scanning bus on first empty PCIe slot and all devices located in higher numbered buses are not discovered. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
* net: mvpp2: Add remove function that is called before the OS is startedStefan Roese2017-05-091-0/+24
| | | | | | | | | | | | | | This patch adds a remove function to the mvpp2 ethernet driver which is called before the OS is started, doing: - Allocate the used buffers back from the buffer manager - Stop the BM activity Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'next' of git://git.denx.de/u-boot-spiTom Rini2017-05-081-56/+36
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| * env_sf: use DIV_ROUND_UP to calculate number of sectors to eraseAndreas Fenkart2017-05-031-13/+5
| | | | | | | | | | | | | | | | | | simpler to read Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
| * env_sf: re-order error handling in single-buffer env_relocate_specAndreas Fenkart2017-05-031-9/+11
| | | | | | | | | | | | | | | | | | this makes it easier comparable to the double-buffered version Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
| * enf_sf: reuse setup_flash_device instead of open coding itAndreas Fenkart2017-05-031-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | setup_flash_device selects one of two code paths depending on the driver model being used (=CONFIG_DM_SPI_FLASH). env_relocate_spec only used the non driver-model code path. I'm unsure why, either none of the platforms that need relocation use the driver model, or - worse - the driver model is not yet usable when relocating. Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
| * env_sf: factor out prepare_flash_deviceAndreas Fenkart2017-05-031-29/+19
| | | | | | | | | | | | | | | | | | copy&paste code found in single/double buffered code path Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@openedev.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-05-0820-124/+979
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| * | sunxi: add support for Banana Pi M2 Plus boardIcenowy Zheng2017-05-042-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Banana Pi M2 Plus is an Allwinner H3-based SBC by Sinovoip, which has already mainline device tree file that have landed into U-Boot source tree. Add a defconfig file for it and add the MAINTAINERS items. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | sunxi: enable SATA on Banana Pi M2 UltraIcenowy Zheng2017-05-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Banana Pi M2 Ultra has a SATA port connected to the internal SATA controller of R40 SoC. The controller's 1.2v VDD is connected to ELDO3 and the 2.5v VDD is connected to DLDO4. Enable these regulators as well as the SATA support of Banana Pi M2 Ultra, by adding needed config lines into its defconfig. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | sunxi: add clock configuration of R40 sataIcenowy Zheng2017-05-022-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R40 has a similar SATA controller with the ones on A10/A20, but with a reset line added (like other peripherals on sun6i+), and two extra VDD pins added (1.2v and 2.5v). Add clock configuration of R40 SATA. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: use imply instead of bare default y in KconfigMasahiro Yamada2017-05-022-26/+8
| | | | | | | | | | | | | | | | | | | | | Fix annoying config redefines in SoC/board level Kconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: move board/sunxi/Kconfig to arch/arm/mach-sunxi/KconfigMasahiro Yamada2017-05-022-1/+2
| | | | | | | | | | | | | | | | | | | | | For the consistent location of SoC-level Kconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | sunxi: Disable DE2 video driver where not neededJernej Skrabec2017-04-283-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because DE2 driver is enabled by default, it is nice to disable it on all boards which don't have any video output. List of such boards is also much shorter. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | sunxi: video: Add A64/H3/H5 HDMI driverJernej Skrabec2017-04-287-0/+795
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for HDMI output. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | sunxi: Enable DM_I2C for A64/H3/H5Jernej Skrabec2017-04-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commits enable DM I2C support for A64/H3/H5 SoCs. It is not enabled globaly for all sunxi SoCs, because some boards use PMICs which are connected through I2C. In order to keep same functionality, PMIC drivers needs to be ported to DM too. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | sunxi: i2c: Add support for DM I2CJernej Skrabec2017-04-284-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for DM I2C on sunxi platform. It can coexist with old style sunxi I2C driver, because it is still used in SPL and by some SoCs. Because sunxi platform doesn't yet support DM clk, reset and pinctrl driver, workaround is needed to enable clocks and set resets and pinctrls. This is done by calling i2c_init_board() in board_init(). This means that CONFIG_I2Cx_ENABLE options needs to be correctly set in order to use needed I2C controller. Commit is based on the previous patch made by Philipp Tomsich Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | sunxi: Move function for later convenienceJernej Skrabec2017-04-281-94/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit only moves i2c_init_board() function almost to the top and doesn't have any functional changes. This is needed for a temporary workaround in next commit when support for DM I2C will be introduced. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | sunxi: power: Compile sy8106a driver only during SPL buildJernej Skrabec2017-04-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver for that regulator is used only in SPL and it uses old I2C interface. If we want to use DM I2C in U-Boot proper, compilation of this driver has to be limited only to SPL. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | ARM: keystone2: Add support for getting external clock dynamicallyLokesh Vutla2017-05-087-30/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One some keystone2 platforms like K2G ICE, there is an option to switch between 24MHz or 25MHz as sysclk. But the existing driver assumes it is always 24MHz. Add support for getting all reference clocks dynamically by reading boot pins. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: k2g: Add support for dynamic programming of PLL based on SYSCLKLokesh Vutla2017-05-083-23/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | K2G supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configured based on this sysclock frequency. Add PLL configurations for all supported sysclk frequencies. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | configs: ks2: Enable TI_COMMON_CMD_OPTIONSLokesh Vutla2017-05-087-106/+31
| | | | | | | | | | | | | | | | | | | | | Enable TI_COMMON_CMD_OPTIONS on all keystone2 platforms. Also sync with savedefconfig. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | configs: dra7xx: Enable TI_COMMON_CMD_OPTIONSLokesh Vutla2017-05-082-44/+2
| | | | | | | | | | | | | | | | | | | | | Enable TI_COMMON_CMD_OPTIONS on all dra7xx platforms. Also sync with savedefconfig. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | configs: am57xx: Enable TI_COMMON_CMD_OPTIONSLokesh Vutla2017-05-082-42/+3
| | | | | | | | | | | | | | | | | | | | | Enable TI_COMMON_CMD_OPTIONS on all am57xx platforms. Also sync with savedefconfig Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | configs: am43xx: Enable TI_COMMON_CMD_OPTIONSLokesh Vutla2017-05-082-38/+2
| | | | | | | | | | | | | | | | | | | | | Enable TI_COMMON_CMD_OPTIONS on all am43xx platforms. Also sync with savedefconfig. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | configs: am335x: Enable TI_COMMON_CMD_OPTIONSLokesh Vutla2017-05-087-69/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable TI_COMMON_CMD_OPTIONS on all am335x platforms. Also sync with savedefconfig. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Re-sync, add in boneblack*, evm_hs_{norboot,spiboot,usbspl} configs] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | board: ti: Define Kconfig symbol for common cmd optionsLokesh Vutla2017-05-081-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of defining command options in every defconfig, define a common Kconfig symbol that consolidates all command options that are supported by any TI platform. Also use imply keyword so that that specific option can be disabled if not required. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Add ARM errata workaround 852421 and 852423 for Cortex-A17Nisal Menuka2017-05-082-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2 revisions of Cortex-A17 processors. These workarounds exist in Linux kernel and I thought it would be better to add them in to U-Boot. Signed-off-by: Nisal Menuka <nisalmenuka23@gmail.com>
* | | aspeed: Cleanup ast2500-u-boot.dtsi Device Treemaxims@google.com2017-05-081-20/+21
| | | | | | | | | | | | | | | | | | | | | | | | Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | aspeed: Refactor SCU to use consistent mask & shiftmaxims@google.com2017-05-083-29/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor SCU header to use consistent Mask & Shift values. Now, consistently, to read value from SCU register, mask needs to be applied before shift. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | aspeed: Add support for Clocks needed by MACsmaxims@google.com2017-05-084-33/+304
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for clocks needed by MACs to ast2500 clock driver. The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and PCLK_MAC2 for MAC1 and MAC2 respectively. The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed SDK. It is not entirely clear from the datasheet how this clock is used by MACs, so not clear if the rate would ever need to be different. So, for now, hardcoding it is probably safer. The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through hardware strapping. So, the network driver would only need to enable these clocks, no need to configure the rate. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | aspeed: Enable I2C in EVB defconfigmaxims@google.com2017-05-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Enable I2C driver in ast2500 Eval Board defconfig. Also enable i2c command. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | aspeed: Add I2C Drivermaxims@google.com2017-05-084-0/+499
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Device Model based I2C driver for ast2500/ast2400 SoCs. The driver is very limited, it only supports master mode and synchronous byte-by-byte reads/writes, no DMA or Pool Buffers. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* | | aspeed: Add P-Bus clock in ast2500 clock drivermaxims@google.com2017-05-082-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add P-Bus Clock support to ast2500 clock driver. This is the clock used by I2C devices. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | aspeed: Enable Pinctrl Driver in AST2500 EVBmaxims@google.com2017-05-081-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable Pinctrl Driver in AST2500 Eval Board's defconfig Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | aspeed: AST2500 Pinctrl Drivermaxims@google.com2017-05-086-0/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver uses Generic Pinctrl framework and is compatible with the Linux driver for ast2500: it uses the same device tree configuration. Not all pins are supported by the driver at the moment, so it actually compatible with ast2400. In general, however, there are differences that in the future would be easier to maintain separately. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | aspeed: Refactor AST2500 RAM Driver and Sysreset Drivermaxims@google.com2017-05-086-112/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change switches all existing users of ast2500 Watchdog to Driver Model based Watchdog driver. To perform system reset Sysreset Driver uses first Watchdog device found via uclass_first_device call. Since the system is going to be reset anyway it does not make much difference which watchdog is used. Instead of using Watchdog to reset itself, SDRAM driver now uses Reset driver to do that. These were the only users of the old Watchdog API, so that API is removed. This all is done in one change to avoid having to maintain dual API for watchdog in between. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | aspeed: Device Tree configuration for Reset Drivermaxims@google.com2017-05-083-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | Add Reset Driver configuration to ast2500 SoC Device Tree and bindings for various reset signals Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | aspeed: Reset Drivermaxims@google.com2017-05-084-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to perform resets and thus depends on it. The actual Watchdog device used needs to be configured in Device Tree using "aspeed,wdt" property, which must be WDT phandle, for example: rst: reset-controller { compatible = "aspeed,ast2500-reset"; aspeed,wdt = <&wdt1>; } Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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