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* riscv: configs: AE350 will use CONFIG_OF_SEPARATE when boots from flashRick Chen2019-05-094-7/+3
| | | | | | | | | | | | | When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of CONFIG_OF_BOARD. Also remove unused code about prior_stage_fdt_address. And modify CONFIG_SYS_FDT_BASE as flash address. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when boots from ramRick Chen2019-05-092-2/+2
| | | | | | | | | | When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead of CONFIG_OF_BOARD. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ↵Rick Chen2019-05-092-0/+4
| | | | | | | | | | | | | | | enabled This patch will fix prior_stage_fdt_address write failure problem, when AE350 boots from flash. When AE350 boots from flash, prior_stage_fdt_address will be flash address, we shall avoid it to be written. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: configs: Support AE350 SMP booting from flash flowRick Chen2019-05-093-0/+77
| | | | | | | | | Add two defconfigs to support AE350 SMP booting from flash. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
* riscv: Introduce CONFIG_XIP to support booting from flashRick Chen2019-05-096-0/+21
| | | | | | | | | | | | | When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: qemu: Use correct SYS_TEXT_BASE for S-mode on 32bit systemAnup Patel2019-05-091-1/+2
| | | | | | | | | | | | | | | | | For 32bit system, the OpenSBI (or BBL) will jump to 0x80400000 address in S-mode whereas for 64bit system it will jump to 0x80200000 address in S-mode. Currently, the S-mode U-Boot sets SYS_TEXT_BASE to 0x80200000 for both 32bit and 64bit system. This breaks S-mode U-Boot for 32bit system. This patch sets different SYS_TEXT_BASE for 32bit and 64bit system so that S-mode U-Boot works fine for both. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Karsten Merker <merker@debian.org>
* riscv: qemu-riscv.h: define CONFIG_PREBOOT (enables extlinux)David Abdurachmanov2019-05-091-0/+4
| | | | | | | | | | | | | | | | - Set fdt_addr variable, which is needed for extlinux to find FDT. Otherwise booting kernel using extlinux results in missing FDT. - Also run fdt addr with FDT address so that fdt commands would work out of the box in U-Boot prompt. This is successfully used by Fedora/RISCV with 5.1-rc3+ kernel using OpenSBI -> U-Boot (S-mode) [extlinux] -> Kernel setup. Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: set CONFIG_SYS_BOOTM_LEN to SZ_64MDavid Abdurachmanov2019-05-091-6/+6
| | | | | | | | | | | | | | After updating Fedora/RISCV kernel to 5.1-rc3+ the size increased above the current threshold. Looking into HiKey, Dragonboards, etc. seems that SZ_64M is a popular option. This sucessfully boots Fedora/RISCV with 5.1-rc3+ kernel on QEMU 4.0 (master) with OpenSBI -> U-Boot (S-mode) [extlinux] -> Kernel setup. Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2019-05-0820-59/+794
|\ | | | | | | | | | | | | | | | | - H6 Beelink GS1 board (Clément) - Olimex A64-Teres-I board (Jonas) - sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej) - Change include order (Jagan) - EPHY clock changes (Jagan) - EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)
| * sunxi: Enable EMAC on the Bananapi M3Chen-Yu Tsai2019-05-091-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Bananapi M3 has an RTL8211E PHY connected to the EMAC using RGMII. The PHY is powered by DCDC1 through SW @ 3.3V. The board is designed to use 3.3V with RGMII, instead of the standard reduced voltage of 2.5V we see everywhere. DLDO3, which provides the I/O voltages, is raised to match. This patch enables the EMAC and Realtek PHY drivers in the defconfig. The device tree file already has the EMAC enabled. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Enable EMAC on the Cubietruck PlusChen-Yu Tsai2019-05-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The Cubietruck Plus has an RTL8211E PHY connected to the EMAC using RGMII. The PHY is powered by DLDO4 @ 3.3V, while the I/O pins are powered by DLDO3 @ 2.5V. This patch enables the EMAC and Realtek PHY drivers in the defconfig. The device tree file already has the EMAC enabled. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sun50i: a64: Add Olimex A64-Teres-I board initial supportJonas Smedegaard2019-05-095-1/+341
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Olimex A64-Teres-I board is a mainboard (the only one so far) for Olimex Teres-I DIY laptop kit. Key features: - Allwinner A64 Cortex-A53 - Mali-400MP2 GPU - AXP803 PMIC - 2GB DDR3 RAM - MicroSD Slot - 16GB eMMC Flash - eDP LCD display - HDMI - USB Host - Battery management - 5V DC power supply - Certified Open Source Hardware (OSHW) Works: - i2C - MMC/SD - PWM backlight Known broken: - Internal keyboard (seems to be because the keyboard firmware loads a bootloader first, and then disconnects bootloader and connect real keyboard). External ones connected to the USB port work fine. This patch enables support for the A64-Teres-I board to u-boot, including enabling screen backlight (lacking from Linux device-tree). Linux commit details about the sun50i-a64-teres-i.dts sync: "arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins" (sha1: d91ebb95b96c8840932dc3a10c9f243712555467) Cosmetic warnings regarding whitespace and placement of SPDX notice for dts file was ignored. config and .dtsi file are adapted from pinebook files. Tested-by: Jonas Smedegaard <dr@jones.dk> Signed-off-by: Jonas Smedegaard <dr@jones.dk> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: move board entry in MAINTAINERS file at proper position] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Add EPHY CLK and RESET supportJagan Teki2019-05-091-17/+57
| | | | | | | | | | | | | | | | | | | | | | Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * test/dm: reset: Add reset_get_by_index[_nodev] testJagan Teki2019-05-091-0/+23
| | | | | | | | | | | | | | | | | | Add sample dm reset test for reset_get_by_index and reset_get_by_index_nodev functionality code. Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * reset: Get the RESET by index without deviceJagan Teki2019-05-092-17/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Getting a RESET by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process RESET operation for child without udevice but with ofnode. So add reset_get_by_index_nodev() and move the common code in reset_get_by_index_tail() to use for reset_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * test/dm: clk: Add clk_get_by_index[_nodev] testJagan Teki2019-05-091-0/+21
| | | | | | | | | | | | | | | | | | Add sample dm clk test for clk_get_by_index and clk_get_by_index_nodev functionality code. Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * clk: Use clk_get_by_index_tail()Jagan Teki2019-05-091-22/+2
| | | | | | | | | | | | | | | | | | clk_get_by_index_tail() now handle common clk get by index code so use it from clk_get_by_indexed_prop(). Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * clk: Get the CLK by index without deviceJagan Teki2019-05-092-1/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * serial: sifive: Change include orderJagan Teki2019-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the serial_sifive driver is unable to find CONFIG_ENV_SIZE. In file included from arch/riscv/include/asm/u-boot.h:23:0, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from drivers/serial/serial_sifive.c:6: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in serial_sifive.c to include first common.h file. Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Rick Chen <rick@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * clk: sifive: fu540-prci: Change include orderJagan Teki2019-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the fu540-prci driver is unable to find CONFIG_ENV_SIZE. In file included from arch/riscv/include/asm/u-boot.h:23:0, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from include/clk-uclass.h:13, from drivers/clk/sifive/fu540-prci.c:32: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in fu540-prci.c to include first common.h file. Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Rick Chen <rick@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: atcspi200: Change include orderJagan Teki2019-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the atcspi200_spi driver is unable to find CONFIG_ENV_SIZE. In file included from arch/nds32/include/asm/u-boot.h:24, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from drivers/spi/atcspi200_spi.c:9: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in atcspi200_spi.c to include first common.h file. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Fix build when CONFIG_CMD_PXE or CONFIG_CMD_DHCP are disabledOndrej Jirman2019-04-181-2/+14
| | | | | | | | | | | | | | | | Fixes a compilation failure with disabled PXE or DHCP command when using sunxi platform. Signed-off-by: Ondřej Jirman <megous@megous.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: dts: h6: Add Beelink GS1 initial supportClément Péron2019-04-184-0/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Beelink GS1 is an Allwinner H6 based TV box, which support: - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 - GPU Mali-T720 - 2GB LPDDR3 RAM - 16GB eMMC - AXP805 PMIC - 1Gbps GMAC via RTL8211E - USB 2.0 and 3.0 Host - HDMI port - S/PDIF port - 5V/2A DC power supply - Wi-Fi/BT via Fn-Link 6222B-SRB (RTL8222BS) Linux commit details about the sun50i-h6-beelink-gs1.dts sync: "arm64: dts: allwinner: h6: Introduce Beelink GS1 board" (sha1: 089bee8dd119ba084dee6b17a2e1a53df4f30193) Signed-off-by: Clément Péron <peron.clem@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2019-05-0864-982/+2063
|\ \ | | | | | | | | | | | | | | | | | | - Allow x86 boards to use TPL, SPL and U-Boot proper - Update sysreset x86 driver to utilize ACPI registers to do power off - Add a new chromebook_samus_tpl board for TPL support - Several minor changes in binman tool
| * | x86: samus: Add a target to boot through TPLSimon Glass2019-05-085-2/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a version of samus which supports booting from TPL to SPL and then to U-Boot. This allows TPL to select from an A or B SPL to support verified boot with field upgrade. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: samus: Update device tree for verified bootSimon Glass2019-05-081-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add nvdata drivers for the TPM and RTC as used on samus. These are needed for Chromium OS verified boot on samus. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: samus: Update device tree for SPLSimon Glass2019-05-081-3/+28
| | | | | | | | | | | | | | | | | | | | | Add tags to allow required nodes to be present in SPL / TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add a simple TPL implementationSimon Glass2019-05-086-13/+183
| | | | | | | | | | | | | | | | | | | | | | | | Add the required CPU code so that TPL builds correctly. Also update the SPL code to deal with being booted from TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add a way to jump from TPL to SPLSimon Glass2019-05-081-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | When TPL finishes it needs to jump to SPL with the stack set up correctly. Add a function to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: samus: Increase the pre-reloc memory againSimon Glass2019-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | This is again too small, so increase it slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: broadwell: Update PCH to work in TPLSimon Glass2019-05-081-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | The early init should only happen once. Update the probe method to deal with TPL, SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Enable the RTC on all boardsSimon Glass2019-05-082-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | With the move to Kconfig this option should be set in Kconfig, not in the config header file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Fix device-tree indentationSimon Glass2019-05-081-74/+73
| | | | | | | | | | | | | | | | | | | | | | | | With the use of a phandle we can outdent the device tree nodes a little. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Update device tree for Chromium OS verified bootSimon Glass2019-05-081-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The standard image generated by U-Boot on x86 is u-boot.rom. Add a separate image called image.bin for verified boot. This supports verification in TPL of which SPL/U-Boot to start, then jumping to the correct one, with SPL setting up the SDRAM and U-Boot proper providing the user interface if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Update device tree for TPLSimon Glass2019-05-081-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add TPL binaries to the device x86 binman desciption. When enabled, TPL will start first, doing the 16-bit init, then jump to SPL and finally U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add documentation on the samus flashmapSimon Glass2019-05-081-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are quite a few variables which control where things appear in the final ROM image. Add a flashmap in the documentation to make this easier to figure out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed "x86: Update the memory map a little" in] [bmeng: fixed typo of 'documentation' in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Support PCI VGA ROM when TPL is usedSimon Glass2019-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | When TPL is in use, U-Boot proper should support initing the VGA ROM even though the 32-bit init portion is in SPL. Update the condition to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Don't generate a bootstage report in SPLSimon Glass2019-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This report is normally generated by U-Boot proper. Correct the condition here so that it respects the Kconfig options for bootstage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Don't set up MTRRs in SPLSimon Glass2019-05-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | The MTRRs are normally set up in U-Boot proper, so avoid setting them up in SPL as well. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Support TPL in Intel common codeSimon Glass2019-05-081-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: sysreset: Implement the get_last() methodSimon Glass2019-05-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a default implementation of this method which always indicates that the last reset was a power-on reset. This is the most likely type of reset and without a PCH-specific driver we cannot determine any other type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: sysreset: Implement power-off if availableSimon Glass2019-05-081-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | On modern x86 devices we can power the system off using the power- management features of the PCH. Add an implementation for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: sysreset: Separate out the EFI codeSimon Glass2019-05-081-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EFI implementation of reset sits inside the driver and is called directly from outside the driver, breaking the normal driver-model conventions. Worse, it passed NULL as the device pointer, hoping that the called function won't use it, which breaks as soon as code is added to use it. Separate out the implementation to improve the situation enough to allow a future patch to add new sysreset features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: broadwell: Implement PCH_REQ_PMBASE_INFOSimon Glass2019-05-081-0/+25
| | | | | | | | | | | | | | | | | | | | | Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: ivybridge: Implement PCH_REQ_PMBASE_INFOSimon Glass2019-05-081-0/+15
| | | | | | | | | | | | | | | | | | | | | Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: pch: Add an ioctl to read power-management infoSimon Glass2019-05-081-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Add a new ioctl() request to read information about the power-management system. This can be used to power off the device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: mrccache: Add more debuggingSimon Glass2019-05-081-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | When the MRC cache fails to save it is useful to have some debugging info to indicate what when wrong. Add some more debug() calls. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Support saving MRC data from SPLSimon Glass2019-05-082-9/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | When SPL is used to set up the memory controller we want to save the MRC data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a function to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add common Intel code for SPLSimon Glass2019-05-082-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: broadwell: Select refcode and CPU code for SPLSimon Glass2019-05-081-3/+4
| | | | | | | | | | | | | | | | | | | | | Allow broadwell to build for SPL and include the reference code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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