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-rw-r--r--include/power/max77693_fg.h49
-rw-r--r--include/power/max77693_muic.h74
-rw-r--r--include/power/max77693_pmic.h43
3 files changed, 166 insertions, 0 deletions
diff --git a/include/power/max77693_fg.h b/include/power/max77693_fg.h
new file mode 100644
index 0000000000..42626ed839
--- /dev/null
+++ b/include/power/max77693_fg.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MAX77693_FG_H_
+#define __MAX77693_FG_H_
+
+/* MAX 77693 registers */
+enum {
+ MAX77693_STATUS = 0x00,
+ MAX77693_SOCREP = 0x06,
+ MAX77693_VCELL = 0x09,
+ MAX77693_CURRENT = 0x0A,
+ MAX77693_AVG_CURRENT = 0x0B,
+ MAX77693_SOCMIX = 0x0D,
+ MAX77693_SOCAV = 0x0E,
+ MAX77693_DESIGN_CAP = 0x18,
+ MAX77693_AVG_VCELL = 0x19,
+ MAX77693_CONFIG = 0x1D,
+ MAX77693_VERSION = 0x21,
+ MAX77693_LEARNCFG = 0x28,
+ MAX77693_FILTERCFG = 0x29,
+ MAX77693_RELAXCFG = 0x2A,
+ MAX77693_MISCCFG = 0x2B,
+ MAX77693_CGAIN = 0x2E,
+ MAX77693_COFF = 0x2F,
+ MAX77693_RCOMP0 = 0x38,
+ MAX77693_TEMPCO = 0x39,
+ MAX77693_FSTAT = 0x3D,
+ MAX77693_VFOCV = 0xEE,
+ MAX77693_VFSOC = 0xFF,
+
+ FG_NUM_OF_REGS = 0x100,
+};
+
+#define MAX77693_POR (1 << 1)
+
+#define MODEL_UNLOCK1 0x0059
+#define MODEL_UNLOCK2 0x00c4
+#define MODEL_LOCK1 0x0000
+#define MODEL_LOCK2 0x0000
+
+#define MAX77693_FUEL_I2C_ADDR (0x6C >> 1)
+
+int power_fg_init(unsigned char bus);
+#endif /* __MAX77693_FG_H_ */
diff --git a/include/power/max77693_muic.h b/include/power/max77693_muic.h
new file mode 100644
index 0000000000..a2c29eb6ce
--- /dev/null
+++ b/include/power/max77693_muic.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MAX77693_MUIC_H_
+#define __MAX77693_MUIC_H_
+
+#include <power/power_chrg.h>
+
+/*
+ * MUIC REGISTER
+ */
+
+#define MAX77693_MUIC_PREFIX "max77693-muic:"
+
+/* MAX77693_MUIC_STATUS1 */
+#define MAX77693_MUIC_ADC_MASK 0x1F
+
+/* MAX77693_MUIC_STATUS2 */
+#define MAX77693_MUIC_CHG_NO 0x00
+#define MAX77693_MUIC_CHG_USB 0x01
+#define MAX77693_MUIC_CHG_USB_D 0x02
+#define MAX77693_MUIC_CHG_TA 0x03
+#define MAX77693_MUIC_CHG_TA_500 0x04
+#define MAX77693_MUIC_CHG_TA_1A 0x05
+#define MAX77693_MUIC_CHG_MASK 0x07
+
+/* MAX77693_MUIC_CONTROL1 */
+#define MAX77693_MUIC_CTRL1_DN1DP2 ((0x1 << 3) | 0x1)
+#define MAX77693_MUIC_CTRL1_UT1UR2 ((0x3 << 3) | 0x3)
+#define MAX77693_MUIC_CTRL1_ADN1ADP2 ((0x4 << 3) | 0x4)
+#define MAX77693_MUIC_CTRL1_AUT1AUR2 ((0x5 << 3) | 0x5)
+#define MAX77693_MUIC_CTRL1_MASK 0xC0
+
+#define MUIC_PATH_USB 0
+#define MUIC_PATH_UART 1
+
+#define MUIC_PATH_CP 0
+#define MUIC_PATH_AP 1
+
+enum muic_path {
+ MUIC_PATH_USB_CP,
+ MUIC_PATH_USB_AP,
+ MUIC_PATH_UART_CP,
+ MUIC_PATH_UART_AP,
+};
+
+/* MAX 777693 MUIC registers */
+enum {
+ MAX77693_MUIC_ID = 0x00,
+ MAX77693_MUIC_INT1 = 0x01,
+ MAX77693_MUIC_INT2 = 0x02,
+ MAX77693_MUIC_INT3 = 0x03,
+ MAX77693_MUIC_STATUS1 = 0x04,
+ MAX77693_MUIC_STATUS2 = 0x05,
+ MAX77693_MUIC_STATUS3 = 0x06,
+ MAX77693_MUIC_INTMASK1 = 0x07,
+ MAX77693_MUIC_INTMASK2 = 0x08,
+ MAX77693_MUIC_INTMASK3 = 0x09,
+ MAX77693_MUIC_CDETCTRL = 0x0A,
+ MAX77693_MUIC_CONTROL1 = 0x0C,
+ MAX77693_MUIC_CONTROL2 = 0x0D,
+ MAX77693_MUIC_CONTROL3 = 0x0E,
+
+ MUIC_NUM_OF_REGS = 0x0F,
+};
+
+#define MAX77693_MUIC_I2C_ADDR (0x4A >> 1)
+
+int power_muic_init(unsigned int bus);
+#endif /* __MAX77693_MUIC_H_ */
diff --git a/include/power/max77693_pmic.h b/include/power/max77693_pmic.h
new file mode 100644
index 0000000000..616d051f17
--- /dev/null
+++ b/include/power/max77693_pmic.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MAX77693_PMIC_H_
+#define __MAX77693_PMIC_H_
+
+#include <power/power_chrg.h>
+
+enum {CHARGER_ENABLE, CHARGER_DISABLE};
+
+#define CHARGER_MIN_CURRENT 200
+#define CHARGER_MAX_CURRENT 2000
+
+#define MAX77693_CHG_PREFIX "max77693-chg:"
+
+/* Registers */
+
+#define MAX77693_CHG_BASE 0xB0
+#define MAX77693_CHG_INT_OK 0xB2
+#define MAX77693_CHG_CNFG_00 0xB7
+#define MAX77693_CHG_CNFG_02 0xB9
+#define MAX77693_CHG_CNFG_06 0xBD
+#define MAX77693_SAFEOUT 0xC6
+
+#define PMIC_NUM_OF_REGS 0xC7
+
+#define MAX77693_CHG_DETBAT (0x1 << 7) /* MAX77693_CHG_INT_OK */
+#define MAX77693_CHG_MODE_ON 0x05 /* MAX77693_CHG_CNFG_00 */
+#define MAX77693_CHG_CC 0x3F /* MAX77693_CHG_CNFG_02 */
+#define MAX77693_CHG_LOCK (0x0 << 2) /* MAX77693_CHG_CNFG_06 */
+#define MAX77693_CHG_UNLOCK (0x3 << 2) /* MAX77693_CHG_CNFG_06 */
+
+#define MAX77693_ENSAFEOUT1 (1 << 6)
+#define MAX77693_ENSAFEOUT2 (1 << 7)
+
+#define MAX77693_PMIC_I2C_ADDR (0xCC >> 1)
+
+int pmic_init_max77693(unsigned char bus);
+#endif /* __MAX77693_PMIC_H_ */