diff options
Diffstat (limited to 'include/configs')
52 files changed, 0 insertions, 6580 deletions
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h deleted file mode 100644 index af2916bf75..0000000000 --- a/include/configs/MPC8308RDB.h +++ /dev/null @@ -1,329 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_USE_PIO -#endif - -/* - * On-board devices - * - * TSEC1 is SoC TSEC - * TSEC2 is VSC switch - */ -#define CONFIG_TSEC1 -#define CONFIG_VSC7385_ENET - -/* - * SERDES - */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of two chips HY5PS12621BFP-C4 from HYNIX - */ - -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ - -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (6 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x27256222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x121048c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03600100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32) - /* 0x43080000 */ - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0232 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -/* 127 64KB sectors and 8 8KB top sectors per device */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ -#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ - /* 0xFFFF8396 */ - -#ifdef CONFIG_VSC7385_ENET -#define CONFIG_TSEC2 - /* VSC7385 Base address on CS2 */ -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 -#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ - /* 0xFFFE09FF */ -/* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFE7FE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 -#endif -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * SPI on header J8 - * - * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) - * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. - */ -#ifdef CONFIG_MPC8XXX_SPI -#define CONFIG_USE_SPIFLASH -#endif - -/* - * Board info - revision and where boot from - */ -#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -/* enable PCIE clock */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=${consoledev},${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "kernel_addr=FE080000\0" \ - "fdt_addr=FE280000\0" \ - "ramdisk_addr=FE290000\0" \ - "u-boot=mpc8308rdb/u-boot.bin\0" \ - "kernel_addr_r=1000000\0" \ - "fdt_addr_r=C00000\0" \ - "hostname=mpc8308rdb\0" \ - "bootfile=mpc8308rdb/uImage\0" \ - "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ - "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "bootcmd=run flash_self\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h deleted file mode 100644 index 586c1e9ae8..0000000000 --- a/include/configs/MPC8349ITX.h +++ /dev/null @@ -1,439 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - */ - -/* - MPC8349E-mITX and MPC8349E-mITX-GP board configuration file - - Memory map: - - 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) - 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) - 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) - 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) - 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) - 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) - 0xF001_0000-0xF001_FFFF Local bus expansion slot - 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) - 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory - 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) - - I2C address list: - Align. Board - Bus Addr Part No. Description Length Location - ---------------------------------------------------------------- - I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 - - I2C1 0x20 PCF8574 I2C Expander 0 U8 - I2C1 0x21 PCF8574 I2C Expander 0 U10 - I2C1 0x38 PCF8574A I2C Expander 0 U8 - I2C1 0x39 PCF8574A I2C Expander 0 U10 - I2C1 0x51 (DDR) DDR EEPROM 1 U1 - I2C1 0x68 DS1339 RTC 1 U68 - - Note that a given board has *either* a pair of 8574s or a pair of 8574As. -*/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * On-board devices - */ - -#ifdef CONFIG_TARGET_MPC8349ITX -/* The CF card interface on the back of the board */ -#define CONFIG_COMPACT_FLASH -#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ -#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ -#endif - -#include <linux/stringify.h> -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C - -/* - * Device configurations - */ - -/* I2C */ -#ifdef CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ -#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ - -#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ -#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ -#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ -#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ -#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ - -/* Don't probe these addresses: */ -#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ - {1, CONFIG_SYS_I2C_8574_ADDR2}, \ - {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ - {1, CONFIG_SYS_I2C_8574A_ADDR2} } -/* Bit definitions for the 8574[A] I2C expander */ - /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ -#define I2C_8574_REVISION 0x03 -#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ -#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ -#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ -#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ - -#endif - -/* Compact Flash */ -#ifdef CONFIG_COMPACT_FLASH - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 -#define CONFIG_SYS_ATA_STRIDE 2 - -/* If a CF card is not inserted, time out quickly */ -#define ATA_RESET_TIME 1 - -#endif - -/* - * SATA - */ -#ifdef CONFIG_SATA_SIL3114 - -#define CONFIG_SYS_SATA_MAX_DEVICE 4 -#define CONFIG_LBA48 - -#endif - -#ifdef CONFIG_SYS_USB_HOST -/* - * Support USB - */ -#define CONFIG_USB_EHCI_FSL - -/* Current USB implementation supports the only USB controller, - * so we have to choose between the MPH or the DR ones */ -#if 1 -#define CONFIG_HAS_FSL_MPH_USB -#else -#define CONFIG_HAS_FSL_DR_USB -#endif - -#endif - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_83XX_DDR_USES_CS0 - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) - -#define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) - -#ifdef CONFIG_SYS_I2C -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ -#endif - -/* No SPD? Then manually set up DDR parameters */ -#ifndef CONFIG_SPD_EEPROM - #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ - #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - - #define CONFIG_SYS_DDR_TIMING_1 0x26242321 - #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ -#endif - -/* - *Flash on the Local Bus - */ - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -/* 127 64KB sectors + 8 8KB sectors per device */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* The ITX has two flash chips, but the ITX-GP has only one. To support both -boards, we say we have two, but don't display a message if we find only one. */ -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} -#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ - -/* Vitesse 7385 */ - -#ifdef CONFIG_VSC7385_ENET - -#define CONFIG_TSEC2 - -/* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFEFFE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 - -#endif - -/* - * BRx, ORx, LBLAWBARx, and LBLAWARx - */ - - -/* Vitesse 7385 */ - -#define CONFIG_SYS_VSC7385_BASE 0xF8000000 - -#define CONFIG_SYS_LED_BASE 0xF9000000 - - -/* Compact Flash */ - -#ifdef CONFIG_COMPACT_FLASH - -#define CONFIG_SYS_CF_BASE 0xF0000000 - - -#endif - -/* - * U-Boot memory configuration - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONSOLE ttyS0 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* - * PCI - */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_MPC83XX_PCI2 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE \ - (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE \ - (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE \ - (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS \ - (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ -#endif - -#ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR 0x00000000 - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE - #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif - -/* TSEC */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_TSEC1 - -#ifdef CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 - -#define TSEC2_PHY_ADDR 4 -#define TSEC2_PHYIDX 0 -#define TSEC2_FLAGS TSEC_GIGABIT -#endif - -#define CONFIG_ETHPRIME "Freescale TSEC" - -#endif - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Watchdog */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * System performance - */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ -#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ - -/* - * System IO Config - */ -/* Needed for gigabit to work on TSEC 1 */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 - /* USB DR as device + USB MPH as host */ -#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_NETDEV "eth0" - -/* Default path and filenames */ -#define CONFIG_ROOTPATH "/nfsroot/rootfs" -#define CONFIG_BOOTFILE "uImage" - /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH "u-boot.bin" - -#ifdef CONFIG_TARGET_MPC8349ITX -#define CONFIG_FDTFILE "mpc8349emitx.dtb" -#else -#define CONFIG_FDTFILE "mpc8349emitxgp.dtb" -#endif - - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=" __stringify(CONSOLE) "\0" \ - "netdev=" CONFIG_NETDEV "\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "fdtaddr=780000\0" \ - "fdtfile=" CONFIG_FDTFILE "\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ - " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ - " console=$console,$baudrate $othbootargs; " \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw" \ - " console=$console,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h deleted file mode 100644 index c42cb426d8..0000000000 --- a/include/configs/MPC837XEMDS.h +++ /dev/null @@ -1,370 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -/* - * IP blocks clock configuration - */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL 0x00000000 - -/* - * Output Buffer Impedance - */ -#define CONFIG_SYS_OBIR 0x31100000 - -#define CONFIG_HWCONFIG - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_83XX_DDR_USES_CS0 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x80080001 */ /* ODT 150ohm on SoC */ - -#undef CONFIG_DDR_ECC /* support DDR ECC function */ -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ - -#if defined(CONFIG_SPD_EEPROM) -#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ -#else -/* - * Manually set up DDR parameters - * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM - * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 - */ -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ - | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ - | CSCONFIG_ROW_BIT_14 \ - | CSCONFIG_COL_BIT_10) - /* 0x80010202 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00620802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (13 << TIMING_CFG1_REFREC_SHIFT) \ - | (3 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x3935d322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (6 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x131088c8 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03E00100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x1432 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 -#endif - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * BCSR on the Local Bus - */ -#define CONFIG_SYS_BCSR 0xF8000000 - /* Access window base at BCSR base */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 - -#define CONFIG_SYS_NAND_BASE 0xE0600000 - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#ifndef __ASSEMBLY__ -extern int board_pci_host_broken(void); -#endif -#define CONFIG_PCIE -#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ - -#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#endif /* CONFIG_PCI */ - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 -#define TSEC1_PHY_ADDR_SGMII 8 -#define TSEC2_PHY_ADDR_SGMII 4 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC1" - -/* SERDES */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_FSL_SERDES2 0xe3100 - -/* - * SATA - */ -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC_PIN_MUX -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc8379_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index f0ef365a85..b1acb564c3 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -19,7 +19,6 @@ #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ -#elif defined(CONFIG_ARCH_T2081) #endif /* High Level Configuration Options */ @@ -50,8 +49,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg #endif #endif @@ -67,8 +64,6 @@ #endif #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg #endif #endif @@ -83,8 +78,6 @@ #endif #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg #endif #endif diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h deleted file mode 100644 index 1ecb7c9df8..0000000000 --- a/include/configs/advantech_dms-ba16.h +++ /dev/null @@ -1,222 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Timesys Corporation - * Copyright (C) 2016 Advantech Corporation - * Copyright (C) 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __ADVANTECH_DMSBA16_CONFIG_H -#define __ADVANTECH_DMSBA16_CONFIG_H - -#include <asm/arch/imx-regs.h> -#include <asm/mach-imx/gpio.h> - -#define CONFIG_BOARD_NAME "Advantech DMS-BA16" - -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" -#define CONFIG_EXTRA_BOOTARGS "panic=10" - -#define CONFIG_BOOT_DIR "" -#define CONFIG_LOADCMD "fatload" -#define CONFIG_RFSPART "2" - -#include "mx6_common.h" -#include <linux/sizes.h> - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -/* SATA Configs */ -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_USBD_HS - -/* Networking Configs */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 4 - -/* Serial Flash */ - -#define CONFIG_LOADADDR 0x12000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=" CONFIG_BOOT_DIR "/uImage\0" \ - "uboot=u-boot.imx\0" \ - "fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=yes\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "sddev=0\0" \ - "emmcdev=1\0" \ - "partnum=1\0" \ - "loadcmd=" CONFIG_LOADCMD "\0" \ - "rfspart=" CONFIG_RFSPART "\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "update_sf_uboot=" \ - "if tftp $loadaddr $uboot; then " \ - "sf probe; " \ - "sf erase 0 0xC0000; " \ - "sf write $loadaddr 0x400 $filesize; " \ - "echo 'U-Boot upgraded. Please reset'; " \ - "fi\0" \ - "setargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \ - "loadbootscript=" \ - "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \ - " source\0" \ - "loadimage=" \ - "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ - "loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \ - "tryboot=" \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run doboot; " \ - "fi; " \ - "fi;\0" \ - "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \ - "run setargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" \ - -#define CONFIG_BOOTCOMMAND \ - "usb start; " \ - "setenv dev usb; " \ - "setenv devnum 0; " \ - "setenv rootdev sda${rfspart}; " \ - "run tryboot; " \ - \ - "setenv dev mmc; " \ - "setenv rootdev mmcblk0p${rfspart}; " \ - \ - "setenv devnum ${sddev}; " \ - "if mmc dev ${devnum}; then " \ - "run tryboot; " \ - "fi; " \ - \ - "setenv devnum ${emmcdev}; " \ - "setenv rootdev mmcblk${emmcdev}p${rfspart}; " \ - "if mmc dev ${devnum}; then " \ - "run tryboot; " \ - "fi; " \ - \ - "bmode usb; " \ - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* FLASH and environment organization */ - -#define CONFIG_SYS_FSL_USDHC_NUM 3 - -/* Framebuffer */ -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) -#endif - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 - -#endif /* __ADVANTECH_DMSBA16_CONFIG_H */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h deleted file mode 100644 index aa20a7d8f2..0000000000 --- a/include/configs/am3517_crane.h +++ /dev/null @@ -1,236 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am3517_crane.h - Default configuration for AM3517 CraneBoard. - * - * Author: Srinath.R <srinath@mistralsolutions.com> - * - * Based on include/configs/am3517evm.h - * - * Copyright (C) 2011 Mistral Solutions pvt Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - /* initial data */ -/* - * DDR related - */ -#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* - * USB configuration - * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_USB_MUSB_UDC for Device functionalities. - */ - -#ifdef CONFIG_USB_AM35X -#ifdef CONFIG_USB_MUSB_UDC -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" -#endif /* CONFIG_USB_MUSB_UDC */ - -#endif /* CONFIG_USB_AM35X */ - -#define CONFIG_SYS_I2C - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access */ - /* nand at CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ - -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ - -/* Environment information */ - -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ - "mmcdev=0\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ - "nandargs=setenv bootargs console=${console} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command */ - /* args */ -/* memtest works on */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ - -/* - * AM3517 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ - /* on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_FLASH_BASE NAND_BASE - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/apf27.h b/include/configs/apf27.h deleted file mode 100644 index b69e5772a6..0000000000 --- a/include/configs/apf27.h +++ /dev/null @@ -1,266 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * Configuration settings for the Armadeus Project motherboard APF27 - * - * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#define CONFIG_ENV_VERSION 10 -#define CONFIG_BOARD_NAME apf27 - -/* - * SoC configurations - */ -#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ -#define CONFIG_MACH_TYPE 1698 /* APF27 */ - -/* - * Enable the call to miscellaneous platform dependent initialization. - */ - -/* - * SPL - */ -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_SIZE 2048 - -/* NAND boot config */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_HOSTNAME "apf27" -#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" - -/* - * Memory configurations - */ -#define CONFIG_NR_DRAM_POPULATED 1 - -#define ACFG_SDRAM_MBYTE_SYZE 64 - -#define PHYS_SDRAM_1 0xA0000000 -#define PHYS_SDRAM_2 0xB0000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ - + PHYS_SDRAM_1_SIZE - 0x0100000) - -/* - * FLASH organization - */ -#define ACFG_MONITOR_OFFSET 0x00000000 -#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ -#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ -#define CONFIG_FIRMWARE_OFFSET 0x00200000 -#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ -#define CONFIG_KERNEL_OFFSET 0x00300000 -#define CONFIG_ROOTFS_OFFSET 0x00800000 - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG /* send initrd params */ - -#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" - -#define ACFG_CONSOLE_DEV ttySMX0 -#define CONFIG_BOOTCOMMAND "run ubifsboot" -#define CONFIG_SYS_AUTOLOAD "no" -/* - * Default load address for user programs and kernel - */ -#define CONFIG_LOADADDR 0xA0000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Extra Environments - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ - "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "partition=nand0,6\0" \ - "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ - "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ - "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ - "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ - "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ - "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ - "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ - "kernel_addr_r=A0000000\0" \ - "check_env=if test -n ${flash_env_version}; " \ - "then env default env_version; " \ - "else env set flash_env_version ${env_version}; env save; "\ - "fi; " \ - "if itest ${flash_env_version} < ${env_version}; then " \ - "echo \"*** Warning - Environment version" \ - " change suggests: run flash_reset_env; reset\"; "\ - "env default flash_reset_env; "\ - "fi; \0" \ - "check_flash=nand lock; nand unlock ${env_addr}; \0" \ - "flash_reset_env=env default -f -a; saveenv; run update_env;" \ - "echo Flash environment variables erased!\0" \ - "download_uboot=tftpboot ${loadaddr} ${board_name}" \ - "-u-boot-with-spl.bin\0" \ - "flash_uboot=nand unlock ${u-boot_addr} ;" \ - "nand erase.part u-boot;" \ - "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ - "then nand lock; nand unlock ${env_addr};" \ - "echo Flashing of uboot succeed;" \ - "else echo Flashing of uboot failed;" \ - "fi; \0" \ - "update_uboot=run download_uboot flash_uboot\0" \ - "download_env=tftpboot ${loadaddr} ${board_name}" \ - "-u-boot-env.txt\0" \ - "flash_env=env import -t ${loadaddr}; env save; \0" \ - "update_env=run download_env flash_env\0" \ - "update_all=run update_env update_uboot\0" \ - "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ - -/* - * Serial Driver - */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* - * NOR - */ - -/* - * NAND - */ - -#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 -#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 -#define NAND_MAX_CHIPS 1 - -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_NAND_QUIET 1 - -/* - * Partitions & Filsystems - */ - -/* - * Ethernet (on SOC imx FEC) - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f - -/* - * FPGA - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_CHECK_CTRLC -#define CONFIG_SYS_FPGA_CHECK_ERROR - -/* - * Fuses - IIM - */ -#ifdef CONFIG_CMD_IMX_FUSE -#define IIM_MAC_BANK 0 -#define IIM_MAC_ROW 5 -#define IIM0_SCC_KEY 11 -#define IIM1_SUID 1 -#endif - -/* - * I2C - */ - -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F -#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES { } - -#ifdef CONFIG_CMD_EEPROM -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ -#endif /* CONFIG_CMD_EEPROM */ -#endif /* CONFIG_CMD_I2C */ - -/* - * SD/MMC - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 -#endif - -/* - * RTC - */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1374 -#define CONFIG_SYS_RTC_BUS_NUM 0 -#endif /* CONFIG_CMD_DATE */ - -/* - * PLL - * - * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 - * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| - */ -#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ - -#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ -/* micron 64MB */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 128) -/* micron 128MB */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 256) -/* micron 256MB */ -#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ -#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h deleted file mode 100644 index 05ada258ea..0000000000 --- a/include/configs/bcm23550_w1d.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __BCM23550_W1D_H -#define __BCM23550_W1D_H - -#include <linux/sizes.h> -#include <asm/arch/sysmap.h> - -/* CPU, chip, mach, etc */ -#define CONFIG_KONA -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_KONA_RESET_S - -/* - * Memory configuration - */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ - -/* GPIO Driver */ -#define CONFIG_KONA_GPIO - -/* MMC/SD Driver */ -#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR -#define CONFIG_SYS_SDIO0_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO1_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO2_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO3_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO0 "sdio1" -#define CONFIG_SYS_SDIO1 "sdio2" -#define CONFIG_SYS_SDIO2 "sdio3" -#define CONFIG_SYS_SDIO3 "sdio4" - -/* I2C Driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_KONA -#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */ -#define CONFIG_SYS_MAX_I2C_BUS 4 -#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR -#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR -#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR -#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR - -/* Timer Driver */ -#define CONFIG_SYS_TIMER_RATE 32000 -#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */ - -/* Init functions */ - -/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* No mtest functions as recommended */ - -/* - * This is the initial SP which is used only briefly for relocating the u-boot - * image to the top of SDRAM. After relocation u-boot moves the stack to the - * proper place. - */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* Serial Info */ -#define CONFIG_SYS_NS16550_SERIAL -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 13000000 -#define CONFIG_SYS_NS16550_COM1 0x3e000000 - -/* must fit into GPT:u-boot-env partition */ - -/* console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * One partition type must be defined for part.c - * This is necessary for the fatls command to work on an SD card - * for example. - */ - -/* version string, parser, etc */ - -/* Initial upstream - boot to cmd prompt only */ -#define CONFIG_BOOTCOMMAND "" - -#define CONFIG_USBID_ADDR 0x34052c46 - -#define CONFIG_SYS_L2CACHE_OFF - -#endif /* __BCM23550_W1D_H */ diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h deleted file mode 100644 index c84a5ca2e5..0000000000 --- a/include/configs/bcm28155_ap.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __BCM28155_AP_H -#define __BCM28155_AP_H - -#include <linux/sizes.h> -#include <asm/arch/sysmap.h> - -/* CPU, chip, mach, etc */ -#define CONFIG_KONA -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Memory configuration - */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 - -#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ - -/* GPIO Driver */ -#define CONFIG_KONA_GPIO - -/* MMC/SD Driver */ -#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR -#define CONFIG_SYS_SDIO0_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO1_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO2_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO3_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO0 "sdio1" -#define CONFIG_SYS_SDIO1 "sdio2" -#define CONFIG_SYS_SDIO2 "sdio3" -#define CONFIG_SYS_SDIO3 "sdio4" - -/* I2C Driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_KONA -#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */ -#define CONFIG_SYS_MAX_I2C_BUS 4 -#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR -#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR -#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR -#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR - -/* Timer Driver */ -#define CONFIG_SYS_TIMER_RATE 32000 -#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */ - -/* Init functions */ - -/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* No mtest functions as recommended */ - -/* - * This is the initial SP which is used only briefly for relocating the u-boot - * image to the top of SDRAM. After relocation u-boot moves the stack to the - * proper place. - */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* Serial Info */ -#define CONFIG_SYS_NS16550_SERIAL -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 13000000 -#define CONFIG_SYS_NS16550_COM1 0x3e000000 - -/* must fit into GPT:u-boot-env partition */ - -/* console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * One partition type must be defined for part.c - * This is necessary for the fatls command to work on an SD card - * for example. - */ - -/* version string, parser, etc */ - -/* Initial upstream - boot to cmd prompt only */ -#define CONFIG_BOOTCOMMAND "" - -#define CONFIG_USBID_ADDR 0x34052c46 - -#endif /* __BCM28155_AP_H */ diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h deleted file mode 100644 index ac5cc4c1c1..0000000000 --- a/include/configs/bcm_ep_board.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#ifndef __BCM_EP_BOARD_H -#define __BCM_EP_BOARD_H - -#include <asm/arch/configs.h> - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Memory configuration - * (these must be defined elsewhere) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#error CONFIG_SYS_TEXT_BASE must be defined! -#endif -#ifndef CONFIG_SYS_SDRAM_BASE -#error CONFIG_SYS_SDRAM_BASE must be defined! -#endif -#ifndef CONFIG_SYS_SDRAM_SIZE -#error CONFIG_SYS_SDRAM_SIZE must be defined! -#endif - -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* - * This is the initial SP which is used only briefly for relocating the u-boot - * image to the top of SDRAM. After relocation u-boot moves the stack to the - * proper place. - */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* Serial Info */ -#define CONFIG_SYS_NS16550_SERIAL - -/* console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* version string, parser, etc */ - -/* Enable Time Command */ - -#endif /* __BCM_EP_BOARD_H */ diff --git a/include/configs/bcm_northstar2.h b/include/configs/bcm_northstar2.h deleted file mode 100644 index fbfab288b3..0000000000 --- a/include/configs/bcm_northstar2.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Broadcom NS2. - */ - -#ifndef __BCM_NORTHSTAR2_H -#define __BCM_NORTHSTAR2_H - -#include <linux/sizes.h> - -#define CONFIG_HOSTNAME "northstar2" - -/* Physical Memory Map */ -#define V2M_BASE 0x80000000 -#define PHYS_SDRAM_1 V2M_BASE - -#define PHYS_SDRAM_1_SIZE (4UL * SZ_1G) -#define PHYS_SDRAM_2_SIZE (4UL * SZ_1G) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* define text_base for U-boot image */ -#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x7ff00) -#define CONFIG_SYS_LOAD_ADDR 0x90000000 -#define CONFIG_SYS_MALLOC_LEN SZ_16M - -/* Serial Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_SYS_NS16550_COM1 0x66100000 -#define CONFIG_SYS_NS16550_COM2 0x66110000 -#define CONFIG_SYS_NS16550_COM3 0x66120000 -#define CONFIG_SYS_NS16550_COM4 0x66130000 - -/* console configuration */ -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* version string, parser, etc */ - -#endif /* __BCM_NORTHSTAR2_H */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h deleted file mode 100644 index bdd5973cb7..0000000000 --- a/include/configs/cgtqmx6eval.h +++ /dev/null @@ -1,197 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * Congatec Conga-QEVAl board configuration file. - * - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * Based on Freescale i.MX6Q Sabre Lite board configuration file. - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Leo Sartre, <lsartre@adeneo-embedded.com> - */ - -#ifndef __CONFIG_CGTQMX6EVAL_H -#define __CONFIG_CGTQMX6EVAL_H - -#include <linux/stringify.h> - -#include "mx6_common.h" - -#define CONFIG_MACH_TYPE 4122 - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* SPI NOR */ -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST - -/* Thermal support */ - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ - -#define CONFIG_USBD_HS - -/* Framebuffer */ -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI - -/* SATA */ -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 - -/* Command definition */ - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p2" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdtfile=undefined\0" \ - "fdt_addr_r=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ - "dfu_alt_info_spl=spl raw 0x400\0" \ - "dfu_alt_info_img=u-boot raw 0x10000\0" \ - "dfu_alt_info=spl raw 0x400\0" \ - "bootm_size=0x10000000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr_r}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-qmx6.dtb; fi; " \ - "if test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-qmx6.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; \0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ - "bootz ${loadaddr} - ${fdt_addr_r}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\ - -#define CONFIG_BOOTCOMMAND \ - "run spilock;" \ - "run findfdt; " \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#endif /* __CONFIG_CGTQMX6EVAL_H */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h deleted file mode 100644 index 8ab8bb9f33..0000000000 --- a/include/configs/controlcenterd.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2013 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - * - * based on P1022DS.h - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#endif - -/* High Level Configuration Options */ -#define CONFIG_CONTROLCENTERD - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_SYS_CLK_FREQ 66666600 -#define CONFIG_DDR_CLK_FREQ 66666600 - -#define CONFIG_SYS_RAMBOOT - -#ifdef CONFIG_TRAILBLAZER - -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -/* - * Config the L2 Cache - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#else /* CONFIG_TRAILBLAZER */ - -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#endif /* CONFIG_TRAILBLAZER */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* - * Memory map - * - * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable - * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable - * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable - * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#ifdef CONFIG_TRAILBLAZER -/* leave CCSRBAR at default, because u-boot expects it to be exactly there */ -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT -#else -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#endif -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200) - -/* - * DDR Setup - */ - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 1024 -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#ifdef CONFIG_TRAILBLAZER -#define CONFIG_SPD_EEPROM -#define SPD_EEPROM_ADDRESS 0x52 -/*#define CONFIG_FSL_DDR_INTERACTIVE*/ -#endif - -/* - * Local Bus Definitions - */ - -#define CONFIG_SYS_ELBC_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE -#endif - -#define CONFIG_UART_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V) -#define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7) - -#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */ -#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */ - -#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -#define CONFIG_PCA9698 /* NXP PCA9698 */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * MMC - */ -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR - -#ifndef CONFIG_TRAILBLAZER - -/* - * Video - */ -#define CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ - -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* - * SATA - */ -#define CONFIG_LBA48 - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -/* - * Ethernet - */ - -#define CONFIG_TSECV2 - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -/* - * USB - */ - -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#endif /* CONFIG_TRAILBLAZER */ - -/* - * Environment - */ -#if defined(CONFIG_TRAILBLAZER) -#elif defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifndef CONFIG_TRAILBLAZER -/* - * Board initialisation callbacks - */ -#endif /* CONFIG_TRAILBLAZER */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ - -#ifdef CONFIG_TRAILBLAZER -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mp_holdoff=1\0" - -#else - -#define CONFIG_HOSTNAME "controlcenterd" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */ - -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=controlcenterd.dtb\0" \ - "bdev=sda3\0" - -/* these are used and NUL-terminated in env_default.h */ -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* CONFIG_TRAILBLAZER */ - -#endif diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h deleted file mode 100644 index 9a8735f850..0000000000 --- a/include/configs/cyrus.h +++ /dev/null @@ -1,458 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Based on corenet_ds.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) -#error Must call Cyrus CONFIG with a specific CPU enabled. -#endif - -#define CONFIG_SDCARD -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 -#ifdef CONFIG_ARCH_P5020 -#define CONFIG_SYS_FSL_RAID_ENGINE -#define CONFIG_SYS_DPAA_RMAN -#endif -#define CONFIG_SYS_DPAA_PME - -/* - * Corenet DS style board configuration file - */ -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg -#if defined(CONFIG_ARCH_P5020) -#define CONFIG_SYS_CLK_FREQ 133000000 -#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg -#elif defined(CONFIG_ARCH_P5040) -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -#define CONFIG_SYS_MMC_MAX_DEVICE 1 - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -/* test POST memory test */ -#undef CONFIG_POST - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) -#else -#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR -#endif -#define CONFIG_SYS_L3_SIZE (1024 << 10) -#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * Local Bus Definitions - */ - -#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE -#endif - -#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull -#else -#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE -#endif - -/* Set the local bus clock 1/16 of platform clock */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) - -#define CONFIG_SYS_BR0_PRELIM \ -(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_SYS_BR1_PRELIM \ -(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) - -#define CONFIG_SYS_OR0_PRELIM 0xfff00010 -#define CONFIG_SYS_OR1_PRELIM 0xfff00010 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ -{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 - -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 - -#define CONFIG_SYS_I2C_GENERIC_MAC -#define CONFIG_SYS_I2C_MAC1_BUS 3 -#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 -#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 -#define CONFIG_SYS_I2C_MAC2_BUS 0 -#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 -#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa - -#define CONFIG_RTC_MCP79411 1 -#define CONFIG_SYS_RTC_BUS_NUM 3 -#define CONFIG_SYS_I2C_RTC_ADDR 0x6f - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ - -/* Qman/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -/* Default address of microcode for the Linux Fman driver */ -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) - -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_ETHPRIME "FM1@DTSEC4" -#endif - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_EHCI_IS_TDI - /* _VIA_CONTROL_EP */ -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ -"bank_intlv=cs0_cs1;" \ -"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ -"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"fdtaddr=1e00000\0" \ -"bdev=sda3\0" - -#define CONFIG_HDBOOT \ -"setenv bootargs root=/dev/$bdev rw " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ -"setenv bootargs root=/dev/nfs rw " \ -"nfsroot=$serverip:$rootpath " \ -"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $ramdiskaddr $ramdiskfile;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#include <asm/fsl_secure_boot.h> - -#endif /* __CONFIG_H */ diff --git a/include/configs/dns325.h b/include/configs/dns325.h index ea8d28b5b5..8990efb3f6 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -36,14 +36,6 @@ #endif /* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif - -/* * Enable GPI0 support */ #define CONFIG_KIRKWOOD_GPIO diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 09bac01779..9106203ebc 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -52,11 +52,4 @@ #define CONFIG_PHY_BASE_ADR 0 #endif /* CONFIG_CMD_NET */ -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - #endif /* _CONFIG_DREAMPLUG_H */ diff --git a/include/configs/ds109.h b/include/configs/ds109.h index 35d85361b4..f232abe430 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -55,11 +55,4 @@ #define CONFIG_PHY_BASE_ADR 8 #endif /* CONFIG_CMD_NET */ -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - #endif /* _CONFIG_DS109_H */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index dd16e3fbda..949ff55624 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -122,9 +122,6 @@ */ #ifdef CONFIG_IDE #define __io -#define CONFIG_IDE_PREINIT -/* ED Mini V has an IDE-compatible SATA connector for port 1 */ -#define CONFIG_MVSATA_IDE_USE_PORT1 /* Needs byte-swapping for ATA data register */ #define CONFIG_IDE_SWAP_IO /* Data, registers and alternate blocks are at the same offset */ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 51325047ec..a18e7869b0 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -72,11 +72,4 @@ #define CONFIG_PHY_BASE_ADR 0 #endif /* CONFIG_CMD_NET */ -/* - * * SATA Driver configuration - * */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - #endif /* _CONFIG_GOFLEXHOME_H */ diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index 1e1e5da4d5..8de888fe7e 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -66,11 +66,4 @@ #define CONFIG_PHY_BASE_ADR 0 #endif /* CONFIG_CMD_NET */ -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - #endif /* _CONFIG_GURUPLUG_H */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h deleted file mode 100644 index ca40417e9a..0000000000 --- a/include/configs/hrcon.h +++ /dev/null @@ -1,421 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR - -/* - * SERDES - */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of one chip NT5TU64M16HG from NANYA - */ - -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ - -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_BANK_BIT_3 \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00260802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (7 << TIMING_CFG1_CASLAT_SHIFT) \ - | (9 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x26279222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x021848c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x08240100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_16) - /* 0x43100000 */ - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0242 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=4, AL=0 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#if 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 -#endif - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FPGA_DONE(k) 0x0010 - -#define CONFIG_SYS_FPGA_COUNT 1 - -#define CONFIG_SYS_MCLINK_MAX 3 - -#define CONFIG_SYS_FPGA_PTR \ - { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* Pass open firmware flat tree */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -#define CONFIG_PCA953X /* NXP PCA9554 */ -#define CONFIG_PCA9698 /* NXP PCA9698 */ - -#define CONFIG_SYS_I2C_IHS -#define CONFIG_SYS_I2C_IHS_CH0 -#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_IHS_CH1 -#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2 -#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F -#define CONFIG_SYS_I2C_IHS_CH3 -#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F - -#ifdef CONFIG_HRCON_DH -#define CONFIG_SYS_I2C_IHS_DUAL -#define CONFIG_SYS_I2C_IHS_CH0_1 -#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH1_1 -#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2_1 -#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH3_1 -#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F -#endif - -/* - * Software (bit-bang) I2C driver configuration - */ -#define CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define I2C_SOFT_DECLARATIONS2 -#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F -#define I2C_SOFT_DECLARATIONS3 -#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F -#define I2C_SOFT_DECLARATIONS4 -#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F -#define I2C_SOFT_DECLARATIONS5 -#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F -#define I2C_SOFT_DECLARATIONS6 -#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F -#define I2C_SOFT_DECLARATIONS7 -#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F -#define I2C_SOFT_DECLARATIONS8 -#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F - -#ifdef CONFIG_HRCON_DH -#define I2C_SOFT_DECLARATIONS9 -#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F -#define I2C_SOFT_DECLARATIONS10 -#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F -#define I2C_SOFT_DECLARATIONS11 -#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F -#define I2C_SOFT_DECLARATIONS12 -#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F -#endif - -#ifdef CONFIG_HRCON_DH -#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} -#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} -#define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ - {12, 0x4c} } -#else -#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ - {8, 0x4c} } -#endif - -#ifndef __ASSEMBLY__ -void fpga_gpio_set(unsigned int bus, int pin); -void fpga_gpio_clear(unsigned int bus, int pin); -int fpga_gpio_get(unsigned int bus, int pin); -void fpga_control_set(unsigned int bus, int pin); -void fpga_control_clear(unsigned int bus, int pin); -#endif - -#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) -#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) -#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) - -#ifdef CONFIG_HRCON_DH -#define I2C_ACTIVE \ - do { \ - if (I2C_ADAP_HWNR > 7) \ - fpga_control_set(I2C_FPGA_IDX, 0x0004); \ - else \ - fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ - } while (0) -#else -#define I2C_ACTIVE { } -#endif -#define I2C_TRISTATE { } -#define I2C_READ \ - (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - } while (0) -#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ - -/* - * Software (bit-bang) MII driver configuration - */ -#define CONFIG_BITBANGMII_MULTI - -/* - * OSD Setup - */ -#define CONFIG_SYS_OSD_SCREENS 1 -#define CONFIG_SYS_DP501_DIFFERENTIAL -#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ - -#ifdef CONFIG_HRCON_DH -#define CONFIG_SYS_OSD_DH -#endif - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -/* enable PCIE clock */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define TSEC1_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - - -#define CONFIG_HOSTNAME "hrcon" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "u-boot=u-boot.bin\0" \ - "kernel_addr=1000000\0" \ - "fdt_addr=C00000\0" \ - "fdtfile=hrcon.dtb\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp ${kernel_addr} $bootfile;" \ - "tftp ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_MMCBOOTCOMMAND \ - "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ - "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index 41483a2f7e..ba859a9a24 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -56,9 +56,6 @@ */ #ifdef CONFIG_IDE #define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_MVSATA_IDE_USE_PORT1 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET #endif /* CONFIG_IDE */ diff --git a/include/configs/kc1.h b/include/configs/kc1.h deleted file mode 100644 index 4e9a567842..0000000000 --- a/include/configs/kc1.h +++ /dev/null @@ -1,150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Amazon Kindle Fire (first generation) codename kc1 config - * - * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/cpu.h> -#include <asm/arch/omap.h> - -/* - * Build - */ - -/* - * CPU - */ - -#define CONFIG_SYS_L2_PL310 1 -#define CONFIG_SYS_PL310_BASE 0x48242000 - -/* - * Board - */ - -/* - * Clocks - */ - -#define CONFIG_SYS_TIMERBASE GPT2_BASE -#define CONFIG_SYS_PTV 2 - -/* - * DRAM - */ - -/* - * Memory - */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) - -/* - * I2C - */ - -#define CONFIG_SYS_I2C -#define CONFIG_I2C_MULTI_BUS - -/* - * Power - */ - -#define CONFIG_TWL6030_POWER - -/* - * Input - */ - -#define CONFIG_TWL6030_INPUT - -/* - * SPL - */ - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) - -/* - * Console - */ - -#define CONFIG_SYS_CBSIZE 512 - -/* - * Serial - */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_SYS_NS16550_COM3 UART3_BASE - -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ - 115200 } - -/* - * USB gadget - */ - -/* - * Environment - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x82000000\0" \ - "loadaddr=0x82000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "fdtaddr=0x88000000\0" \ - "ramdisk_addr_r=0x88080000\0" \ - "pxefile_addr_r=0x80100000\0" \ - "scriptaddr=0x80000000\0" \ - "bootm_size=0x10000000\0" \ - "boot_mmc_dev=0\0" \ - "kernel_mmc_part=7\0" \ - "recovery_mmc_part=5\0" \ - "fdtfile=omap4-kc1.dtb\0" \ - "bootfile=/boot/extlinux/extlinux.conf\0" \ - "bootargs=console=ttyO2,115200 mem=512M\0" - -/* - * ATAGs - */ - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* - * Boot - */ - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -#define CONFIG_BOOTCOMMAND \ - "setenv boot_mmc_part ${kernel_mmc_part}; " \ - "if test reboot-${reboot-mode} = reboot-r; then " \ - "echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \ - "if test reboot-${reboot-mode} = reboot-b; then " \ - "echo fastboot; fastboot 0; fi; " \ - "part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \ - "part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \ - "mmc dev ${boot_mmc_dev}; " \ - "mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \ - "bootm ${kernel_addr_r};" - -#endif diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h deleted file mode 100644 index 91a56dda28..0000000000 --- a/include/configs/mx53evk.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX53-EVK Freescale board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK - -#include <asm/arch/imx-regs.h> - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_FSL_CLK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* PMIC Configs */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_FSL -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_RTC_MC13XXX - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - -/* Eth Configs */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -/* Command definition */ - -#define CONFIG_ETHPRIME "FEC0" - -#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm\0" \ - "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h deleted file mode 100644 index 83c09ead27..0000000000 --- a/include/configs/mx6qarm2.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q Armadillo2 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_MXC_UART_BASE UART4_BASE - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc3\0" \ - "fdt_file=imx6q-arm2.dtb\0" \ - "fdt_addr=0x18000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=1\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/nas220.h b/include/configs/nas220.h index b95c7fc3be..1fd5471ac5 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -81,14 +81,6 @@ #define CONFIG_JFFS2_LZO /* - * SATA - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif - -/* * EFI partition */ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 1cb0d68b5a..e38c65a485 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -48,8 +48,6 @@ /* SATA driver configuration */ #ifdef CONFIG_IDE #define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #endif /* CONFIG_IDE */ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h deleted file mode 100644 index ea61f92bdb..0000000000 --- a/include/configs/ot1200.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. - * Copyright (C) 2014 Bachmann electronic GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* UART Configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* SF Configs */ - -/* IO expander */ -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* OCOTP Configs */ -#define CONFIG_IMX_OTP -#define IMX_OTP_BASE OCOTP_BASE_ADDR -#define IMX_OTP_ADDR_MAX 0x7F -#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA -#define IMX_OTPWRITE_ENABLED - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* SPL */ -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE MII100 -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0x5 - -#ifndef CONFIG_SPL -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_BUS 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#endif - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -/* M25P16 has an erase size of 64 KiB */ - -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_BOOTP_BOOTFILE - -#endif /* __CONFIG_H */ diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h deleted file mode 100644 index e96429083e..0000000000 --- a/include/configs/pfla02.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic <sbabic@denx.de> - */ - - -#ifndef __PCM058_CONFIG_H -#define __PCM058_CONFIG_H - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#include "mx6_common.h" - -/* Serial */ -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" - -/* Early setup */ - - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - -/* Ethernet */ -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 3 - -/* SPI Flash */ - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 0 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* Enable NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* Filesystem support */ - -/* Various command support */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* Environment organization */ - -/* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \ - "addmtd=run mtdnand;run mtdspi;" \ - "setenv bootargs ${bootargs} ${mtdparts}\0" \ - "mtdnand=setenv mtdparts mtdparts=gpmi-nand:" \ - "40m(Kernels),400m(root),-(nand)\0" \ - "mtdspi=setenv mtdparts ${mtdparts}" \ - "';spi2.0:1024k(bootloader)," \ - "64k(env1),64k(env2),-(rescue)'\0" \ - "bootcmd=if test -n ${rescue};" \ - "then run swupdate;fi;run nandboot;run swupdate\0" \ - "bootfile=uImage\0" \ - "bootimage=uImage\0" \ - "console=ttymxc3\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdt_file=pfla02.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "miscargs=panic=1 quiet\0" \ - "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \ - "mmcboot=if run mmcload;then " \ - "run mmcargs addcons addmisc;" \ - "bootm;fi\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p1\0" \ - "ubiroot=1\0" \ - "nandargs=setenv bootargs ubi.mtd=1 " \ - "root=ubi0:rootfs${ubiroot} rootfstype=ubifs\0" \ - "nandboot=run mtdnand;ubi part nand0,0;" \ - "ubi readvol ${kernel_addr_r} kernel${ubiroot};" \ - "run nandargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \ - "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \ - "run nfsargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_nfs_fit=tftp ${kernel_addr_r} ${board_name}/${fitfile};" \ - "run nfsargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "nfsargs=setenv bootargs root=/dev/nfs" \ - " nfsroot=${serverip}:${nfsroot},v3 panic=1\0" \ - "swupdate=setenv bootargs root=/dev/ram;" \ - "run addip addcons addmtd addmisc;" \ - "sf probe;" \ - "sf read ${kernel_addr_r} 120000 600000;" \ - "sf read 14000000 730000 800000;" \ - "bootm ${kernel_addr_r} 14000000\0" - -#endif diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h deleted file mode 100644 index 77b7ce411f..0000000000 --- a/include/configs/picosam9g45.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the mini-box PICOSAM9G45 board. - * (C) Copyright 2015 Inter Act B.V. - * - * Based on: - * U-Boot file: include/configs/at91sam9m10g45ek.h - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/hardware.h> - -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* LCD */ -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO -#define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_LCD -#define CONFIG_ATMEL_LCD_RGB565 -/* board specific(not enough SRAM) */ -#define CONFIG_AT91SAM9G45_LCD_BASE 0x23E00000 - -/* LED */ -#define CONFIG_AT91_LED -#define CONFIG_GREEN_LED AT91_PIN_PD31 /* this is the user1 led */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define PHYS_SDRAM_1 ATMEL_BASE_CS1 /* on DDRSDRC1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2 ATMEL_BASE_CS6 /* on DDRSDRC0 */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* MMC */ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R -#define CONFIG_AT91_WANTS_COMMON_PHY - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#ifdef CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env + linux in mmc */ - -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE 0x010000 -#define CONFIG_SPL_STACK 0x310000 - -#define CONFIG_SYS_MONITOR_LEN 0x80000 - -#ifdef CONFIG_SYS_USE_MMC - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_ATMEL_SIZE -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#endif -#endif diff --git a/include/configs/platinum.h b/include/configs/platinum.h deleted file mode 100644 index 325a28001e..0000000000 --- a/include/configs/platinum.h +++ /dev/null @@ -1,189 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Barco (www.barco.com) - */ - -#ifndef __PLATINUM_CONFIG_H__ -#define __PLATINUM_CONFIG_H__ - -/* SPL */ - -/* Location in NAND to read U-Boot from */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024) - -#include "imx6_spl.h" /* common IMX6 SPL configuration */ -#include "mx6_common.h" - -/* - * Hardware configuration - */ - -/* UART config */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C config */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* MMC config */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -/* Ethernet config */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR - -/* USB config */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* Memory config */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#ifndef PHYS_SDRAM_SIZE -#define PHYS_SDRAM_SIZE (1024 << 20) -#endif - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) - -#ifdef CONFIG_CMD_NAND - -/* NAND config */ -#ifndef CONFIG_SYS_NAND_MAX_CHIPS -#define CONFIG_SYS_NAND_MAX_CHIPS 2 -#endif -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA config, needed for GPMI/MXS NAND support */ - -/* Environment in NAND */ - -#else /* CONFIG_CMD_NAND */ - -/* Environment in MMC */ - -#endif /* CONFIG_CMD_NAND */ - -/* - * U-Boot configuration - */ - -/* Board startup config */ - -#define CONFIG_BOOTCOMMAND "run bootubi_scr" - -/* Miscellaneous configurable options */ - -/* MTD/UBI/UBIFS config */ - -/* - * Environment configuration - */ - -#if (CONFIG_SYS_NAND_MAX_CHIPS == 1) -#define CONFIG_COMMON_ENV_UBI \ - "setubipartition=env set ubipartition ubi\0" \ - "setubirfs=env set ubirfs $ubipartition:rootfs$boot_vol\0" -#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2) -#define CONFIG_COMMON_ENV_UBI \ - "setubipartition=env set ubipartition ubi$boot_vol\0" \ - "setubirfs=env set ubirfs ubi0:rootfs\0" -#endif - -#define CONFIG_COMMON_ENV_MISC \ - "user=user\0" \ - "project="CONFIG_PLATINUM_PROJECT"\0" \ - "uimage=uImage\0" \ - "dtb="CONFIG_PLATINUM_CPU"-platinum-"CONFIG_PLATINUM_PROJECT".dtb\0" \ - "serverip=serverip\0" \ - "memaddrlinux=0x10800000\0" \ - "memaddrsrc=0x11000000\0" \ - "memaddrdtb=0x12000000\0" \ - "console=ttymxc0\0" \ - "baudrate=115200\0" \ - "boot_scr=boot.uboot\0" \ - "boot_vol=0\0" \ - "mtdids="CONFIG_MTDIDS_DEFAULT"\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ - "mmcfs=ext2\0" \ - "mmcrootpart=1\0" \ - \ - "setnfspath=env set nfspath /home/nfs/$user/$project/root\0" \ - "settftpfilelinux=env set tftpfilelinux $user/$project/$uimage\0" \ - "settftpfiledtb=env set tftpfiledtb $user/$project/$dtb\0" \ - "setubifilelinux=env set ubifilelinux boot/$uimage\0" \ - "setubipfiledtb=env set ubifiledtb boot/$dtb\0" \ - "setmmcrootdev=env set mmcrootdev /dev/mmcblk0p$mmcrootpart\0" \ - "setmmcfilelinux=env set mmcfilelinux /boot/$uimage\0" \ - "setmmcfiledtb=env set mmcfiledtb /boot/$dtb\0" \ - \ - "loadtftpkernel=dhcp $memaddrlinux $tftpfilelinux\0" \ - "loadtftpdtb=dhcp $memaddrdtb $tftpfiledtb\0" \ - "loadubikernel=ubifsload $memaddrlinux $ubifilelinux\0" \ - "loadubidtb=ubifsload $memaddrdtb $ubifiledtb\0" \ - "loadmmckernel=${mmcfs}load mmc 0:$mmcrootpart $memaddrlinux " \ - "$mmcfilelinux\0" \ - "loadmmcdtb=${mmcfs}load mmc 0:$mmcrootpart $memaddrdtb " \ - "$mmcfiledtb\0" \ - \ - "ubipart=ubi part $ubipartition\0" \ - "ubimount=ubifsmount $ubirfs\0" \ - \ - "setbootargscommon=env set bootargs $bootargs " \ - "console=$console,$baudrate enable_wait_mode=off\0" \ - "setbootargsmtd=env set bootargs $bootargs $mtdparts\0" \ - "setbootargsdhcp=env set bootargs $bootargs ip=dhcp\0" \ - "setbootargsubirfs=env set bootargs $bootargs " \ - "ubi.mtd=$ubipartition root=$ubirfs rootfstype=ubifs\0" \ - "setbootargsnfsrfs=env set bootargs $bootargs root=/dev/nfs " \ - "nfsroot=$serverip:$nfspath,v3,tcp\0" \ - "setbootargsmmcrfs=env set bootargs $bootargs " \ - "root=$mmcrootdev rootwait rw\0" \ - \ - "bootnet=run settftpfilelinux settftpfiledtb setnfspath " \ - "setbootargscommon setbootargsmtd setbootargsdhcp " \ - "setbootargsnfsrfs;" \ - "run loadtftpkernel loadtftpdtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - "bootnet_ubirfs=run settftpfilelinux settftpfiledtb;" \ - "run setubipartition setubirfs;" \ - "run setbootargscommon setbootargsmtd " \ - "setbootargsubirfs;" \ - "run loadtftpkernel loadtftpdtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - "bootubi=run setubipartition setubirfs setubifilelinux " \ - "setubipfiledtb;" \ - "run setbootargscommon setbootargsmtd " \ - "setbootargsubirfs;" \ - "run ubipart ubimount loadubikernel loadubidtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - "bootubi_scr=run setubipartition setubirfs;" \ - "run ubipart ubimount;" \ - "if ubifsload ${memaddrsrc} boot/${boot_scr}; " \ - "then source ${memaddrsrc}; else run bootubi; fi\0" \ - "bootmmc=run setmmcrootdev setmmcfilelinux setmmcfiledtb " \ - "setbootargscommon setbootargsmmcrfs;" \ - "run loadmmckernel loadmmcdtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - \ - "bootcmd="CONFIG_BOOTCOMMAND"\0" - -#define CONFIG_COMMON_ENV_SETTINGS CONFIG_COMMON_ENV_MISC \ - CONFIG_COMMON_ENV_UBI -#endif /* __PLATINUM_CONFIG_H__ */ diff --git a/include/configs/platinum_picon.h b/include/configs/platinum_picon.h deleted file mode 100644 index 1b55e73979..0000000000 --- a/include/configs/platinum_picon.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Barco (www.barco.com) - */ - -#ifndef __PLATINUM_PICON_CONFIG_H__ -#define __PLATINUM_PICON_CONFIG_H__ - -#define CONFIG_PLATINUM_BOARD "Barco Picon" -#define CONFIG_PLATINUM_PROJECT "picon" -#define CONFIG_PLATINUM_CPU "imx6dl" - -#include <configs/platinum.h> - -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_HOSTNAME "picon" - -#define CONFIG_PLATFORM_ENV_SETTINGS "\0" - -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ - CONFIG_PLATFORM_ENV_SETTINGS - -#endif /* __PLATINUM_PICON_CONFIG_H__ */ diff --git a/include/configs/platinum_titanium.h b/include/configs/platinum_titanium.h deleted file mode 100644 index b4028832e9..0000000000 --- a/include/configs/platinum_titanium.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Barco (www.barco.com) - */ - -#ifndef __PLATINUM_TITANIUM_CONFIG_H__ -#define __PLATINUM_TITANIUM_CONFIG_H__ - -#define CONFIG_PLATINUM_BOARD "Barco Titanium" -#define CONFIG_PLATINUM_PROJECT "titanium" -#define CONFIG_PLATINUM_CPU "imx6q" - -#define PHYS_SDRAM_SIZE (512 << 20) -#define CONFIG_SYS_NAND_MAX_CHIPS 1 - -#include <configs/platinum.h> - -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 4 - -#define CONFIG_PHY_RESET_DELAY 1000 - -#define CONFIG_HOSTNAME "titanium" - -#define CONFIG_PLATFORM_ENV_SETTINGS "\0" - -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ - CONFIG_PLATFORM_ENV_SETTINGS - -#endif /* __PLATINUM_TITANIUM_CONFIG_H__ */ diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h deleted file mode 100644 index 275d92eff7..0000000000 --- a/include/configs/s32v234evb.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale S32V234 EVB board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -#define CONFIG_S32V234 - -/* Config GIC */ -#define CONFIG_GICV2 -#define GICD_BASE 0x7D001000 -#define GICC_BASE 0x7D002000 - -#define CONFIG_REMAKE_ELF -#undef CONFIG_RUN_FROM_IRAM_ONLY - -#define CONFIG_RUN_FROM_DDR1 -#undef CONFIG_RUN_FROM_DDR0 - -/* Run by default from DDR1 */ -#ifdef CONFIG_RUN_FROM_DDR0 -#define DDR_BASE_ADDR 0x80000000 -#else -#define DDR_BASE_ADDR 0xC0000000 -#endif - -#define CONFIG_MACH_TYPE 4146 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* SMP Spin Table Definitions */ -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (1000000000) /* 1000MHz */ -#define CONFIG_SYS_FSL_ERRATUM_A008585 - -/* Size of malloc() pool */ -#ifdef CONFIG_RUN_FROM_IRAM_ONLY -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 * 1024 * 1024) -#else -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -#endif - -#define LINFLEXUART_BASE LINFLEXD0_BASE_ADDR - -#define CONFIG_DEBUG_UART_LINFLEXUART -#define CONFIG_DEBUG_UART_BASE LINFLEXUART_BASE - -#define CONFIG_SYS_UART_PORT (1) - -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#if 0 - -/* Ethernet config */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#endif - -#if 0 /* Disable until the FLASH will be implemented */ -#define CONFIG_SYS_USE_NAND -#endif - -#ifdef CONFIG_SYS_USE_NAND -/* Nand Flash Configs */ -#define CONFIG_JFFS2_NAND -#define MTD_NAND_FSL_NFC_SWECC 1 -#define CONFIG_NAND_FSL_NFC -#define CONFIG_SYS_NAND_BASE 0x400E0000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE -#define CONFIG_SYS_NAND_SELECT_DEVICE -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ -#endif - -#define CONFIG_LOADADDR 0xC307FFC0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "boot_scripts=boot.scr.uimg boot.scr\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "console=ttyLF0,115200\0" \ - "fdt_file=s32v234-evb.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr_r=0xC2000000\0" \ - "kernel_addr_r=0xC307FFC0\0" \ - "ramdisk_addr_r=0xC4000000\0" \ - "ramdisk=rootfs.uimg\0"\ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "update_sd_firmware_filename=u-boot.imx\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \ - "jtagboot=echo Booting using jtag...; " \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \ - "run loaduimage; run loadramdisk; run loadfdt;"\ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "boot_net_usb_start=true\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd" - -#include <config_distro_bootcmd.h> -#include <linux/stringify.h> - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "=> " - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -#ifdef CONFIG_RUN_FROM_IRAM_ONLY -#define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR) -#endif - -/* Physical memory map */ -/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */ -#define PHYS_SDRAM (DDR_BASE_ADDR) -#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ - - -#define CONFIG_BOOTP_BOOTFILESIZE - -#endif diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h deleted file mode 100644 index 853a89ced1..0000000000 --- a/include/configs/sansa_fuze_plus.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - */ -#ifndef __CONFIGS_SANSA_FUZE_PLUS_H__ -#define __CONFIGS_SANSA_FUZE_PLUS_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_FONT_4X6 -#define CONFIG_VIDEO_MXS_MODE_SYSTEM -#define CONFIG_SYS_BLACK_IN_WRITE -#define LCD_BPP LCD_COLOR16 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_SANSA_FUZE_PLUS_H__ */ diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h deleted file mode 100644 index 6011fb7d52..0000000000 --- a/include/configs/sc_sps_1.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SchulerControl GmbH, SC_SPS_1 module config - * - * Copyright (C) 2012 Marek Vasut <marex@denx.de> - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_SC_SPS_1_H__ -#define __CONFIGS_SC_SPS_1_H__ - -/* System configuration */ -#define CONFIG_MACH_TYPE MACH_TYPE_SC_SPS_1 - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Environment is in MMC */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "bootm" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_SC_SPS_1_H__ */ diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h deleted file mode 100644 index bd3c3402c4..0000000000 --- a/include/configs/secomx6quq7.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Seco S.r.l - * - * Configuration settings for the Seco Boards. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_BOARD_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ethprime=FEC0\0" \ - "netdev=eth0\0" \ - "ethprime=FEC0\0" \ - "uboot=u-boot.bin\0" \ - "kernel=uImage\0" \ - "nfsroot=/opt/eldk/arm\0" \ - "ip_local=10.0.0.5::10.0.0.1:255.255.255.0::eth0:off\0" \ - "ip_server=10.0.0.1\0" \ - "nfs_path=/targetfs \0" \ - "memory=mem=1024M\0" \ - "bootdev=mmc dev 0; ext2load mmc 0:1\0" \ - "root=root=/dev/mmcblk0p1\0" \ - "option=rootwait rw fixrtc rootflags=barrier=1\0" \ - "cpu_freq=arm_freq=996\0" \ - "setbootargs=setenv bootargs console=ttymxc1,115200 ${root}" \ - " ${option} ${memory} ${cpu_freq}\0" \ - "setbootargs_nfs=setenv bootargs console=ttymxc1,115200" \ - " root=/dev/nfs nfsroot=${ip_server}:${nfs_path}" \ - " nolock,wsize=4096,rsize=4096 ip=:::::eth0:dhcp" \ - " ${memory} ${cpu_freq}\0" \ - "setbootdev=setenv boot_dev ${bootdev} 10800000 /boot/uImage\0" \ - "bootcmd=run setbootargs; run setbootdev; run boot_dev;" \ - " bootm 0x10800000\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ - -#if defined(CONFIG_ENV_IS_IN_MMC) - #define CONFIG_DYNAMIC_MMC_DEVNO -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index abe8418984..41ba799659 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -55,9 +55,6 @@ */ #ifdef CONFIG_IDE #define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_MVSATA_IDE_USE_PORT1 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET #endif /* CONFIG_IDE */ diff --git a/include/configs/strider.h b/include/configs/strider.h deleted file mode 100644 index 85db657077..0000000000 --- a/include/configs/strider.h +++ /dev/null @@ -1,454 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR - -/* - * SERDES - */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of one chip NT5TU64M16HG from NANYA - */ - -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ - -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_BANK_BIT_3 \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00260802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (7 << TIMING_CFG1_CASLAT_SHIFT) \ - | (9 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x26279222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x021848c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x08240100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_16) - /* 0x43100000 */ - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0242 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=4, AL=0 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FPGA_DONE(k) 0x0010 - -#define CONFIG_SYS_FPGA_COUNT 1 - -#define CONFIG_SYS_MCLINK_MAX 3 - -#define CONFIG_SYS_FPGA_PTR \ - { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } - -#define CONFIG_SYS_FPGA_NO_RFL_HI - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* Pass open firmware flat tree */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -#define CONFIG_PCA953X /* NXP PCA9554 */ -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ - {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } - -#define CONFIG_PCA9698 /* NXP PCA9698 */ - -#define CONFIG_SYS_I2C_IHS -#define CONFIG_SYS_I2C_IHS_CH0 -#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_IHS_CH1 -#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2 -#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F -#define CONFIG_SYS_I2C_IHS_CH3 -#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F - -#ifdef CONFIG_STRIDER_CON_DP -#define CONFIG_SYS_I2C_IHS_DUAL -#define CONFIG_SYS_I2C_IHS_CH0_1 -#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH1_1 -#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2_1 -#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH3_1 -#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F -#endif - -/* - * Software (bit-bang) I2C driver configuration - */ -#define CONFIG_SYS_I2C_SOFT -#define CONFIG_SOFT_I2C_READ_REPEATED_START -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define I2C_SOFT_DECLARATIONS2 -#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F -#define I2C_SOFT_DECLARATIONS3 -#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F -#define I2C_SOFT_DECLARATIONS4 -#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F -#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) -#define I2C_SOFT_DECLARATIONS5 -#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F -#define I2C_SOFT_DECLARATIONS6 -#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F -#define I2C_SOFT_DECLARATIONS7 -#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F -#define I2C_SOFT_DECLARATIONS8 -#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F -#endif -#ifdef CONFIG_STRIDER_CON_DP -#define I2C_SOFT_DECLARATIONS9 -#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F -#define I2C_SOFT_DECLARATIONS10 -#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F -#define I2C_SOFT_DECLARATIONS11 -#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F -#define I2C_SOFT_DECLARATIONS12 -#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F -#endif - -#ifdef CONFIG_STRIDER_CON -#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} -#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} -#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ - {12, 0x4c} } -#elif defined(CONFIG_STRIDER_CON_DP) -#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} -#define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} -#define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} -#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} -#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ - {12, 0x4c} } -#elif defined(CONFIG_STRIDER_CPU_DP) -#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} -#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ - {8, 0x4c} } -#else -#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} -#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ - {4, 0x18} } -#endif - -#ifndef __ASSEMBLY__ -void fpga_gpio_set(unsigned int bus, int pin); -void fpga_gpio_clear(unsigned int bus, int pin); -int fpga_gpio_get(unsigned int bus, int pin); -void fpga_control_set(unsigned int bus, int pin); -void fpga_control_clear(unsigned int bus, int pin); -#endif - -#ifdef CONFIG_STRIDER_CON -#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) -#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) -#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ - (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) -#elif defined(CONFIG_STRIDER_CON_DP) -#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) -#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) -#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) -#else -#define I2C_SDA_GPIO 0x0040 -#define I2C_SCL_GPIO 0x0020 -#define I2C_FPGA_IDX I2C_ADAP_HWNR -#endif - -#ifdef CONFIG_STRIDER_CON_DP -#define I2C_ACTIVE \ - do { \ - if (I2C_ADAP_HWNR > 7) \ - fpga_control_set(I2C_FPGA_IDX, 0x0004); \ - else \ - fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ - } while (0) -#else -#define I2C_ACTIVE { } -#endif - -#define I2C_TRISTATE { } -#define I2C_READ \ - (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - } while (0) -#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ - -/* - * Software (bit-bang) MII driver configuration - */ -#define CONFIG_BITBANGMII_MULTI - -/* - * OSD Setup - */ -#define CONFIG_SYS_OSD_SCREENS 1 -#define CONFIG_SYS_DP501_DIFFERENTIAL -#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ - -#ifdef CONFIG_STRIDER_CON_DP -#define CONFIG_SYS_OSD_DH -#endif - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -/* enable PCIE clock */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define TSEC1_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS 0 - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - - -#define CONFIG_HOSTNAME "hrcon" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "u-boot=u-boot.bin\0" \ - "kernel_addr=1000000\0" \ - "fdt_addr=C00000\0" \ - "fdtfile=hrcon.dtb\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp ${kernel_addr} $bootfile;" \ - "tftp ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_MMCBOOTCOMMAND \ - "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ - "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h deleted file mode 100644 index 2954baf165..0000000000 --- a/include/configs/tao3530.h +++ /dev/null @@ -1,222 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the TechNexion TAO-3530 SOM - * equipped on Thunder baseboard. - * - * Edward Lin <linuxfae@technexion.com> - * Tapani Utriainen <linuxfae@technexion.com> - * - * Copyright (C) 2013 Stefan Roese <sr@denx.de> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -/* commands to include */ - -#define CONFIG_SYS_I2C -#define CONFIG_I2C_MULTI_BUS - -/* - * TWL4030 - */ - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -/* Environment information */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ - "mpurate=600\0" \ - "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ - "tv_mode=omapfb.mode=tv:ntsc\0" \ - "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ - "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ - "extra_options= \0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "nandroot=ubi0:rootfs ubi.mtd=4\0" \ - "nandrootfstype=ubifs\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "${video_mode} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype} " \ - "${extra_options}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "${video_mode} " \ - "${network_setting} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype} "\ - "${extra_options}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ - -/* turn on command-line edit/hist/auto */ - - /* defaults */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE NAND_BASE - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * USB - * - * Currently only EHCI is enabled, the MUSB OTG controller - * is not enabled. - */ - -/* USB EHCI */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 - -/* Defines for SPL */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -/* - * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: - * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT - */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -/* - * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the - * older x-loader implementations. And move the BSS area so that it - * doesn't overlap with TEXT_BASE. - */ -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/titanium.h b/include/configs/titanium.h deleted file mode 100644 index 895c79f1a9..0000000000 --- a/include/configs/titanium.h +++ /dev/null @@ -1,151 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Stefan Roese <sr@denx.de> - * - * Configuration settings for the ProjectionDesign / Barco - * Titanium board. - * - * Based on mx6qsabrelite.h which is: - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 3769 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) - -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 4 - -/* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_HOSTNAME "titanium" -#define CONFIG_UBI_PART ubi -#define CONFIG_UBIFS_VOLUME rootfs0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel=" CONFIG_HOSTNAME "/uImage\0" \ - "kernel_fs=/boot/uImage\0" \ - "kernel_addr=11000000\0" \ - "dtb=" CONFIG_HOSTNAME "/" \ - CONFIG_HOSTNAME ".dtb\0" \ - "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \ - "dtb_addr=12800000\0" \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "console=ttymxc0\0" \ - "baudrate=115200\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "uimage=uImage\0" \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ - " ${script}\0" \ - "bootscript=echo Running bootscript from mmc ...; source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot} rootwait rw\0" \ - "bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ - " ${uimage}; bootm\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcon=setenv bootargs ${bootargs} console=ttymxc0," \ - "${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \ - "part=" __stringify(CONFIG_UBI_PART) "\0" \ - "boot_vol=0\0" \ - "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ - "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ - "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ - " ${filesize}\0" \ - "upd_ubifs=run load_ubifs update_ubifs\0" \ - "init_ubi=nand erase.part ubi;ubi part ${part};" \ - "ubi create ${vol} c800000\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ - " addcon addmtd;" \ - "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "ubifsargs=set bootargs ubi.mtd=ubi " \ - "root=ubi:rootfs${boot_vol} rootfstype=ubifs\0" \ - "ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0" \ - "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ - "ubifsload ${dtb_addr} ${dtb_fs};\0" \ - "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ - "addmtd;bootm ${kernel_addr} - ${dtb_addr}\0" \ - "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ - "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ - "net_nfs=run load_dtb load_kernel; " \ - "run nfsargs addip addcon addmtd;" \ - "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "delenv=env default -a -f; saveenv; reset\0" - -#define CONFIG_BOOTCOMMAND "run nand_ubifs" - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (512 << 20) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Enable NAND support */ -#ifdef CONFIG_CMD_NAND - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* Environment in NAND */ - -#else /* CONFIG_CMD_NAND */ - -/* Environment in MMC */ - -#endif /* CONFIG_CMD_NAND */ - -/* UBI/UBIFS config options */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h deleted file mode 100644 index 55f25857eb..0000000000 --- a/include/configs/tricorder.h +++ /dev/null @@ -1,236 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * (C) Copyright 2012 - * Corscience GmbH & Co. KG - * Thomas Weber <weber@corscience.de> - * - * Configuration settings for the Tricorder board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (1024*1024) - -/* Hardware drivers */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -/* select serial console configuration */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* I2C */ -#define CONFIG_SYS_I2C - - -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 - -/* TWL4030 */ - -/* Board NAND Info */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 - -/* needed for ubi */ - -/* Environment information (this is the common part) */ - - -/* hang() the board on panic() */ - -/* environment placement (for NAND), is different for FLASHCARD but does not - * harm there */ -#define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ - -/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend - * value can not be used here! */ -#define CONFIG_LOADADDR 0x82000000 - -#define CONFIG_COMMON_ENV_SETTINGS \ - "console=ttyO2,115200n8\0" \ - "mmcdev=0\0" \ - "vram=3M\0" \ - "defaultdisplay=lcd\0" \ - "kernelopts=mtdoops.mtddev=3\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "commonargs=" \ - "setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${kernelopts} " \ - "vt.global_cursor_default=0 " \ - "vram=${vram} " \ - "omapdss.def_disp=${defaultdisplay}\0" - -#define CONFIG_BOOTCOMMAND "run autoboot" - -/* specific environment settings for different use cases - * FLASHCARD: used to run a rdimage from sdcard to program the device - * 'NORMAL': used to boot kernel from sdcard, nand, ... - * - * The main aim for the FLASHCARD skin is to have an embedded environment - * which will not be influenced by any data already on the device. - */ -#ifdef CONFIG_FLASHCARD -/* the rdaddr is 16 MiB before the loadaddr */ -#define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_COMMON_ENV_SETTINGS \ - CONFIG_ENV_RDADDR \ - "autoboot=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ - "rdinit=/sbin/init; " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ - "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ - "bootm ${loadaddr} ${rdaddr}\0" - -#else /* CONFIG_FLASHCARD */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_COMMON_ENV_SETTINGS \ - "mmcargs=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p2 " \ - "rootwait " \ - "rw\0" \ - "nandargs=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "root=ubi0:root " \ - "ubi.mtd=7 " \ - "rootfstype=ubifs " \ - "ro\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "loaduimage_ubi=ubi part ubi; " \ - "ubifsmount ubi:root; " \ - "ubifsload ${loadaddr} /boot/uImage\0" \ - "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "run loaduimage_nand; " \ - "bootm ${loadaddr}\0" \ - "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi\0" - -#endif /* CONFIG_FLASHCARD */ - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* NAND and environment organization */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Defines for SPL */ - -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ - 13, 14, 16, 17, 18, 19, 20, 21, 22, \ - 23, 24, 25, 26, 27, 28, 30, 31, 32, \ - 33, 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 44, 45, 46, 47, 48, 49, 50, 51, \ - 52, 53, 54, 55, 56} - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ts4600.h b/include/configs/ts4600.h deleted file mode 100644 index ae9352f5b9..0000000000 --- a/include/configs/ts4600.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Savoir-faire Linux Inc. - * - * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> - * - * Derived from MX28EVK code by - * Fabio Estevam <fabio.estevam@freescale.com> - * Freescale Semiconductor, Inc. - * - * Configuration settings for the TS4600 Board - */ -#ifndef __CONFIGS_TS4600_H__ -#define __CONFIGS_TS4600_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Environment is in MMC */ - -/* Boot Linux */ -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_addr=0x41000000\0" \ - "loadkernel=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} imx28-ts4600.dtb\0" \ - "loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot.ub\0" \ - "bootscript=echo Running bootscript from mmc...; " \ - "setenv mmcdev 0; " \ - "setenv mmcpart 2; " \ - "run loadbootscript && source ${loadaddr}; \0" \ - "sdboot=echo Booting from SD card ...; " \ - "setenv mmcdev 0; " \ - "setenv mmcpart 2; " \ - "setenv root /dev/mmcblk0p3; " \ - "run loadkernel && run loadfdt; \0" \ - "startbootsequence=run bootscript || run sdboot \0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; " \ - "run startbootsequence; " \ - "setenv cmdline_append console=ttyAMA0,115200; " \ - "setenv bootargs root=${root} rootwait rw ${cmdline_append}; " \ - "bootz ${loadaddr} - ${fdt_addr}; " - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_TS4600_H__ */ diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h deleted file mode 100644 index f0630a7b92..0000000000 --- a/include/configs/ts4800.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Savoir-faire Linux Inc. - * - * Derived from MX51EVK code by - * Guennadi Liakhovetski <lg@denx.de> - * Freescale Semiconductor, Inc. - * - * Configuration settings for the TS4800 Board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ - -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ - -#define CONFIG_HW_WATCHDOG - -#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX - -/* text base address used when linking */ - -#include <asm/arch/imx-regs.h> - -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* - * MMC Configs - * */ -#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR - -/* - * Eth Configs - */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -/*********************************************************** - * Command definition - ***********************************************************/ - -/* Environment variables */ - - -#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdt_file=imx51-ts4800.dtb\0" \ - "fdt_addr=0x90fe0000\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ - "mmcargs=setenv bootargs root=${mmcroot}\0" \ - "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs addtty; " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo ERR: cannot load FDT; " \ - "fi; " - - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi; " - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Low level init */ -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 -#define CONFIG_SYS_MAIN_PWR_ON - -/*----------------------------------------------------------------------- - * Environment organization - */ - -#endif diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h deleted file mode 100644 index 4f8e63574d..0000000000 --- a/include/configs/vexpress_ca15_tc2.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Linaro - * Andre Przywara, <andre.przywara@linaro.org> - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA15X2_TC2_h -#define __VEXPRESS_CA15X2_TC2_h - -#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#include "vexpress_common.h" - -#define CONFIG_SYSFLAGS_ADDR 0x1c010030 -#define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR - -#endif diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h deleted file mode 100644 index b8079e63d6..0000000000 --- a/include/configs/vexpress_ca5x2.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Linaro - * Ryan Harkin, <ryan.harkin@linaro.org> - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA5X2_h -#define __VEXPRESS_CA5X2_h - -#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#include "vexpress_common.h" - -#endif /* __VEXPRESS_CA5X2_h */ diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h deleted file mode 100644 index 8157a5868d..0000000000 --- a/include/configs/vexpress_ca9x4.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Linaro - * Ryan Harkin, <ryan.harkin@linaro.org> - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA9X4_H -#define __VEXPRESS_CA9X4_H - -#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -#include "vexpress_common.h" - -#endif /* VEXPRESS_CA9X4_H */ diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h deleted file mode 100644 index cc7a688580..0000000000 --- a/include/configs/wb45n.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the WB45N CPU Module. - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -#include <asm/hardware.h> -#include <linux/stringify.h> - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 - -#define CONFIG_RBTREE - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_ETHADDR C0:EE:40:00:00:00 - -/* System */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#ifdef CONFIG_SYS_USE_NANDFLASH -/* bootstrap + u-boot + env + linux in nandflash */ - -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \ - "run _mtd; bootm" - -#define MTDIDS_DEFAULT "nand0=atmel_nand" -#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \ - "128K(at91bs)," \ - "512K(u-boot)," \ - "128K(u-boot-env)," \ - "128K(redund-env)," \ - "2560K(kernel-a)," \ - "2560K(kernel-b)," \ - "38912K(rootfs-a)," \ - "38912K(rootfs-b)," \ - "46208K(user)," \ - "512K(logs)" - -#else -#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \ - "autoload=no\0" \ - "autostart=no\0" \ - "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ - "\0" - -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x6000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif /* __CONFIG_H__ */ diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h deleted file mode 100644 index b1f3b8452c..0000000000 --- a/include/configs/wb50n.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the WB50N CPU Module. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/hardware.h> - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_DBGU - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x310000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* Ethernet Hardware */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_RGMII -#define CONFIG_ETHADDR C0:EE:40:00:00:00 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "autostart=no\0" - -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_BOOTCOMMAND \ - "nand read 0x22000000 0x000e0000 0x500000; " \ - "bootm" - -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h deleted file mode 100644 index 80849129b9..0000000000 --- a/include/configs/xfi3.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut <marex@denx.de> - */ -#ifndef __CONFIGS_XFI3_H__ -#define __CONFIGS_XFI3_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_FONT_4X6 -#define CONFIG_VIDEO_MXS_MODE_SYSTEM -#define CONFIG_SYS_BLACK_IN_WRITE -#define LCD_BPP LCD_COLOR16 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* The rest of the configuration is shared */ -#include <configs/mxs.h> - -#endif /* __CONFIGS_XFI3_H__ */ diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h deleted file mode 100644 index 7246b9eb65..0000000000 --- a/include/configs/zc5202.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic <sbabic@denx.de> - * - * Configuration settings for the E+L i.MX6Q DO82 board. - */ - -#ifndef __EL_ZC5202_H -#define __EL_ZC5202_H - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p2" - -#include "el6x_common.h" - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE MII100 -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX - -#endif /*__EL6Q_CONFIG_H */ diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h deleted file mode 100644 index e4fe7a462d..0000000000 --- a/include/configs/zc5601.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic <sbabic@denx.de> - * - * Configuration settings for the E+L i.MX6Q DO82 board. - */ - -#ifndef __EL_ZC5601_H -#define __EL_ZC5601_H - - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p1" - -#include "el6x_common.h" - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0x10 -#define CONFIG_FEC_FIXED_SPEED 1000 /* No autoneg, fix Gb */ - -#endif /*__EL6Q_CONFIG_H */ |