diff options
Diffstat (limited to 'include/configs/EB+MCF-EV123.h')
| -rw-r--r-- | include/configs/EB+MCF-EV123.h | 168 |
1 files changed, 84 insertions, 84 deletions
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index 72f7b3fe4f..876ec20ad1 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -27,7 +27,7 @@ #define CONFIG_EB_MCF_EV123 -#undef CFG_HALT_BEFOR_RAM_JUMP +#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP /* * High Level Configuration Options (easy to change) @@ -39,9 +39,9 @@ #define CONFIG_MISC_INIT_R #define CONFIG_MCFUART -#define CFG_UART_PORT (0) +#define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ @@ -91,22 +91,22 @@ # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 # define CONFIG_MII_INIT 1 -# define CFG_DISCOVER_PHY -# define CFG_RX_ETH_BUFFER 8 -# define CFG_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CFG_FEC0_PINMUX 0 -# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define CONFIG_SYS_FEC0_PINMUX 0 +# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE # define MCFFEC_TOUT_LOOP 50000 -/* If CFG_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CFG_DISCOVER_PHY +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL # define FECSPEED _100BASET # else -# ifndef CFG_FAULT_ECHO_LINK_DOWN -# define CFG_FAULT_ECHO_LINK_DOWN +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # endif -# endif /* CFG_DISCOVER_PHY */ +# endif /* CONFIG_SYS_DISCOVER_PHY */ #endif #ifdef CONFIG_MCFFEC @@ -119,146 +119,146 @@ #endif /* CONFIG_MCFFEC */ #define CONFIG_BOOTDELAY 5 -#define CFG_PROMPT "\nEV123 U-Boot> " -#define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "\nEV123 U-Boot> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x20000 +#define CONFIG_SYS_LOAD_ADDR 0x20000 -#define CFG_MEMTEST_START 0x100000 -#define CFG_MEMTEST_END 0x400000 -/*#define CFG_DRAM_TEST 1 */ -#undef CFG_DRAM_TEST +#define CONFIG_SYS_MEMTEST_START 0x100000 +#define CONFIG_SYS_MEMTEST_END 0x400000 +/*#define CONFIG_SYS_DRAM_TEST 1 */ +#undef CONFIG_SYS_DRAM_TEST /* Clock and PLL Configuration */ -#define CFG_HZ 10000000 -#define CFG_CLK 58982400 /* 9,8304MHz * 6 */ +#define CONFIG_SYS_HZ 10000000 +#define CONFIG_SYS_CLK 58982400 /* 9,8304MHz * 6 */ /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ -#define CFG_MFD 0x01 /* PLL Multiplication Factor Devider */ -#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */ +#define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */ +#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ -#define CFG_MBAR 0x40000000 +#define CONFIG_SYS_MBAR 0x40000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE1 0x00000000 -#define CFG_SDRAM_SIZE1 16 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_BASE1 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */ /* -#define CFG_SDRAM_BASE0 CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024 -#define CFG_SDRAM_SIZE0 16 */ /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_BASE0 CONFIG_SYS_SDRAM_BASE1+CONFIG_SYS_SDRAM_SIZE1*1024*1024 +#define CONFIG_SYS_SDRAM_SIZE0 16 */ /* SDRAM size in MB */ -#define CFG_SDRAM_BASE CFG_SDRAM_BASE1 -#define CFG_SDRAM_SIZE CFG_SDRAM_SIZE1 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1 +#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1 -#define CFG_FLASH_BASE 0xFFE00000 -#define CFG_INT_FLASH_BASE 0xF0000000 -#define CFG_INT_FLASH_ENABLE 0x21 +#define CONFIG_SYS_FLASH_BASE 0xFFE00000 +#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 +#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 /* If M5282 port is fully implemented the monitor base will be behind * the vector table. */ -#if (TEXT_BASE != CFG_INT_FLASH_BASE) -#define CFG_MONITOR_BASE (TEXT_BASE + 0x400) +#if (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) +#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) #else -#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ +#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ #endif -#define CFG_MONITOR_LEN 0x20000 -#define CFG_MALLOC_LEN (256 << 10) -#define CFG_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MONITOR_LEN 0x20000 +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_SECT 35 -#define CFG_MAX_FLASH_BANKS 2 -#define CFG_FLASH_ERASE_TOUT 10000000 -#define CFG_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_SECT 35 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 +#define CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 16 +#define CONFIG_SYS_CACHELINE_SIZE 16 /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CFG_CS0_BASE CFG_FLASH_BASE -#define CFG_CS0_SIZE 2*1024*1024 -#define CFG_CS0_WIDTH 16 -#define CFG_CS0_RO 0 -#define CFG_CS0_WS 6 +#define CONFIG_SYS_CS0_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE 2*1024*1024 +#define CONFIG_SYS_CS0_WIDTH 16 +#define CONFIG_SYS_CS0_RO 0 +#define CONFIG_SYS_CS0_WS 6 -#define CFG_CS3_BASE 0xE0000000 -#define CFG_CS3_SIZE 1*1024*1024 -#define CFG_CS3_WIDTH 16 -#define CFG_CS3_RO 0 -#define CFG_CS3_WS 6 +#define CONFIG_SYS_CS3_BASE 0xE0000000 +#define CONFIG_SYS_CS3_SIZE 1*1024*1024 +#define CONFIG_SYS_CS3_WIDTH 16 +#define CONFIG_SYS_CS3_RO 0 +#define CONFIG_SYS_CS3_WS 6 /*----------------------------------------------------------------------- * Port configuration */ -#define CFG_PACNT 0x0000000 /* Port A D[31:24] */ -#define CFG_PADDR 0x0000000 -#define CFG_PADAT 0x0000000 +#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CONFIG_SYS_PADDR 0x0000000 +#define CONFIG_SYS_PADAT 0x0000000 -#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CFG_PBDDR 0x0000000 -#define CFG_PBDAT 0x0000000 +#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CONFIG_SYS_PBDDR 0x0000000 +#define CONFIG_SYS_PBDAT 0x0000000 -#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CFG_PCDDR 0x0000000 -#define CFG_PCDAT 0x0000000 +#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ +#define CONFIG_SYS_PCDDR 0x0000000 +#define CONFIG_SYS_PCDAT 0x0000000 -#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CFG_PCDDR 0x0000000 -#define CFG_PCDAT 0x0000000 +#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CONFIG_SYS_PCDDR 0x0000000 +#define CONFIG_SYS_PCDAT 0x0000000 -#define CFG_PEHLPAR 0xC0 -#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ -#define CFG_DDRUA 0x05 -#define CFG_PJPAR 0xFF +#define CONFIG_SYS_PEHLPAR 0xC0 +#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ +#define CONFIG_SYS_DDRUA 0x05 +#define CONFIG_SYS_PJPAR 0xFF /*----------------------------------------------------------------------- * CCM configuration */ -#define CFG_CCM_SIZ 0 +#define CONFIG_SYS_CCM_SIZ 0 /*---------------------------------------------------------------------*/ #endif /* _CONFIG_M5282EVB_H */ |