diff options
Diffstat (limited to 'drivers')
49 files changed, 2399 insertions, 1135 deletions
diff --git a/drivers/block/Makefile b/drivers/block/Makefile index dea2c15c14..d06a598f14 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -12,7 +12,6 @@ obj-y += blk_legacy.o endif obj-$(CONFIG_IDE) += ide.o -obj-$(CONFIG_IDE_FTIDE020) += ftide020.o obj-$(CONFIG_SANDBOX) += sandbox.o obj-$(CONFIG_SYSTEMACE) += systemace.o obj-$(CONFIG_BLOCK_CACHE) += blkcache.o diff --git a/drivers/block/ftide020.c b/drivers/block/ftide020.c deleted file mode 100644 index 1f6995ec2e..0000000000 --- a/drivers/block/ftide020.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Faraday FTIDE020 ATA Controller (AHB) - * - * (C) Copyright 2011 Andes Technology - * Greentime Hu <greentime@andestech.com> - * Macpaul Lin <macpaul@andestech.com> - * Kuo-Wei Chou <kwchou@andestech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* ftide020.c - ide support functions for the FTIDE020_S controller */ - -#include <config.h> -#include <common.h> -#include <ata.h> -#include <ide.h> -#include <asm/io.h> -#include <api_public.h> - -#include "ftide020.h" - -/* base address */ -#define FTIDE_BASE CONFIG_SYS_ATA_BASE_ADDR - -/* - * data address - The CMD and DATA use the same FIFO in FTIDE020_S - * FTIDE_DATA = CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_DATA_OFFSET - * = &ftide020->rw_fifo - */ -#define FTIDE_DATA (&ftide020->rw_fifo) - -/* command and data I/O macros */ -/* 0x0 - DATA FIFO */ -#define WRITE_DATA(x) outl((x), &ftide020->rw_fifo) /* 0x00 */ -#define READ_DATA() inl(&ftide020->rw_fifo) /* 0x00 */ -/* 0x04 - R: Status Reg, W: CMD_FIFO */ -#define WRITE_CMD(x) outl((x), &ftide020->cmd_fifo) /* 0x04 */ -#define READ_STATUS() inl(&ftide020->cmd_fifo) /* 0x04 */ - -void ftide_set_device(int cx8, int dev) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - - WRITE_CMD(SET_DEV_CMD | IDE_SET_CX8(cx8) | dev); -} - -unsigned char ide_read_register(int dev, unsigned int port) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - - ftide_set_device(0, dev); - WRITE_CMD(READ_REG_CMD | IDE_REG_CS_READ(CONFIG_IDE_REG_CS) | - IDE_REG_DA_WRITE(port)); - - return READ_DATA() & 0xff; -} - -void ide_write_register(int dev, unsigned int port, unsigned char val) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - - ftide_set_device(0, dev); - WRITE_CMD(WRITE_REG_CMD | IDE_REG_CS_WRITE(CONFIG_IDE_REG_CS) | - IDE_REG_DA_WRITE(port) | val); -} - -void ide_write_data(int dev, const ulong *sect_buf, int words) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - - ftide_set_device(0, dev); - WRITE_CMD(WRITE_DATA_CMD | ((words << 2) - 1)); - - /* block write */ - outsl(FTIDE_DATA, sect_buf, words); -} - -void ide_read_data(int dev, ulong *sect_buf, int words) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - - ftide_set_device(0, dev); - WRITE_CMD(READ_DATA_CMD | ((words << 2) - 1)); - - /* block read */ - insl(FTIDE_DATA, sect_buf, words); -} - -void ftide_dfifo_ready(ulong *time) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - - while (!(READ_STATUS() & STATUS_RFE)) { - if (*time-- == 0) - break; - - udelay(100); - } -} - -extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; - -/* Reset_IDE_controller */ -static void reset_ide_controller(void) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - unsigned int val; - - val = inl(&ftide020->cr); - - val |= CONTROL_RST; - outl(val, &ftide020->cr); - - /* wait until reset OK, this is poor HW design */ - mdelay(50); - val &= ~(CONTROL_RST); - outl(val, &ftide020->cr); - - mdelay(50); - val |= CONTROL_SRST; - outl(val, &ftide020->cr); - - /* wait until reset OK, this is poor HW design */ - mdelay(50); - val &= ~(CONTROL_SRST); - outl(val, &ftide020->cr); - - /* IORDY enable for PIO, for 2 device */ - val |= (CONTROL_IRE0 | CONTROL_IRE1); - outl(val, &ftide020->cr); -} - -/* IDE clock frequence */ -uint ftide_clock_freq(void) -{ - /* - * todo: To aquire dynamic system frequency is dependend on the power - * management unit which the ftide020 is connected to. In current, - * there are only few PMU supports in u-boot. - * So this function is wait for future enhancement. - */ - return 100; -} - -/* Calculate Timing Registers */ -static unsigned int timing_cal(u16 t0, u16 t1, u16 t2, u16 t4) -{ - unsigned int val, ahb_ns = 8; - u8 TEOC, T1, T2, T4; - - T1 = (u8) (t1 / ahb_ns); - if ((T1 * ahb_ns) == t1) - T1--; - - T2 = (u8) (t2 / ahb_ns); - if ((T2 * ahb_ns) == t2) - T2--; - - T4 = (u8) (t4 / ahb_ns); - if ((T4 * ahb_ns) == t4) - T4--; - - TEOC = (u8) (t0 / ahb_ns); - if ((TEOC * ahb_ns) == t0) - TEOC--; - - TEOC = ((TEOC > (T1 + T2 + T4)) ? (TEOC - (T1 + T2 + T4)) : 0); - - /* - * Here the fields in data timing registers in PIO mode - * is accessed the same way as command timing registers. - */ - val = DT_REG_PIO_T1(T1) | - DT_REG_PIO_T2(T2) | - DT_REG_PIO_T4(T4) | - DT_REG_PIO_TEOC(TEOC); - - return val; -} - -/* Set Timing Register */ -static unsigned int set_mode_timing(u8 dev, u8 id, u8 mode) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - u16 t0, t1, t2, t4; - u8 tcyc, tcvs, tmli, tenv, tack, trp; - unsigned int val, sysclk = 8; - - if (id >= TATOL_TIMING) - return 0; - - sysclk = ftide_clock_freq(); - switch (id) { - case CMD_TIMING: - if (mode < REG_MODE) { - t0 = REG_ACCESS_TIMING[REG_T0][mode]; - t1 = REG_ACCESS_TIMING[REG_T1][mode]; - t2 = REG_ACCESS_TIMING[REG_T2][mode]; - t4 = REG_ACCESS_TIMING[REG_T4][mode]; - - val = timing_cal(t0, t1, t2, t4); - outl(val, (dev ? &ftide020->ctrd1 : &ftide020->ctrd0)); - return 1; - } else - return 0; - case PIO_TIMING: - if (mode < PIO_MODE) { - t0 = PIO_ACCESS_TIMING[PIO_T0][mode]; - t1 = PIO_ACCESS_TIMING[PIO_T1][mode]; - t2 = PIO_ACCESS_TIMING[PIO_T2][mode]; - t4 = PIO_ACCESS_TIMING[PIO_T4][mode]; - - val = timing_cal(t0, t1, t2, t4); - - outl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0)); - return 1; - } else - return 0; - case DMA_TIMING: - if (mode < UDMA_MODE) { - /* - * 0.999 is ceiling - * for tcyc, tcvs, tmli, tenv, trp, tack - */ - tcyc = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCYC][mode] \ - * sysclk) + 9990) / 10000); - tcvs = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCVS][mode] \ - * sysclk) + 9990) / 10000); - tmli = (u8) (((UDMA_ACCESS_TIMING[UDMA_TMLI][mode] \ - * sysclk) + 9990) / 10000); - tenv = (u8) (((UDMA_ACCESS_TIMING[UDMA_TENV][mode] \ - * sysclk) + 9990) / 10000); - trp = (u8) (((UDMA_ACCESS_TIMING[UDMA_TRP][mode] \ - * sysclk) + 9990) / 10000); - tack = (u8) (((UDMA_ACCESS_TIMING[UDMA_TACK][mode] \ - * sysclk) + 9990) / 10000); - - val = DT_REG_UDMA_TENV((tenv > 0) ? (tenv - 1) : 0) | - DT_REG_UDMA_TMLI((tmli > 0) ? (tmli - 1) : 0) | - DT_REG_UDMA_TCYC((tcyc > 0) ? (tcyc - 1) : 0) | - DT_REG_UDMA_TACK((tack > 0) ? (tack - 1) : 0) | - DT_REG_UDMA_TCVS((tcvs > 0) ? (tcvs - 1) : 0) | - DT_REG_UDMA_TRP((trp > 0) ? (trp - 1) : 0); - - outl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0)); - return 1; - } else - return 0; - default: - return 0; - } -} - -static void ftide_read_hwrev(void) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - unsigned int rev; - - rev = inl(&ftide020->revision); -} - -static int ftide_controller_probe(void) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - unsigned int bak; - - bak = inl(&ftide020->ctrd1); - - /* probing by using shorter setup time */ - outl(CONFIG_CTRD1_PROBE_T1, &ftide020->ctrd1); - if ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T1) { - outl(bak, &ftide020->ctrd1); - return 0; - } - - /* probing by using longer setup time */ - outl(CONFIG_CTRD1_PROBE_T2, &ftide020->ctrd1); - if ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T2) { - outl(bak, &ftide020->ctrd1); - return 0; - } - - outl(bak, &ftide020->ctrd1); - - return 1; -} - -/* ide_preinit() was migrated from linux driver ide_probe_for_ftide() */ -int ide_preinit(void) -{ - static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE; - int status; - unsigned int val; - int i; - - status = 1; - for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; i++) - ide_bus_offset[i] = -ATA_STATUS; - - /* auto-detect IDE controller */ - if (ftide_controller_probe()) { - printf("FTIDE020_S\n"); - } else { - printf("FTIDE020_S ATA controller not found.\n"); - return API_ENODEV; - } - - /* check HW IP revision */ - ftide_read_hwrev(); - - /* set FIFO threshold */ - outl(((WRITE_FIFO - RX_THRESH) << 16) | RX_THRESH, &ftide020->dmatirr); - - /* set Device_0 PIO_4 timing */ - set_mode_timing(0, CMD_TIMING, REG_MODE4); - set_mode_timing(0, PIO_TIMING, PIO_MODE4); - - /* set Device_1 PIO_4 timing */ - set_mode_timing(1, CMD_TIMING, REG_MODE4); - set_mode_timing(1, PIO_TIMING, PIO_MODE4); - - /* from E-bios */ - /* little endian */ - outl(0x0, &ftide020->cr); - mdelay(10); - - outl(0x0fff0fff, &ftide020->ahbtr); - mdelay(10); - - /* Enable controller Interrupt */ - val = inl(&ftide020->cr); - - /* Enable: IDE IRQ, IDE Terminate ERROR IRQ, AHB Timeout error IRQ */ - val |= (CONTROL_IIE | CONTROL_TERIE | CONTROL_AERIE); - outl(val, &ftide020->cr); - - status = 0; - - return status; -} - -void ide_set_reset(int flag) -{ - debug("ide_set_reset()\n"); - reset_ide_controller(); - return; -} diff --git a/drivers/block/ftide020.h b/drivers/block/ftide020.h deleted file mode 100644 index 2d88c7ce77..0000000000 --- a/drivers/block/ftide020.h +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Faraday FTIDE020_s ATA Controller (AHB) - * - * (C) Copyright 2011 Andes Technology - * Greentime Hu <greentime@andestech.com> - * Macpaul Lin <macpaul@andestech.com> - * Kuo-Wei Chou <kwchou@andestech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FTIDE020_H -#define __FTIDE020_H - -/* ftide020.h - ide support functions for the FTIDE020_S controller */ - -/* ATA controller register offset */ -struct ftide020_s { - unsigned int rw_fifo; /* 0x00 - READ/WRITE FIFO */ - unsigned int cmd_fifo; /* 0x04 - R: Status Reg, W: CMD_FIFO */ - unsigned int cr; /* 0x08 - Control Reg */ - unsigned int dmatirr; /* 0x0c - DMA Threshold/Interrupt Reg */ - unsigned int ctrd0; /* 0x10 - Command Timing Reg Device 0 */ - unsigned int dtrd0; /* 0x14 - Data Timing Reg Device 0 */ - unsigned int ctrd1; /* 0x18 - Command Timing Reg Device 1 */ - unsigned int dtrd1; /* 0x1c - Data Timing Reg Device 1 */ - unsigned int ahbtr; /* 0x20 - AHB Timeout Reg */ - unsigned int RESVD0; /* 0x24 */ - unsigned int RESVD1; /* 0x28 */ - unsigned int RESVD2; /* 0x2c */ - unsigned int f_cfifo; /* 0x30 - Feature Info of CMD_FIFO */ - unsigned int f_wfifo; /* 0x34 - Feature Info of WRITE_FIFO */ - unsigned int f_rfifo; /* 0x3c - Feature Info of READ_FIFO */ - unsigned int revision; /* 0x38 - Revision No. of FTIDE020_S */ -}; - -/* reference parameters */ -#define CONFIG_IDE_REG_CS 0x2 /* ref: ATA spec chaper 10, table 42 */ -#define CONFIG_CTRD1_PROBE_T1 0x2 -#define CONFIG_CTRD1_PROBE_T2 0x5 - -/* status register - 0x04 */ -#define STATUS_CSEL (1 << 0) /* CSEL */ -#define STATUS_CS(x) (((x) >> 1) & 0x3) /* CS#[1:0] */ -#define STATUS_DMACK (1 << 3) /* DMACK# */ -#define STATUS_DMARQ (1 << 4) /* DMA req */ -#define STATUS_INTRQ (1 << 5) /* INT req */ -#define STATUS_DIOR (1 << 6) /* DIOR */ -#define STATUS_IORDY (1 << 7) /* I/O ready */ -#define STATUS_DIOW (1 << 8) /* DIOW# */ -#define STATUS_PDIAG (1 << 9) /* PDIAG */ -#define STATUS_DASP (1 << 10) /* DASP# */ -#define STATUS_DEV (1 << 11) /* selected device */ -#define STATUS_PIO (1 << 12) /* PIO in progress */ -#define STATUS_DMA (1 << 13) /* DMA in progress */ -#define STATUS_WFE (1 << 14) /* write fifo full */ -#define STATUS_RFE (1 << 15) /* read fifo empty */ -#define STATUS_COUNTER(x) (((x) >> 16) & 0x3fff) /* data tx counter */ -#define STATUS_ERR (1 << 30) /* trasfer terminated */ -#define STATUS_AER (1 << 31) /* AHB timeout indicate */ - -/* Control register - 0x08 */ -#define CONTROL_TYPE_PIO 0x0 -#define CONTROL_TYPE_UDMA 0x1 - -/* Device 0 */ -#define CONTROL_TYP0(x) (((x) & 0x7) << 0) -#define CONTROL_IRE0 (1 << 3) /* enable IORDY for PIO */ -#define CONTROL_RESVD_DW0 (1 << 4) /* Reserved - DW0 ? */ -#define CONTROL_E0 (1 << 5) /* E0: 1: Big Endian */ -#define CONTROL_RESVD_WP0 (1 << 6) /* Reserved - WP0 ? */ -#define CONTROL_RESVD_SE0 (1 << 7) /* Reserved - SE0 ? */ -#define CONTROL_RESVD_ECC0 (1 << 8) /* Reserved - ECC0 ? */ - -#define CONTROL_RAEIE (1 << 9) /* IRQ - read fifo almost full */ -#define CONTROL_RNEIE (1 << 10) /* IRQ - read fifo not empty */ -#define CONTROL_WAFIE (1 << 11) /* IRQ - write fifo almost empty */ -#define CONTROL_WNFIE (1 << 12) /* IRQ - write fifo not full */ -#define CONTROL_RESVD_FIRQ (1 << 13) /* RESERVED - FIRQ ? */ -#define CONTROL_AERIE (1 << 14) /* IRQ - AHB timeout error */ -#define CONTROL_IIE (1 << 15) /* IDE IRQ enable */ - -/* Device 1 */ -#define CONTROL_TYP1(x) (((x) & 0x7) << 16) -#define CONTROL_IRE1 (1 << 19) /* enable IORDY for PIO */ -#define CONTROL_RESVD_DW1 (1 << 20) /* Reserved - DW1 ? */ -#define CONTROL_E1 (1 << 21) /* E1: 1: Big Endian */ -#define CONTROL_RESVD_WP1 (1 << 22) /* Reserved - WP1 ? */ -#define CONTROL_RESVD_SE1 (1 << 23) /* Reserved - SE1 ? */ -#define CONTROL_RESVD_ECC1 (1 << 24) /* Reserved - ECC1 ? */ - -#define CONTROL_DRE (1 << 25) /* DMA receive enable */ -#define CONTROL_DTE (1 << 26) /* DMA transmit enable */ -#define CONTRIL_RESVD (1 << 27) -#define CONTROL_TERIE (1 << 28) /* transfer terminate error IRQ */ -#define CONTROL_T (1 << 29) /* terminate current operation */ -#define CONTROL_SRST (1 << 30) /* IDE soft reset */ -#define CONTROL_RST (1 << 31) /* IDE hardware reset */ - -/* IRQ register - 0x0c */ -#define IRQ_RXTHRESH(x) (((x) & 0x3ff) << 0) /* Read FIFO threshold */ -#define IRQ_RFAEIRQ (1 << 10) /* Read FIFO almost full intr req */ -#define IRQ_RFNEIRQ (1 << 11) /* Read FIFO not empty intr req */ -#define IRQ_WFAFIRQ (1 << 12) /* Write FIFO almost empty int req */ -#define IRQ_WFNFIRQ (1 << 13) /* Write FIFO not full intr req */ -#define IRQ_RESVD_FIRQ (1 << 14) /* Reserved - FIRQ ? */ -#define IRQ_IIRQ (1 << 15) /* IDE device interrupt request */ -#define IRQ_TXTHRESH(x) (((x) & 0x3ff) << 16) /* Write FIFO thershold */ -#define IRQ_TERMERR (1 << 28) /* Transfer termination indication */ -#define IRQ_AHBERR (1 << 29) /* AHB Timeout indication */ - -/* Command Timing Register 0-1: ctrd (0x10, 0x18) */ -#define CT_REG_T1(x) (((x) & 0xff) << 0) /* setup time of addressed */ -#define CT_REG_T2(x) (((x) & 0xff) << 8) /* pluse width of DIOR/DIOW */ -#define CT_REG_T4(x) (((x) & 0xff) << 16) /* data hold time */ -#define CT_REG_TEOC(x) (((x) & 0xff) << 24) /* time to the end of a cycle */ - -/* Data Timing Register 0-1: dtrd (0x14, 0x1c) */ -/* - * PIO mode: - * b(0:7) DT_REG_PIO_T1: the setup time of addressed - * b(8:15) DT_REG_PIO_T2: the pluse width of DIOR/DIOW - * b(16:23) DT_REG_PIO_T4: data hold time - * b(24:31) DT_REG_PIO_TEOC: the time to the end of a cycle - */ -#define DT_REG_PIO_T1(x) (((x) & 0xff) << 0) -#define DT_REG_PIO_T2(x) (((x) & 0xff) << 8) -#define DT_REG_PIO_T4(x) (((x) & 0xff) << 16) -#define DT_REG_PIO_TEOC(x) (((x) & 0xff) << 24) - -/* - * UDMA mode: - * b(0:3) DT_REG_UDMA_TENV: the envelope time - * b(4:7) DT_REG_UDMA_TMLI: interlock time - * b(8:15) DT_REG_UDMA_TCYC: cycle time - data time - * b(16:19) DT_REG_UDMA_TACK: setup and hold time of DMACK - * b(23:30) DT_REG_UDMA_TCVS: setup time of CRC - * b(24:31) DT_REG_UDMA_TRP: time to ready to pause - */ -#define DT_REG_UDMA_TENV(x) (((x) & 0xf) << 0) -#define DT_REG_UDMA_TMLI(x) (((x) & 0xf) << 4) -#define DT_REG_UDMA_TCYC(x) (((x) & 0xff) << 8) -#define DT_REG_UDMA_TACK(x) (((x) & 0xf) << 16) -#define DT_REG_UDMA_TCVS(x) (((x) & 0xf) << 20) -#define DT_REG_UDMA_TRP(x) (((x) & 0xff) << 24) - -/* ftide020_s command formats */ -/* read: IDE Register (CF1) */ -#define IDE_REG_OPCODE_READ (1 << 13) /* 0x2000 */ -#define IDE_REG_CS_READ(x) (((x) & 0x3) << 11) -#define IDE_REG_DA_READ(x) (((x) & 0x7) << 8) -#define IDE_REG_CMD_READ(x) 0x0 /* fixed value */ - -/* write: IDE Register (CF2) */ -#define IDE_REG_OPCODE_WRITE (0x5 << 13) /* 0xA000 */ -#define IDE_REG_CS_WRITE(x) (((x) & 0x3) << 11) -#define IDE_REG_DA_WRITE(x) (((x) & 0x7) << 8) -/* b(0:7) IDE_REG_CMD_WRITE(x): Actual ATA command or data */ -#define IDE_REG_CMD_WRITE(x) (((x) & 0xff) << 0) - -/* read/write data: PIO/UDMA (CF3) */ -#define IDE_DATA_WRITE (1 << 15) /* read: 0, write: 1 */ -#define IDE_DATA_OPCODE (0x2 << 13) /* device data access opcode */ -/* b(0:12) IDE_DATA_COUNTER(x): Number of transfers minus 1 */ -#define IDE_DATA_COUNTER(x) (((x) & 0x1fff) << 0) - -/* set device: (CF4) */ -#define IDE_SET_OPCODE (0x2740 << 2) /* [15:2], 0x9d00 */ -/* CF3 counter value: 0: Tx in bytes, 1: in blocks (each block is 8 bytes) */ -#define IDE_SET_CX8(x) (((x) & 0x1) << 1) -#define IDE_SET_DEV(x) (((x) & 0x1) << 0) /* 0: Master, 1: Slave */ - -/* - * IDE command bit definition - * This section is designed for minor hardware revision compatibility. - */ -#define READ_REG_CMD IDE_REG_OPCODE_READ /* 0x2000 */ -#define WRITE_REG_CMD IDE_REG_OPCODE_WRITE /* 0xA000 */ -#define READ_DATA_CMD IDE_DATA_OPCODE /* 0x4000 */ -#define WRITE_DATA_CMD (IDE_DATA_OPCODE | IDE_DATA_WRITE) /* 0xC000 */ -#define SET_DEV_CMD IDE_SET_OPCODE /* 0x9D00 */ - -#define TATOL_TIMING 3 -#define CMD_TIMING 0 -#define PIO_TIMING 1 -#define DMA_TIMING 2 - -/* Timing Parameters */ -/* Register Access Timing Parameters */ -#define REG_PARAMETER 4 -#define REG_T0 0 -#define REG_T1 1 -#define REG_T2 2 -#define REG_T4 3 - -#define REG_MODE 5 -#define REG_MODE0 0 -#define REG_MODE1 1 -#define REG_MODE2 2 -#define REG_MODE3 3 -#define REG_MODE4 4 - -/* PIO Access Timing Parameters */ -#define PIO_PARAMETER 4 -#define PIO_T0 0 -#define PIO_T1 1 -#define PIO_T2 2 -#define PIO_T4 3 - -#define PIO_MODE 5 -#define PIO_MODE0 0 -#define PIO_MODE1 1 -#define PIO_MODE2 2 -#define PIO_MODE3 3 -#define PIO_MODE4 4 - -/* UDMA Access Timing Parameters */ -#define UDMA_PARAMETER 6 -#define UDMA_TCYC 0 -#define UDMA_TCVS 1 -#define UDMA_TMLI 2 -#define UDMA_TENV 3 -#define UDMA_TRP 4 -#define UDMA_TACK 5 - -#define UDMA_MODE 7 -#define UDMA_MODE0 0 -#define UDMA_MODE1 1 -#define UDMA_MODE2 2 -#define UDMA_MODE3 3 -#define UDMA_MODE4 4 -#define UDMA_MODE5 5 -#define UDMA_MODE6 6 - -/* - * RX_THRESH: - * hardware limitation: max = 8, should support 1,4,8,16,32,64,128,256 - */ -#define RX_THRESH 8 -#define WRITE_FIFO 32 /* Hardwired value */ - -/* Time Table */ -unsigned int REG_ACCESS_TIMING[REG_PARAMETER][REG_MODE] = { - {600, 383, 330, 180, 120}, - {70, 50, 30, 30, 25}, - {290, 290, 290, 80, 70}, - {30, 20, 15, 10, 10}, -}; - -unsigned int PIO_ACCESS_TIMING[PIO_PARAMETER][PIO_MODE] = { - {600, 383, 240, 180, 120}, - {70, 50, 30, 30, 25}, - {165, 125, 100, 80, 70}, - {30, 20, 15, 10, 10}, -}; - -unsigned int UDMA_ACCESS_TIMING[UDMA_PARAMETER][UDMA_MODE] = { - {1120, 730, 540, 390, 250, 168, 130}, /* 10X */ - {700, 480, 310, 200, 67, 100, 100}, /* 10X */ - {200, 200, 200, 200, 200, 200, 200}, /* 10X */ - {200, 200, 200, 200, 200, 200, 200}, /* 10X */ - {1600, 1250, 1000, 1000, 1000, 850, 850}, /* 10X */ - {200, 200, 200, 200, 200, 200, 200}, /* 10X */ -}; - -#endif /* __FTIDE020_H */ diff --git a/drivers/block/ide.c b/drivers/block/ide.c index edcf87b8c1..ce51153099 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -44,12 +44,6 @@ struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE]; #define CONFIG_SYS_ATA_PORT_ADDR(port) (port) #endif -#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */ -# define DEVICE_LED(x) 0 -# define LED_IDE1 1 -# define LED_IDE2 2 -#endif - #ifdef CONFIG_IDE_RESET extern void ide_set_reset(int idereset); @@ -217,8 +211,6 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen, unsigned char c, err, mask, res; int n; - ide_led(DEVICE_LED(device), 1); /* LED on */ - /* Select device */ mask = ATA_STAT_BUSY | ATA_STAT_DRQ; @@ -326,7 +318,6 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen, err = 0; } AI_OUT: - ide_led(DEVICE_LED(device), 0); /* LED off */ return err; } @@ -560,7 +551,6 @@ static void ide_ident(struct blk_desc *dev_desc) device = dev_desc->devnum; printf(" Device %d: ", device); - ide_led(DEVICE_LED(device), 1); /* LED on */ /* Select device */ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); @@ -600,7 +590,6 @@ static void ide_ident(struct blk_desc *dev_desc) */ c = ide_wait(device, IDE_TIME_OUT); } - ide_led(DEVICE_LED(device), 0); /* LED off */ if (((c & ATA_STAT_DRQ) == 0) || ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) { @@ -716,22 +705,6 @@ static void ide_ident(struct blk_desc *dev_desc) #endif } -__weak void ide_led(uchar led, uchar status) -{ -#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */ - static uchar led_buffer; /* Buffer for current LED status */ - - uchar *led_port = LED_PORT; - - if (status) /* switch LED on */ - led_buffer |= led; - else /* switch LED off */ - led_buffer &= ~led; - - *led_port = led_buffer; -#endif -} - __weak void ide_outb(int dev, int port, unsigned char val) { debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", @@ -783,24 +756,9 @@ void ide_init(void) WATCHDOG_RESET(); - /* - * Reset the IDE just to be sure. - * Light LED's to show - */ - ide_led((LED_IDE1 | LED_IDE2), 1); /* LED's on */ - /* ATAPI Drives seems to need a proper IDE Reset */ ide_reset(); -#ifdef CONFIG_IDE_INIT_POSTRESET - WATCHDOG_RESET(); - - if (ide_init_postreset()) { - puts("ide_preinit_postreset failed\n"); - return; - } -#endif /* CONFIG_IDE_INIT_POSTRESET */ - /* * Wait for IDE to get ready. * According to spec, this can take up to 31 seconds! @@ -827,8 +785,6 @@ void ide_init(void) i++; if (i > (ATA_RESET_TIME * 100)) { puts("** Timeout **\n"); - /* LED's off */ - ide_led((LED_IDE1 | LED_IDE2), 0); return; } if ((i >= 100) && ((i % 100) == 0)) @@ -853,10 +809,7 @@ void ide_init(void) putc('\n'); - ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */ - for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) { - int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2; ide_dev_desc[i].type = DEV_TYPE_UNKNOWN; ide_dev_desc[i].if_type = IF_TYPE_IDE; ide_dev_desc[i].devnum = i; @@ -871,9 +824,7 @@ void ide_init(void) #endif if (!ide_bus_ok[IDE_BUS(i)]) continue; - ide_led(led, 1); /* LED on */ ide_ident(&ide_dev_desc[i]); - ide_led(led, 0); /* LED off */ dev_print(&ide_dev_desc[i]); if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) { @@ -996,8 +947,6 @@ ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer); - ide_led(DEVICE_LED(device), 1); /* LED on */ - /* Select device */ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); @@ -1095,7 +1044,6 @@ ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, buffer += ATA_BLOCKSIZE; } IDE_READ_E: - ide_led(DEVICE_LED(device), 0); /* LED off */ return n; } @@ -1123,8 +1071,6 @@ ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, } #endif - ide_led(DEVICE_LED(device), 1); /* LED on */ - /* Select device */ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); @@ -1188,7 +1134,6 @@ ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, buffer += ATA_BLOCKSIZE; } WR_OUT: - ide_led(DEVICE_LED(device), 0); /* LED off */ return n; } diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile index ed623aa56f..54c7e09bd6 100644 --- a/drivers/clk/uniphier/Makefile +++ b/drivers/clk/uniphier/Makefile @@ -1,2 +1,3 @@ obj-y += clk-uniphier-core.o +obj-y += clk-uniphier-sys.o obj-y += clk-uniphier-mio.o diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index eed21b9a68..722cd6b060 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -146,6 +146,36 @@ static int uniphier_clk_probe(struct udevice *dev) } static const struct udevice_id uniphier_clk_match[] = { + /* System clock */ + { + .compatible = "socionext,uniphier-ld4-clock", + .data = (ulong)&uniphier_pxs2_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-pro4-clock", + .data = (ulong)&uniphier_pxs2_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-sld8-clock", + .data = (ulong)&uniphier_pxs2_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-pro5-clock", + .data = (ulong)&uniphier_pxs2_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-pxs2-clock", + .data = (ulong)&uniphier_pxs2_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-ld11-clock", + .data = (ulong)&uniphier_ld20_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-ld20-clock", + .data = (ulong)&uniphier_ld20_sys_clk_data, + }, + /* Media I/O clock */ { .compatible = "socionext,uniphier-ld4-mio-clock", .data = (ulong)&uniphier_mio_clk_data, diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c new file mode 100644 index 0000000000..709fa5081a --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016-2017 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "clk-uniphier.h" + +const struct uniphier_clk_gate_data uniphier_pxs2_sys_clk_gate[] = { + UNIPHIER_CLK_GATE(8, 0x2104, 10), /* stdmac */ + UNIPHIER_CLK_GATE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ + UNIPHIER_CLK_GATE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ + UNIPHIER_CLK_GATE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ + UNIPHIER_CLK_GATE(16, 0x2104, 19), /* usb30-phy (PXs2) */ + UNIPHIER_CLK_GATE(20, 0x2104, 20), /* usb31-phy (PXs2) */ + UNIPHIER_CLK_END +}; + +const struct uniphier_clk_data uniphier_pxs2_sys_clk_data = { + .gate = uniphier_pxs2_sys_clk_gate, +}; + +const struct uniphier_clk_gate_data uniphier_ld20_sys_clk_gate[] = { + UNIPHIER_CLK_GATE(8, 0x210c, 8), /* stdmac */ + UNIPHIER_CLK_GATE(14, 0x210c, 14), /* usb30 (LD20) */ + UNIPHIER_CLK_GATE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ + UNIPHIER_CLK_GATE(17, 0x210c, 13), /* usb30-phy1 (LD20) */ + UNIPHIER_CLK_END +}; + +const struct uniphier_clk_data uniphier_ld20_sys_clk_data = { + .gate = uniphier_ld20_sys_clk_gate, +}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index f9a560ee73..770a3225e1 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -50,6 +50,8 @@ struct uniphier_clk_data { .rates = {(_reg),}, \ } +extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data; +extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data; extern const struct uniphier_clk_data uniphier_mio_clk_data; #endif /* __CLK_UNIPHIER_H__ */ diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index c1a2e9f0da..0685b689d8 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -627,3 +627,15 @@ int ofnode_read_resource(ofnode node, uint index, struct resource *res) return 0; } } + +int ofnode_read_resource_byname(ofnode node, const char *name, + struct resource *res) +{ + int index; + + index = ofnode_stringlist_search(node, "reg-names", name); + if (index < 0) + return index; + + return ofnode_read_resource(node, index, res); +} diff --git a/drivers/core/read.c b/drivers/core/read.c index fe40bed64d..6acb33388f 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -164,3 +164,9 @@ int dev_read_resource(struct udevice *dev, uint index, struct resource *res) { return ofnode_read_resource(dev_ofnode(dev), index, res); } + +int dev_read_resource_byname(struct udevice *dev, const char *name, + struct resource *res) +{ + return ofnode_read_resource_byname(dev_ofnode(dev), name, res); +} diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index fd736cf3be..ea878e1822 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -6,5 +6,6 @@ obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o -obj-$(CONFIG_CMD_BLOB)$(CONFIG_CMD_DEKBLOB) += fsl_blob.o +obj-$(CONFIG_CMD_BLOB) += fsl_blob.o +obj-$(CONFIG_CMD_DEKBLOB) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 720e82d5de..c296985d9b 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -174,6 +174,26 @@ config SYS_I2C_S3C24X0 help Support for Samsung I2C controller as Samsung SoCs. +config SYS_I2C_STM32F7 + bool "STMicroelectronics STM32F7 I2C support" + depends on (STM32F7 || STM32H7) && DM_I2C + help + Enable this option to add support for STM32 I2C controller + introduced with STM32F7/H7 SoCs. This I2C controller supports : + _ Slave and master modes + _ Multimaster capability + _ Standard-mode (up to 100 kHz) + _ Fast-mode (up to 400 kHz) + _ Fast-mode Plus (up to 1 MHz) + _ 7-bit and 10-bit addressing mode + _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) + _ All 7-bit addresses acknowledge mode + _ General call + _ Programmable setup and hold times + _ Easy to use event management + _ Optional clock stretching + _ Software reset + config SYS_I2C_UNIPHIER bool "UniPhier I2C driver" depends on ARCH_UNIPHIER && DM_I2C @@ -207,6 +227,16 @@ config TEGRA186_BPMP_I2C by the BPMP, and can only be accessed by the main CPU via IPC requests to the BPMP. This driver covers the latter case. +config SYS_I2C_BUS_MAX + int "Max I2C busses" + depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA + default 2 if TI816X + default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE + default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X + default 5 if OMAP54XX + help + Define the maximum number of available I2C buses. + source "drivers/i2c/muxes/Kconfig" endmenu diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 4f754191e2..e7ade94d91 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o +obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index 2df07bbe8c..a35ec467c6 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -343,11 +343,11 @@ static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip) static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { -#if I2C_BUS_MAX >= 3 +#if CONFIG_SYS_I2C_BUS_MAX >= 3 case 2: return (struct i2c_regs *)I2C2_BASE; #endif -#if I2C_BUS_MAX >= 2 +#if CONFIG_SYS_I2C_BUS_MAX >= 2 case 1: return (struct i2c_regs *)I2C1_BASE; #endif @@ -412,7 +412,7 @@ U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip, CONFIG_SYS_DAVINCI_I2C_SLAVE, 0) -#if I2C_BUS_MAX >= 2 +#if CONFIG_SYS_I2C_BUS_MAX >= 2 U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip, davinci_i2c_read, davinci_i2c_write, davinci_i2c_setspeed, @@ -421,7 +421,7 @@ U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip, 1) #endif -#if I2C_BUS_MAX >= 3 +#if CONFIG_SYS_I2C_BUS_MAX >= 3 U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip, davinci_i2c_read, davinci_i2c_write, davinci_i2c_setspeed, diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index 48900ed2af..156380c1cc 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -34,3 +34,12 @@ config I2C_MUX_PCA954x paritioning I2C bus and connect multiple devices with the same address to the same I2C controller where driver handles proper routing to target i2c device. PCA9544 and PCA9548 are supported. + +config I2C_MUX_GPIO + tristate "GPIO-based I2C multiplexer" + depends on I2C_MUX && DM_GPIO + help + If you say yes to this option, support will be included for + a GPIO based I2C multiplexer. This driver provides access to + I2C busses connected through a MUX, which is controlled + through GPIO pins. diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile index 0811add421..3831f4e4fb 100644 --- a/drivers/i2c/muxes/Makefile +++ b/drivers/i2c/muxes/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o +obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c new file mode 100644 index 0000000000..0269b3a18e --- /dev/null +++ b/drivers/i2c/muxes/i2c-mux-gpio.c @@ -0,0 +1,138 @@ +/* + * I2C multiplexer using GPIO API + * + * Copyright 2017 NXP + * + * Peng Fan <peng.fan@nxp.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <fdtdec.h> +#include <i2c.h> +#include <linux/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * struct i2c_mux_gpio_priv - private data for i2c mux gpio + * + * @values: the reg value of each child node + * @n_values: num of regs + * @gpios: the mux-gpios array + * @n_gpios: num of gpios in mux-gpios + * @idle: the value of idle-state + */ +struct i2c_mux_gpio_priv { + u32 *values; + int n_values; + struct gpio_desc *gpios; + int n_gpios; + u32 idle; +}; + + +static int i2c_mux_gpio_select(struct udevice *dev, struct udevice *bus, + uint channel) +{ + struct i2c_mux_gpio_priv *priv = dev_get_priv(dev); + int i, ret; + + for (i = 0; i < priv->n_gpios; i++) { + ret = dm_gpio_set_value(&priv->gpios[i], (channel >> i) & 1); + if (ret) + return ret; + } + + return 0; +} + +static int i2c_mux_gpio_deselect(struct udevice *dev, struct udevice *bus, + uint channel) +{ + struct i2c_mux_gpio_priv *priv = dev_get_priv(dev); + int i, ret; + + for (i = 0; i < priv->n_gpios; i++) { + ret = dm_gpio_set_value(&priv->gpios[i], (priv->idle >> i) & 1); + if (ret) + return ret; + } + + return 0; +} + +static int i2c_mux_gpio_probe(struct udevice *dev) +{ + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(dev); + struct i2c_mux_gpio_priv *mux = dev_get_priv(dev); + struct gpio_desc *gpios; + u32 *values; + int i = 0, subnode, ret; + + mux->n_values = fdtdec_get_child_count(fdt, node); + values = devm_kzalloc(dev, sizeof(*mux->values) * mux->n_values, + GFP_KERNEL); + if (!values) { + dev_err(dev, "Cannot alloc values array"); + return -ENOMEM; + } + + fdt_for_each_subnode(subnode, fdt, node) { + *(values + i) = fdtdec_get_uint(fdt, subnode, "reg", -1); + i++; + } + + mux->values = values; + + mux->idle = fdtdec_get_uint(fdt, node, "idle-state", -1); + + mux->n_gpios = gpio_get_list_count(dev, "mux-gpios"); + if (mux->n_gpios < 0) { + dev_err(dev, "Missing mux-gpios property\n"); + return -EINVAL; + } + + gpios = devm_kzalloc(dev, sizeof(struct gpio_desc) * mux->n_gpios, + GFP_KERNEL); + if (!gpios) { + dev_err(dev, "Cannot allocate gpios array\n"); + return -ENOMEM; + } + + ret = gpio_request_list_by_name(dev, "mux-gpios", gpios, mux->n_gpios, + GPIOD_IS_OUT_ACTIVE); + if (ret <= 0) { + dev_err(dev, "Failed to request mux-gpios\n"); + return ret; + } + + mux->gpios = gpios; + + return 0; +} + +static const struct i2c_mux_ops i2c_mux_gpio_ops = { + .select = i2c_mux_gpio_select, + .deselect = i2c_mux_gpio_deselect, +}; + +static const struct udevice_id i2c_mux_gpio_ids[] = { + { .compatible = "i2c-mux-gpio", }, + {} +}; + +U_BOOT_DRIVER(i2c_mux_gpio) = { + .name = "i2c_mux_gpio", + .id = UCLASS_I2C_MUX, + .of_match = i2c_mux_gpio_ids, + .ops = &i2c_mux_gpio_ops, + .probe = i2c_mux_gpio_probe, + .priv_auto_alloc_size = sizeof(struct i2c_mux_gpio_priv), +}; diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index f71e0a5a26..c98c6276dd 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -706,15 +706,15 @@ static struct i2c *omap24_get_base(struct i2c_adapter *adap) case 1: return (struct i2c *)I2C_BASE2; break; -#if (I2C_BUS_MAX > 2) +#if (CONFIG_SYS_I2C_BUS_MAX > 2) case 2: return (struct i2c *)I2C_BASE3; break; -#if (I2C_BUS_MAX > 3) +#if (CONFIG_SYS_I2C_BUS_MAX > 3) case 3: return (struct i2c *)I2C_BASE4; break; -#if (I2C_BUS_MAX > 4) +#if (CONFIG_SYS_I2C_BUS_MAX > 4) case 4: return (struct i2c *)I2C_BASE5; break; @@ -795,7 +795,7 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, CONFIG_SYS_OMAP24_I2C_SPEED1, CONFIG_SYS_OMAP24_I2C_SLAVE1, 1) -#if (I2C_BUS_MAX > 2) +#if (CONFIG_SYS_I2C_BUS_MAX > 2) #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED #endif @@ -808,7 +808,7 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, CONFIG_SYS_OMAP24_I2C_SPEED2, CONFIG_SYS_OMAP24_I2C_SLAVE2, 2) -#if (I2C_BUS_MAX > 3) +#if (CONFIG_SYS_I2C_BUS_MAX > 3) #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED #endif @@ -821,7 +821,7 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, CONFIG_SYS_OMAP24_I2C_SPEED3, CONFIG_SYS_OMAP24_I2C_SLAVE3, 3) -#if (I2C_BUS_MAX > 4) +#if (CONFIG_SYS_I2C_BUS_MAX > 4) #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED #endif diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c new file mode 100644 index 0000000000..bf5fefab7b --- /dev/null +++ b/drivers/i2c/stm32f7_i2c.c @@ -0,0 +1,882 @@ +/* + * (C) Copyright 2017 STMicroelectronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <i2c.h> +#include <reset.h> + +#include <dm/device.h> +#include <linux/io.h> + +/* STM32 I2C registers */ +struct stm32_i2c_regs { + u32 cr1; /* I2C control register 1 */ + u32 cr2; /* I2C control register 2 */ + u32 oar1; /* I2C own address 1 register */ + u32 oar2; /* I2C own address 2 register */ + u32 timingr; /* I2C timing register */ + u32 timeoutr; /* I2C timeout register */ + u32 isr; /* I2C interrupt and status register */ + u32 icr; /* I2C interrupt clear register */ + u32 pecr; /* I2C packet error checking register */ + u32 rxdr; /* I2C receive data register */ + u32 txdr; /* I2C transmit data register */ +}; + +#define STM32_I2C_CR1 0x00 +#define STM32_I2C_CR2 0x04 +#define STM32_I2C_TIMINGR 0x10 +#define STM32_I2C_ISR 0x18 +#define STM32_I2C_ICR 0x1C +#define STM32_I2C_RXDR 0x24 +#define STM32_I2C_TXDR 0x28 + +/* STM32 I2C control 1 */ +#define STM32_I2C_CR1_ANFOFF BIT(12) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_TCIE BIT(6) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_PE BIT(0) + +/* STM32 I2C control 2 */ +#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16) +#define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_HEAD10R BIT(12) +#define STM32_I2C_CR2_ADD10 BIT(11) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0) +#define STM32_I2C_CR2_SADD10(n) ((n & STM32_I2C_CR2_SADD10_MASK)) +#define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1) +#define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1) +#define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \ + | STM32_I2C_CR2_NBYTES_MASK \ + | STM32_I2C_CR2_SADD7_MASK \ + | STM32_I2C_CR2_RELOAD \ + | STM32_I2C_CR2_RD_WRN) + +/* STM32 I2C Interrupt Status */ +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_STOPF BIT(5) +#define STM32_I2C_ISR_NACKF BIT(4) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \ + | STM32_I2C_ISR_ARLO) + +/* STM32 I2C Interrupt Clear */ +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_NACKCF BIT(4) + +/* STM32 I2C Timing */ +#define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28) +#define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20) +#define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16) +#define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8) +#define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff) + +#define STM32_I2C_MAX_LEN 0xff + +#define STM32_I2C_DNF_DEFAULT 0 +#define STM32_I2C_DNF_MAX 16 + +#define STM32_I2C_ANALOG_FILTER_ENABLE 1 +#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ +#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ + +#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ +#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ + +#define STM32_PRESC_MAX BIT(4) +#define STM32_SCLDEL_MAX BIT(4) +#define STM32_SDADEL_MAX BIT(4) +#define STM32_SCLH_MAX BIT(8) +#define STM32_SCLL_MAX BIT(8) + +#define STM32_NSEC_PER_SEC 1000000000L + +#define STANDARD_RATE 100000 +#define FAST_RATE 400000 +#define FAST_PLUS_RATE 1000000 + +enum stm32_i2c_speed { + STM32_I2C_SPEED_STANDARD, /* 100 kHz */ + STM32_I2C_SPEED_FAST, /* 400 kHz */ + STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */ + STM32_I2C_SPEED_END, +}; + +/** + * struct stm32_i2c_spec - private i2c specification timing + * @rate: I2C bus speed (Hz) + * @rate_min: 80% of I2C bus speed (Hz) + * @rate_max: 120% of I2C bus speed (Hz) + * @fall_max: Max fall time of both SDA and SCL signals (ns) + * @rise_max: Max rise time of both SDA and SCL signals (ns) + * @hddat_min: Min data hold time (ns) + * @vddat_max: Max data valid time (ns) + * @sudat_min: Min data setup time (ns) + * @l_min: Min low period of the SCL clock (ns) + * @h_min: Min high period of the SCL clock (ns) + */ + +struct stm32_i2c_spec { + u32 rate; + u32 rate_min; + u32 rate_max; + u32 fall_max; + u32 rise_max; + u32 hddat_min; + u32 vddat_max; + u32 sudat_min; + u32 l_min; + u32 h_min; +}; + +/** + * struct stm32_i2c_setup - private I2C timing setup parameters + * @speed: I2C speed mode (standard, Fast Plus) + * @speed_freq: I2C speed frequency (Hz) + * @clock_src: I2C clock source frequency (Hz) + * @rise_time: Rise time (ns) + * @fall_time: Fall time (ns) + * @dnf: Digital filter coefficient (0-16) + * @analog_filter: Analog filter delay (On/Off) + */ +struct stm32_i2c_setup { + enum stm32_i2c_speed speed; + u32 speed_freq; + u32 clock_src; + u32 rise_time; + u32 fall_time; + u8 dnf; + bool analog_filter; +}; + +/** + * struct stm32_i2c_timings - private I2C output parameters + * @prec: Prescaler value + * @scldel: Data setup time + * @sdadel: Data hold time + * @sclh: SCL high period (master mode) + * @sclh: SCL low period (master mode) + */ +struct stm32_i2c_timings { + struct list_head node; + u8 presc; + u8 scldel; + u8 sdadel; + u8 sclh; + u8 scll; +}; + +struct stm32_i2c_priv { + struct stm32_i2c_regs *regs; + struct clk clk; + struct stm32_i2c_setup *setup; + int speed; +}; + +static struct stm32_i2c_spec i2c_specs[] = { + [STM32_I2C_SPEED_STANDARD] = { + .rate = STANDARD_RATE, + .rate_min = 8000, + .rate_max = 120000, + .fall_max = 300, + .rise_max = 1000, + .hddat_min = 0, + .vddat_max = 3450, + .sudat_min = 250, + .l_min = 4700, + .h_min = 4000, + }, + [STM32_I2C_SPEED_FAST] = { + .rate = FAST_RATE, + .rate_min = 320000, + .rate_max = 480000, + .fall_max = 300, + .rise_max = 300, + .hddat_min = 0, + .vddat_max = 900, + .sudat_min = 100, + .l_min = 1300, + .h_min = 600, + }, + [STM32_I2C_SPEED_FAST_PLUS] = { + .rate = FAST_PLUS_RATE, + .rate_min = 800000, + .rate_max = 1200000, + .fall_max = 100, + .rise_max = 120, + .hddat_min = 0, + .vddat_max = 450, + .sudat_min = 50, + .l_min = 500, + .h_min = 260, + }, +}; + +static struct stm32_i2c_setup stm32f7_setup = { + .rise_time = STM32_I2C_RISE_TIME_DEFAULT, + .fall_time = STM32_I2C_FALL_TIME_DEFAULT, + .dnf = STM32_I2C_DNF_DEFAULT, + .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE, +}; + +DECLARE_GLOBAL_DATA_PTR; + +static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 status = readl(®s->isr); + + if (status & STM32_I2C_ISR_BUSY) + return -EBUSY; + + return 0; +} + +static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv, + struct i2c_msg *msg, bool stop) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 cr2 = readl(®s->cr2); + + /* Set transfer direction */ + cr2 &= ~STM32_I2C_CR2_RD_WRN; + if (msg->flags & I2C_M_RD) + cr2 |= STM32_I2C_CR2_RD_WRN; + + /* Set slave address */ + cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10); + if (msg->flags & I2C_M_TEN) { + cr2 &= ~STM32_I2C_CR2_SADD10_MASK; + cr2 |= STM32_I2C_CR2_SADD10(msg->addr); + cr2 |= STM32_I2C_CR2_ADD10; + } else { + cr2 &= ~STM32_I2C_CR2_SADD7_MASK; + cr2 |= STM32_I2C_CR2_SADD7(msg->addr); + } + + /* Set nb bytes to transfer and reload or autoend bits */ + cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD | + STM32_I2C_CR2_AUTOEND); + if (msg->len > STM32_I2C_MAX_LEN) { + cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); + cr2 |= STM32_I2C_CR2_RELOAD; + } else { + cr2 |= STM32_I2C_CR2_NBYTES(msg->len); + } + + /* Write configurations register */ + writel(cr2, ®s->cr2); + + /* START/ReSTART generation */ + setbits_le32(®s->cr2, STM32_I2C_CR2_START); +} + +/* + * RELOAD mode must be selected if total number of data bytes to be + * sent is greater than MAX_LEN + */ + +static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv, + struct i2c_msg *msg, bool stop) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 cr2 = readl(®s->cr2); + + cr2 &= ~STM32_I2C_CR2_NBYTES_MASK; + + if (msg->len > STM32_I2C_MAX_LEN) { + cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); + } else { + cr2 &= ~STM32_I2C_CR2_RELOAD; + cr2 |= STM32_I2C_CR2_NBYTES(msg->len); + } + + writel(cr2, ®s->cr2); +} + +static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv, + u32 flags, u32 *status) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 time_start = get_timer(0); + + *status = readl(®s->isr); + while (!(*status & flags)) { + if (get_timer(time_start) > CONFIG_SYS_HZ) { + debug("%s: i2c timeout\n", __func__); + return -ETIMEDOUT; + } + + *status = readl(®s->isr); + } + + return 0; +} + +static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF | + STM32_I2C_ISR_STOPF; + u32 status; + int ret; + + ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); + if (ret) + return ret; + + if (status & STM32_I2C_ISR_BERR) { + debug("%s: Bus error\n", __func__); + + /* Clear BERR flag */ + setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF); + + return -EIO; + } + + if (status & STM32_I2C_ISR_ARLO) { + debug("%s: Arbitration lost\n", __func__); + + /* Clear ARLO flag */ + setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF); + + return -EAGAIN; + } + + if (status & STM32_I2C_ISR_NACKF) { + debug("%s: Receive NACK\n", __func__); + + /* Clear NACK flag */ + setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF); + + /* Wait until STOPF flag is set */ + mask = STM32_I2C_ISR_STOPF; + ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); + if (ret) + return ret; + + ret = -EIO; + } + + if (status & STM32_I2C_ISR_STOPF) { + /* Clear STOP flag */ + setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF); + + /* Clear control register 2 */ + setbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK); + } + + return ret; +} + +static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv, + struct i2c_msg *msg, bool stop) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 status; + u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : + STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; + int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ? + STM32_I2C_MAX_LEN : msg->len; + int ret = 0; + + /* Add errors */ + mask |= STM32_I2C_ISR_ERRORS; + + stm32_i2c_message_start(i2c_priv, msg, stop); + + while (msg->len) { + /* + * Wait until TXIS/NACKF/BERR/ARLO flags or + * RXNE/BERR/ARLO flags are set + */ + ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); + if (ret) + break; + + if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS)) + break; + + if (status & STM32_I2C_ISR_RXNE) { + *msg->buf++ = readb(®s->rxdr); + msg->len--; + bytes_to_rw--; + } + + if (status & STM32_I2C_ISR_TXIS) { + writeb(*msg->buf++, ®s->txdr); + msg->len--; + bytes_to_rw--; + } + + if (!bytes_to_rw && msg->len) { + /* Wait until TCR flag is set */ + mask = STM32_I2C_ISR_TCR; + ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); + if (ret) + break; + + bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ? + STM32_I2C_MAX_LEN : msg->len; + mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : + STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; + + stm32_i2c_handle_reload(i2c_priv, msg, stop); + } else if (!bytes_to_rw) { + /* Wait until TC flag is set */ + mask = STM32_I2C_ISR_TC; + ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); + if (ret) + break; + + if (!stop) + /* Message sent, new message has to be sent */ + return 0; + } + } + + /* End of transfer, send stop condition */ + mask = STM32_I2C_CR2_STOP; + setbits_le32(®s->cr2, mask); + + return stm32_i2c_check_end_of_message(i2c_priv); +} + +static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) +{ + struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); + int ret; + + ret = stm32_i2c_check_device_busy(i2c_priv); + if (ret) + return ret; + + for (; nmsgs > 0; nmsgs--, msg++) { + ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1); + if (ret) + return ret; + } + + return 0; +} + +static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, + struct list_head *solutions) +{ + struct stm32_i2c_timings *v; + u32 p_prev = STM32_PRESC_MAX; + u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, + setup->clock_src); + u32 af_delay_min, af_delay_max; + u16 p, l, a; + int sdadel_min, sdadel_max, scldel_min; + int ret = 0; + + af_delay_min = setup->analog_filter ? + STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0; + af_delay_max = setup->analog_filter ? + STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0; + + sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min - + af_delay_min - (setup->dnf + 3) * i2cclk; + + sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time - + af_delay_max - (setup->dnf + 4) * i2cclk; + + scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min; + + if (sdadel_min < 0) + sdadel_min = 0; + if (sdadel_max < 0) + sdadel_max = 0; + + debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__, + sdadel_min, sdadel_max, scldel_min); + + /* Compute possible values for PRESC, SCLDEL and SDADEL */ + for (p = 0; p < STM32_PRESC_MAX; p++) { + for (l = 0; l < STM32_SCLDEL_MAX; l++) { + u32 scldel = (l + 1) * (p + 1) * i2cclk; + + if (scldel < scldel_min) + continue; + + for (a = 0; a < STM32_SDADEL_MAX; a++) { + u32 sdadel = (a * (p + 1) + 1) * i2cclk; + + if (((sdadel >= sdadel_min) && + (sdadel <= sdadel_max)) && + (p != p_prev)) { + v = kmalloc(sizeof(*v), GFP_KERNEL); + if (!v) + return -ENOMEM; + + v->presc = p; + v->scldel = l; + v->sdadel = a; + p_prev = p; + + list_add_tail(&v->node, solutions); + } + } + } + } + + if (list_empty(solutions)) { + error("%s: no Prescaler solution\n", __func__); + ret = -EPERM; + } + + return ret; +} + +static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, + struct list_head *solutions, + struct stm32_i2c_timings *s) +{ + struct stm32_i2c_timings *v; + u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, + setup->speed_freq); + u32 clk_error_prev = i2cbus; + u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, + setup->clock_src); + u32 clk_min, clk_max; + u32 af_delay_min; + u32 dnf_delay; + u32 tsync; + u16 l, h; + int ret = 0; + + af_delay_min = setup->analog_filter ? + STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0; + dnf_delay = setup->dnf * i2cclk; + + tsync = af_delay_min + dnf_delay + (2 * i2cclk); + clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min; + clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max; + + /* + * Among Prescaler possibilities discovered above figures out SCL Low + * and High Period. Provided: + * - SCL Low Period has to be higher than Low Period of the SCL Clock + * defined by I2C Specification. I2C Clock has to be lower than + * (SCL Low Period - Analog/Digital filters) / 4. + * - SCL High Period has to be lower than High Period of the SCL Clock + * defined by I2C Specification + * - I2C Clock has to be lower than SCL High Period + */ + list_for_each_entry(v, solutions, node) { + u32 prescaler = (v->presc + 1) * i2cclk; + + for (l = 0; l < STM32_SCLL_MAX; l++) { + u32 tscl_l = (l + 1) * prescaler + tsync; + if ((tscl_l < i2c_specs[setup->speed].l_min) || + (i2cclk >= + ((tscl_l - af_delay_min - dnf_delay) / 4))) { + continue; + } + + for (h = 0; h < STM32_SCLH_MAX; h++) { + u32 tscl_h = (h + 1) * prescaler + tsync; + u32 tscl = tscl_l + tscl_h + + setup->rise_time + setup->fall_time; + + if ((tscl >= clk_min) && (tscl <= clk_max) && + (tscl_h >= i2c_specs[setup->speed].h_min) && + (i2cclk < tscl_h)) { + int clk_error = tscl - i2cbus; + + if (clk_error < 0) + clk_error = -clk_error; + + if (clk_error < clk_error_prev) { + clk_error_prev = clk_error; + v->scll = l; + v->sclh = h; + s = v; + } + } + } + } + } + + if (!s) { + error("%s: no solution at all\n", __func__); + ret = -EPERM; + } + + return ret; +} + +static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, + struct stm32_i2c_setup *setup, + struct stm32_i2c_timings *output) +{ + struct stm32_i2c_timings *v, *_v, *s; + struct list_head solutions; + int ret; + + if (setup->speed >= STM32_I2C_SPEED_END) { + error("%s: speed out of bound {%d/%d}\n", __func__, + setup->speed, STM32_I2C_SPEED_END - 1); + return -EINVAL; + } + + if ((setup->rise_time > i2c_specs[setup->speed].rise_max) || + (setup->fall_time > i2c_specs[setup->speed].fall_max)) { + error("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", + __func__, + setup->rise_time, i2c_specs[setup->speed].rise_max, + setup->fall_time, i2c_specs[setup->speed].fall_max); + return -EINVAL; + } + + if (setup->dnf > STM32_I2C_DNF_MAX) { + error("%s: DNF out of bound %d/%d\n", __func__, + setup->dnf, STM32_I2C_DNF_MAX); + return -EINVAL; + } + + if (setup->speed_freq > i2c_specs[setup->speed].rate) { + error("%s: Freq {%d/%d}\n", __func__, + setup->speed_freq, i2c_specs[setup->speed].rate); + return -EINVAL; + } + + s = NULL; + INIT_LIST_HEAD(&solutions); + ret = stm32_i2c_compute_solutions(setup, &solutions); + if (ret) + goto exit; + + ret = stm32_i2c_choose_solution(setup, &solutions, s); + if (ret) + goto exit; + + output->presc = s->presc; + output->scldel = s->scldel; + output->sdadel = s->sdadel; + output->scll = s->scll; + output->sclh = s->sclh; + + debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", + __func__, output->presc, + output->scldel, output->sdadel, + output->scll, output->sclh); + +exit: + /* Release list and memory */ + list_for_each_entry_safe(v, _v, &solutions, node) { + list_del(&v->node); + kfree(v); + } + + return ret; +} + +static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, + struct stm32_i2c_timings *timing) +{ + struct stm32_i2c_setup *setup = i2c_priv->setup; + int ret = 0; + + setup->speed = i2c_priv->speed; + setup->speed_freq = i2c_specs[setup->speed].rate; + setup->clock_src = clk_get_rate(&i2c_priv->clk); + + if (!setup->clock_src) { + error("%s: clock rate is 0\n", __func__); + return -EINVAL; + } + + do { + ret = stm32_i2c_compute_timing(i2c_priv, setup, timing); + if (ret) { + debug("%s: failed to compute I2C timings.\n", + __func__); + if (i2c_priv->speed > STM32_I2C_SPEED_STANDARD) { + i2c_priv->speed--; + setup->speed = i2c_priv->speed; + setup->speed_freq = + i2c_specs[setup->speed].rate; + debug("%s: downgrade I2C Speed Freq to (%i)\n", + __func__, i2c_specs[setup->speed].rate); + } else { + break; + } + } + } while (ret); + + if (ret) { + error("%s: impossible to compute I2C timings.\n", __func__); + return ret; + } + + debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__, + setup->speed, setup->speed_freq, setup->clock_src); + debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__, + setup->rise_time, setup->fall_time); + debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__, + setup->analog_filter ? "On" : "Off", setup->dnf); + + return 0; +} + +static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + struct stm32_i2c_timings t; + int ret; + u32 timing = 0; + + ret = stm32_i2c_setup_timing(i2c_priv, &t); + if (ret) + return ret; + + /* Disable I2C */ + clrbits_le32(®s->cr1, STM32_I2C_CR1_PE); + + /* Timing settings */ + timing |= STM32_I2C_TIMINGR_PRESC(t.presc); + timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel); + timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel); + timing |= STM32_I2C_TIMINGR_SCLH(t.sclh); + timing |= STM32_I2C_TIMINGR_SCLL(t.scll); + writel(timing, ®s->timingr); + + /* Enable I2C */ + if (i2c_priv->setup->analog_filter) + clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); + else + setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); + setbits_le32(®s->cr1, STM32_I2C_CR1_PE); + + return 0; +} + +static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); + + switch (speed) { + case STANDARD_RATE: + i2c_priv->speed = STM32_I2C_SPEED_STANDARD; + break; + case FAST_RATE: + i2c_priv->speed = STM32_I2C_SPEED_FAST; + break; + case FAST_PLUS_RATE: + i2c_priv->speed = STM32_I2C_SPEED_FAST_PLUS; + break; + default: + debug("%s: Speed %d not supported\n", __func__, speed); + return -EINVAL; + } + + return stm32_i2c_hw_config(i2c_priv); +} + +static int stm32_i2c_probe(struct udevice *dev) +{ + struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); + struct reset_ctl reset_ctl; + fdt_addr_t addr; + int ret; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + i2c_priv->regs = (struct stm32_i2c_regs *)addr; + + ret = clk_get_by_index(dev, 0, &i2c_priv->clk); + if (ret) + return ret; + + ret = clk_enable(&i2c_priv->clk); + if (ret) + goto clk_free; + + ret = reset_get_by_index(dev, 0, &reset_ctl); + if (ret) + goto clk_disable; + + reset_assert(&reset_ctl); + udelay(2); + reset_deassert(&reset_ctl); + + return 0; + +clk_disable: + clk_disable(&i2c_priv->clk); +clk_free: + clk_free(&i2c_priv->clk); + + return ret; +} + +static int stm32_ofdata_to_platdata(struct udevice *dev) +{ + struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); + u32 rise_time, fall_time; + + i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev); + if (!i2c_priv->setup) + return -EINVAL; + + rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0); + if (rise_time) + i2c_priv->setup->rise_time = rise_time; + + fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0); + if (fall_time) + i2c_priv->setup->fall_time = fall_time; + + return 0; +} + +static const struct dm_i2c_ops stm32_i2c_ops = { + .xfer = stm32_i2c_xfer, + .set_bus_speed = stm32_i2c_set_bus_speed, +}; + +static const struct udevice_id stm32_i2c_of_match[] = { + { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup }, + {} +}; + +U_BOOT_DRIVER(stm32f7_i2c) = { + .name = "stm32f7-i2c", + .id = UCLASS_I2C, + .of_match = stm32_i2c_of_match, + .ofdata_to_platdata = stm32_ofdata_to_platdata, + .probe = stm32_i2c_probe, + .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv), + .ops = &stm32_i2c_ops, +}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index d1ddbbe157..3d282d5b14 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -196,4 +196,49 @@ config I2C_EEPROM depends on MISC help Enable a generic driver for EEPROMs attached via I2C. + +if I2C_EEPROM + +config SYS_I2C_EEPROM_ADDR + hex "Chip address of the EEPROM device" + default 0 + +config SYS_I2C_EEPROM_BUS + int "I2C bus of the EEPROM device." + default 0 + +config SYS_EEPROM_SIZE + int "Size in bytes of the EEPROM device" + default 256 + +config SYS_EEPROM_PAGE_WRITE_BITS + int "Number of bits used to address bytes in a single page" + default 0 + help + The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. + A 64 byte page, for example would require six bits. + +config SYS_EEPROM_PAGE_WRITE_DELAY_MS + int "Number of milliseconds to delay between page writes" + default 0 + +config SYS_I2C_EEPROM_ADDR_LEN + int "Length in bytes of the EEPROM memory array address" + default 1 + help + Note: This is NOT the chip address length! + +config SYS_I2C_EEPROM_ADDR_OVERFLOW + hex "EEPROM Address Overflow" + default 0 + help + EEPROM chips that implement "address overflow" are ones + like Catalyst 24WC04/08/16 which has 9/10/11 bits of + address and the extra bits end up in the "chip address" bit + slots. This makes a 24WC08 (1Kbyte) chip look like four 256 + byte chips. + +endif + + endmenu diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 56c352e72a..6de927b8c6 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -369,6 +369,10 @@ config MMC_SUNXI This selects support for the SD/MMC Host Controller on Allwinner sunxi SoCs. +config MMC_SUNXI_HAS_NEW_MODE + bool + depends on MMC_SUNXI + config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" depends on DM_MMC && BLK && ARCH_AT91 diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 588574fab6..4edb4be46c 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -96,6 +96,18 @@ static int mmc_resource_init(int sdc_no) static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) { unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; + bool new_mode = false; + u32 val = 0; + + if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2)) + new_mode = true; + + /* + * The MMC clock has an extra /2 post-divider when operating in the new + * mode. + */ + if (new_mode) + hz = hz * 2; if (hz <= 24000000) { pll = CCM_MMC_CTRL_OSCM24; @@ -152,9 +164,18 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) #endif } - writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | - CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | - CCM_MMC_CTRL_M(div), priv->mclkreg); + if (new_mode) { +#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE + val = CCM_MMC_CTRL_MODE_SEL_NEW; + setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); +#endif + } else { + val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | + CCM_MMC_CTRL_SCLK_DLY(sclk_dly); + } + + writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) | + CCM_MMC_CTRL_M(div) | val, priv->mclkreg); debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div); @@ -498,7 +519,7 @@ struct mmc *sunxi_mmc_init(int sdc_no) if (ret) return NULL; - return mmc_create(cfg, mmc_host); + return mmc_create(cfg, priv); } #else diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 42bc2efd90..f3bb72788a 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -178,7 +178,7 @@ __maybe_weak u64 flash_read64(void *addr) /*----------------------------------------------------------------------- */ #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) -flash_info_t *flash_get_info(ulong base) +static flash_info_t *flash_get_info(ulong base) { int i; flash_info_t *info; @@ -355,8 +355,8 @@ static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, /* * Write a proper sized command to the correct address */ -void flash_write_cmd (flash_info_t * info, flash_sect_t sect, - uint offset, u32 cmd) +static void flash_write_cmd(flash_info_t *info, flash_sect_t sect, + uint offset, u32 cmd) { void *addr; @@ -2298,7 +2298,7 @@ static void cfi_flash_set_config_reg(u32 base, u16 val) /*----------------------------------------------------------------------- */ -void flash_protect_default(void) +static void flash_protect_default(void) { #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) int i; diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 71d678fc66..85b26d6088 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -16,6 +16,13 @@ config NAND_DENALI help Enable support for the Denali NAND controller. +config NAND_DENALI_DT + bool "Support Denali NAND controller as a DT device" + depends on NAND_DENALI && OF_CONTROL && DM + help + Enable the driver for NAND flash on platforms using a Denali NAND + controller as a DT device. + config SYS_NAND_DENALI_64BIT bool "Use 64-bit variant of Denali NAND controller" depends on NAND_DENALI diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index c3d4a996f3..9f7d9d6ff7 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o obj-$(CONFIG_NAND_DENALI) += denali.o +obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 18280b0b2f..47cf37d1d9 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1175,7 +1175,7 @@ static void denali_hw_init(struct denali_nand_info *denali) static struct nand_ecclayout nand_oob; -static int denali_init(struct denali_nand_info *denali) +int denali_init(struct denali_nand_info *denali) { struct mtd_info *mtd = nand_to_mtd(&denali->nand); int ret; @@ -1273,6 +1273,7 @@ fail: return ret; } +#ifndef CONFIG_NAND_DENALI_DT static int __board_nand_init(void) { struct denali_nand_info *denali; @@ -1296,3 +1297,4 @@ void board_nand_init(void) if (__board_nand_init() < 0) pr_warn("Failed to initialize Denali NAND controller.\n"); } +#endif diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 0e098bddf1..694bce53a9 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -464,4 +464,6 @@ struct denali_nand_info { uint32_t max_banks; }; +int denali_init(struct denali_nand_info *denali); + #endif /* __DENALI_H__ */ diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c new file mode 100644 index 0000000000..0a6155c748 --- /dev/null +++ b/drivers/mtd/nand/denali_dt.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <linux/io.h> +#include <linux/ioport.h> + +#include "denali.h" + +static const struct udevice_id denali_nand_dt_ids[] = { + { + .compatible = "altr,socfpga-denali-nand", + }, + { + .compatible = "socionext,uniphier-denali-nand-v5a", + }, + { + .compatible = "socionext,uniphier-denali-nand-v5b", + }, + { /* sentinel */ } +}; + +static int denali_dt_probe(struct udevice *dev) +{ + struct denali_nand_info *denali = dev_get_priv(dev); + struct resource res; + int ret; + + ret = dev_read_resource_byname(dev, "denali_reg", &res); + if (ret) + return ret; + + denali->flash_reg = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "nand_data", &res); + if (ret) + return ret; + + denali->flash_mem = devm_ioremap(dev, res.start, resource_size(&res)); + + return denali_init(denali); +} + +U_BOOT_DRIVER(denali_nand_dt) = { + .name = "denali-nand-dt", + .id = UCLASS_MISC, + .of_match = denali_nand_dt_ids, + .probe = denali_dt_probe, + .priv_auto_alloc_size = sizeof(struct denali_nand_info), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(denali_nand_dt), + &dev); + if (ret && ret != -ENODEV) + printf("Failed to initialize Denali NAND controller. (error %d)\n", + ret); +} diff --git a/drivers/nvme/nvme-uclass.c b/drivers/nvme/nvme-uclass.c index 0895bc9c24..56a6171876 100644 --- a/drivers/nvme/nvme-uclass.c +++ b/drivers/nvme/nvme-uclass.c @@ -11,43 +11,26 @@ #include <dm/device.h> #include "nvme.h" -static int nvme_info_init(struct uclass *uc) -{ - struct nvme_info *info = (struct nvme_info *)uc->priv; - - info->ns_num = 0; - info->ndev_num = 0; - INIT_LIST_HEAD(&info->dev_list); - nvme_info = info; - - return 0; -} - static int nvme_uclass_post_probe(struct udevice *udev) { char name[20]; - char *str; struct udevice *ns_udev; int i, ret; struct nvme_dev *ndev = dev_get_priv(udev); /* Create a blk device for each namespace */ for (i = 0; i < ndev->nn; i++) { - sprintf(name, "nvme-blk#%d", nvme_info->ns_num); - str = strdup(name); - if (!str) - return -ENOMEM; + /* + * Encode the namespace id to the device name so that + * we can extract it when doing the probe. + */ + sprintf(name, "blk#%d", i); /* The real blksz and size will be set by nvme_blk_probe() */ - ret = blk_create_device(udev, "nvme-blk", str, IF_TYPE_NVME, - nvme_info->ns_num++, 512, 0, &ns_udev); - if (ret) { - free(str); - nvme_info->ns_num--; - + ret = blk_create_devicef(udev, "nvme-blk", name, IF_TYPE_NVME, + -1, 512, 0, &ns_udev); + if (ret) return ret; - } - device_set_name_alloced(ns_udev); } return 0; @@ -56,7 +39,5 @@ static int nvme_uclass_post_probe(struct udevice *udev) UCLASS_DRIVER(nvme) = { .name = "nvme", .id = UCLASS_NVME, - .init = nvme_info_init, .post_probe = nvme_uclass_post_probe, - .priv_auto_alloc_size = sizeof(struct nvme_info), }; diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 151fe92479..1c3519ba74 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -13,8 +13,6 @@ #include <dm/device-internal.h> #include "nvme.h" -struct nvme_info *nvme_info; - #define NVME_Q_DEPTH 2 #define NVME_AQ_DEPTH 2 #define NVME_SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) @@ -23,6 +21,12 @@ struct nvme_info *nvme_info; #define IO_TIMEOUT 30 #define MAX_PRP_POOL 512 +enum nvme_queue_id { + NVME_ADMIN_Q, + NVME_IO_Q, + NVME_Q_NUM, +}; + /* * An NVM Express queue. Each device has at least two (one for admin * commands and one for I/O commands). @@ -47,11 +51,19 @@ struct nvme_queue { static int nvme_wait_ready(struct nvme_dev *dev, bool enabled) { u32 bit = enabled ? NVME_CSTS_RDY : 0; + int timeout; + ulong start; - while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) - udelay(10000); + /* Timeout field in the CAP register is in 500 millisecond units */ + timeout = NVME_CAP_TIMEOUT(dev->cap) * 500; - return 0; + start = get_timer(0); + while (get_timer(start) < timeout) { + if ((readl(&dev->bar->csts) & NVME_CSTS_RDY) == bit) + return 0; + } + + return -ETIME; } static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, @@ -201,7 +213,8 @@ static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, u32 *result) { - return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); + return nvme_submit_sync_cmd(dev->queues[NVME_ADMIN_Q], cmd, + result, ADMIN_TIMEOUT); } static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, @@ -318,7 +331,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) { int result; u32 aqa; - u64 cap = nvme_readq(&dev->bar->cap); + u64 cap = dev->cap; struct nvme_queue *nvmeq; /* most architectures use 4KB as the page size */ unsigned page_shift = 12; @@ -341,7 +354,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) if (result < 0) return result; - nvmeq = dev->queues[0]; + nvmeq = dev->queues[NVME_ADMIN_Q]; if (!nvmeq) { nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); if (!nvmeq) @@ -369,7 +382,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) nvmeq->cq_vector = 0; - nvme_init_queue(dev->queues[0], 0); + nvme_init_queue(dev->queues[NVME_ADMIN_Q], 0); return result; @@ -420,6 +433,7 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, u32 page_size = dev->page_size; int offset = dma_addr & (page_size - 1); int length = sizeof(struct nvme_id_ctrl); + int ret; memset(&c, 0, sizeof(c)); c.identify.opcode = nvme_admin_identify; @@ -431,12 +445,17 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, c.identify.prp2 = 0; } else { dma_addr += (page_size - offset); - c.identify.prp2 = dma_addr; + c.identify.prp2 = cpu_to_le64(dma_addr); } c.identify.cns = cpu_to_le32(cns); - return nvme_submit_admin_cmd(dev, &c, NULL); + ret = nvme_submit_admin_cmd(dev, &c, NULL); + if (!ret) + invalidate_dcache_range(dma_addr, + dma_addr + sizeof(struct nvme_id_ctrl)); + + return ret; } int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, @@ -450,6 +469,11 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, c.features.prp1 = cpu_to_le64(dma_addr); c.features.fid = cpu_to_le32(fid); + /* + * TODO: add cache invalidate operation when the size of + * the DMA buffer is known + */ + return nvme_submit_admin_cmd(dev, &c, result); } @@ -464,6 +488,11 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, c.features.fid = cpu_to_le32(fid); c.features.dword11 = cpu_to_le32(dword11); + /* + * TODO: add cache flush operation when the size of + * the DMA buffer is known + */ + return nvme_submit_admin_cmd(dev, &c, result); } @@ -533,9 +562,6 @@ static int nvme_setup_io_queues(struct nvme_dev *dev) if (result <= 0) return result; - if (result < nr_io_queues) - nr_io_queues = result; - dev->max_qid = nr_io_queues; /* Free previously allocated queues */ @@ -547,10 +573,10 @@ static int nvme_setup_io_queues(struct nvme_dev *dev) static int nvme_get_info_from_identify(struct nvme_dev *dev) { - u16 vendor, device; - struct nvme_id_ctrl buf, *ctrl = &buf; + ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ctrl)); + struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf; int ret; - int shift = NVME_CAP_MPSMIN(nvme_readq(&dev->bar->cap)) + 12; + int shift = NVME_CAP_MPSMIN(dev->cap) + 12; ret = nvme_identify(dev, 0, 1, (dma_addr_t)ctrl); if (ret) @@ -585,22 +611,6 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev) dev->max_transfer_shift = 20; } - /* Apply quirk stuff */ - dm_pci_read_config16(dev->pdev, PCI_VENDOR_ID, &vendor); - dm_pci_read_config16(dev->pdev, PCI_DEVICE_ID, &device); - if ((vendor == PCI_VENDOR_ID_INTEL) && - (device == 0x0953) && ctrl->vs[3]) { - unsigned int max_transfer_shift; - dev->stripe_size = (ctrl->vs[3] + shift); - max_transfer_shift = (ctrl->vs[3] + 18); - if (dev->max_transfer_shift) { - dev->max_transfer_shift = min(max_transfer_shift, - dev->max_transfer_shift); - } else { - dev->max_transfer_shift = max_transfer_shift; - } - } - return 0; } @@ -629,12 +639,14 @@ static int nvme_blk_probe(struct udevice *udev) struct blk_desc *desc = dev_get_uclass_platdata(udev); struct nvme_ns *ns = dev_get_priv(udev); u8 flbas; - u16 vendor; - struct nvme_id_ns buf, *id = &buf; + ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ns)); + struct nvme_id_ns *id = (struct nvme_id_ns *)buf; + struct pci_child_platdata *pplat; memset(ns, 0, sizeof(*ns)); ns->dev = ndev; - ns->ns_id = desc->devnum - ndev->blk_dev_start + 1; + /* extract the namespace id from the block device name */ + ns->ns_id = trailing_strtol(udev->name) + 1; if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)id)) return -EIO; @@ -649,8 +661,8 @@ static int nvme_blk_probe(struct udevice *udev) desc->log2blksz = ns->lba_shift; desc->blksz = 1 << ns->lba_shift; desc->bdev = udev; - dm_pci_read_config16(ndev->pdev, PCI_VENDOR_ID, &vendor); - sprintf(desc->vendor, "0x%.4x", vendor); + pplat = dev_get_parent_platdata(udev->parent); + sprintf(desc->vendor, "0x%.4x", pplat->vendor); memcpy(desc->product, ndev->serial, sizeof(ndev->serial)); memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev)); part_init(desc); @@ -658,8 +670,8 @@ static int nvme_blk_probe(struct udevice *udev) return 0; } -static ulong nvme_blk_read(struct udevice *udev, lbaint_t blknr, - lbaint_t blkcnt, void *buffer) +static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + lbaint_t blkcnt, void *buffer, bool read) { struct nvme_ns *ns = dev_get_priv(udev); struct nvme_dev *dev = ns->dev; @@ -674,7 +686,11 @@ static ulong nvme_blk_read(struct udevice *udev, lbaint_t blknr, u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift); u64 total_lbas = blkcnt; - c.rw.opcode = nvme_cmd_read; + if (!read) + flush_dcache_range((unsigned long)buffer, + (unsigned long)buffer + total_len); + + c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write; c.rw.flags = 0; c.rw.nsid = cpu_to_le32(ns->ns_id); c.rw.control = 0; @@ -692,76 +708,39 @@ static ulong nvme_blk_read(struct udevice *udev, lbaint_t blknr, total_lbas -= lbas; } - if (nvme_setup_prps - (dev, &prp2, lbas << ns->lba_shift, (ulong)buffer)) + if (nvme_setup_prps(dev, &prp2, + lbas << ns->lba_shift, (ulong)buffer)) return -EIO; c.rw.slba = cpu_to_le64(slba); slba += lbas; c.rw.length = cpu_to_le16(lbas - 1); c.rw.prp1 = cpu_to_le64((ulong)buffer); c.rw.prp2 = cpu_to_le64(prp2); - status = nvme_submit_sync_cmd(dev->queues[1], + status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], &c, NULL, IO_TIMEOUT); if (status) break; - temp_len -= lbas << ns->lba_shift; + temp_len -= (u32)lbas << ns->lba_shift; buffer += lbas << ns->lba_shift; } + if (read) + invalidate_dcache_range((unsigned long)buffer, + (unsigned long)buffer + total_len); + return (total_len - temp_len) >> desc->log2blksz; } +static ulong nvme_blk_read(struct udevice *udev, lbaint_t blknr, + lbaint_t blkcnt, void *buffer) +{ + return nvme_blk_rw(udev, blknr, blkcnt, buffer, true); +} + static ulong nvme_blk_write(struct udevice *udev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer) { - struct nvme_ns *ns = dev_get_priv(udev); - struct nvme_dev *dev = ns->dev; - struct nvme_command c; - struct blk_desc *desc = dev_get_uclass_platdata(udev); - int status; - u64 prp2; - u64 total_len = blkcnt << desc->log2blksz; - u64 temp_len = total_len; - - u64 slba = blknr; - u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift); - u64 total_lbas = blkcnt; - - c.rw.opcode = nvme_cmd_write; - c.rw.flags = 0; - c.rw.nsid = cpu_to_le32(ns->ns_id); - c.rw.control = 0; - c.rw.dsmgmt = 0; - c.rw.reftag = 0; - c.rw.apptag = 0; - c.rw.appmask = 0; - c.rw.metadata = 0; - - while (total_lbas) { - if (total_lbas < lbas) { - lbas = (u16)total_lbas; - total_lbas = 0; - } else { - total_lbas -= lbas; - } - - if (nvme_setup_prps - (dev, &prp2, lbas << ns->lba_shift, (ulong)buffer)) - return -EIO; - c.rw.slba = cpu_to_le64(slba); - slba += lbas; - c.rw.length = cpu_to_le16(lbas - 1); - c.rw.prp1 = cpu_to_le64((ulong)buffer); - c.rw.prp2 = cpu_to_le64(prp2); - status = nvme_submit_sync_cmd(dev->queues[1], - &c, NULL, IO_TIMEOUT); - if (status) - break; - temp_len -= lbas << ns->lba_shift; - buffer += lbas << ns->lba_shift; - } - - return (total_len - temp_len) >> desc->log2blksz; + return nvme_blk_rw(udev, blknr, blkcnt, (void *)buffer, false); } static const struct blk_ops nvme_blk_ops = { @@ -779,8 +758,10 @@ U_BOOT_DRIVER(nvme_blk) = { static int nvme_bind(struct udevice *udev) { + static int ndev_num; char name[20]; - sprintf(name, "nvme#%d", nvme_info->ndev_num++); + + sprintf(name, "nvme#%d", ndev_num++); return device_set_name(udev, name); } @@ -789,9 +770,7 @@ static int nvme_probe(struct udevice *udev) { int ret; struct nvme_dev *ndev = dev_get_priv(udev); - u64 cap; - ndev->pdev = pci_get_controller(udev); ndev->instance = trailing_strtol(udev->name); INIT_LIST_HEAD(&ndev->namespaces); @@ -803,13 +782,13 @@ static int nvme_probe(struct udevice *udev) goto free_nvme; } - ndev->queues = malloc(2 * sizeof(struct nvme_queue)); + ndev->queues = malloc(NVME_Q_NUM * sizeof(struct nvme_queue *)); if (!ndev->queues) { ret = -ENOMEM; printf("Error: %s: Out of memory!\n", udev->name); goto free_nvme; } - memset(ndev->queues, 0, sizeof(2 * sizeof(struct nvme_queue))); + memset(ndev->queues, 0, NVME_Q_NUM * sizeof(struct nvme_queue *)); ndev->prp_pool = malloc(MAX_PRP_POOL); if (!ndev->prp_pool) { @@ -819,9 +798,9 @@ static int nvme_probe(struct udevice *udev) } ndev->prp_entry_num = MAX_PRP_POOL >> 3; - cap = nvme_readq(&ndev->bar->cap); - ndev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); - ndev->db_stride = 1 << NVME_CAP_STRIDE(cap); + ndev->cap = nvme_readq(&ndev->bar->cap); + ndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH); + ndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap); ndev->dbs = ((void __iomem *)ndev->bar) + 4096; ret = nvme_configure_admin_queue(ndev); @@ -833,8 +812,6 @@ static int nvme_probe(struct udevice *udev) goto free_queue; nvme_get_info_from_identify(ndev); - ndev->blk_dev_start = nvme_info->ns_num; - list_add(&ndev->node, &nvme_info->dev_list); return 0; diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h index b7fdd0b8e2..67bf6e187f 100644 --- a/drivers/nvme/nvme.h +++ b/drivers/nvme/nvme.h @@ -528,42 +528,6 @@ struct nvme_completion { __le16 status; /* did the command fail, and if so, why? */ }; -struct nvme_user_io { - __u8 opcode; - __u8 flags; - __u16 control; - __u16 nblocks; - __u16 rsvd; - __u64 metadata; - __u64 addr; - __u64 slba; - __u32 dsmgmt; - __u32 reftag; - __u16 apptag; - __u16 appmask; -}; - -struct nvme_passthru_cmd { - __u8 opcode; - __u8 flags; - __u16 rsvd1; - __u32 nsid; - __u32 cdw2; - __u32 cdw3; - __u64 metadata; - __u64 addr; - __u32 metadata_len; - __u32 data_len; - __u32 cdw10; - __u32 cdw11; - __u32 cdw12; - __u32 cdw13; - __u32 cdw14; - __u32 cdw15; - __u32 timeout_ms; - __u32 result; -}; - /* * Registers should always be accessed with double word or quad word * accesses. Registers with 64-bit address pointers should be written @@ -644,11 +608,7 @@ struct nvme_dev { struct list_head node; struct nvme_queue **queues; u32 __iomem *dbs; - unsigned int cardnum; - struct udevice *pdev; - pci_dev_t pci_dev; int instance; - uint8_t *hw_addr; unsigned queue_count; unsigned online_queues; unsigned max_qid; @@ -657,42 +617,17 @@ struct nvme_dev { u32 ctrl_config; struct nvme_bar __iomem *bar; struct list_head namespaces; - const char *name; char serial[20]; char model[40]; char firmware_rev[8]; u32 max_transfer_shift; + u64 cap; u32 stripe_size; u32 page_size; - u16 oncs; - u16 abort_limit; - u8 event_limit; u8 vwc; u64 *prp_pool; u32 prp_entry_num; u32 nn; - u32 blk_dev_start; -}; - -struct nvme_info { - int ns_num; /*the number of nvme namespaces*/ - int ndev_num; /*the number of nvme devices*/ - struct list_head dev_list; -}; - -/* - * The nvme_iod describes the data in an I/O, including the list of PRP - * entries. You can't see it in this data structure because C doesn't let - * me express that. Use nvme_alloc_iod to ensure there's enough space - * allocated to store the PRP list. - */ -struct nvme_iod { - unsigned long private; /* For the use of the submitter of the I/O */ - int npages; /* In the PRP list. 0 means small pool in use */ - int offset; /* Of PRP list */ - int nents; /* Used in scatterlist */ - int length; /* Of data, in bytes */ - dma_addr_t first_dma; }; /* @@ -705,13 +640,9 @@ struct nvme_ns { unsigned ns_id; int devnum; int lba_shift; - u16 ms; u8 flbas; - u8 pi_type; u64 mode_select_num_blocks; u32 mode_select_block_len; }; -extern struct nvme_info *nvme_info; - #endif /* __DRIVER_NVME_H__ */ diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c index 5577e5de45..52351388e2 100644 --- a/drivers/nvme/nvme_show.c +++ b/drivers/nvme/nvme_show.c @@ -8,6 +8,7 @@ #include <common.h> #include <dm.h> #include <errno.h> +#include <memalign.h> #include <nvme.h> #include "nvme.h" @@ -106,8 +107,10 @@ int nvme_print_info(struct udevice *udev) { struct nvme_ns *ns = dev_get_priv(udev); struct nvme_dev *dev = ns->dev; - struct nvme_id_ns buf_ns, *id = &buf_ns; - struct nvme_id_ctrl buf_ctrl, *ctrl = &buf_ctrl; + ALLOC_CACHE_ALIGN_BUFFER(char, buf_ns, sizeof(struct nvme_id_ns)); + struct nvme_id_ns *id = (struct nvme_id_ns *)buf_ns; + ALLOC_CACHE_ALIGN_BUFFER(char, buf_ctrl, sizeof(struct nvme_id_ctrl)); + struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf_ctrl; if (nvme_identify(dev, 0, 1, (dma_addr_t)ctrl)) return -EIO; diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 75fb093337..46fe5e6247 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -202,47 +202,6 @@ static int pci_rom_load(struct pci_rom_header *rom_header, struct vbe_mode_info mode_info; -int vbe_get_video_info(struct graphic_device *gdev) -{ -#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE - struct vesa_mode_info *vesa = &mode_info.vesa; - - gdev->winSizeX = vesa->x_resolution; - gdev->winSizeY = vesa->y_resolution; - - gdev->plnSizeX = vesa->x_resolution; - gdev->plnSizeY = vesa->y_resolution; - - gdev->gdfBytesPP = vesa->bits_per_pixel / 8; - - switch (vesa->bits_per_pixel) { - case 32: - case 24: - gdev->gdfIndex = GDF_32BIT_X888RGB; - break; - case 16: - gdev->gdfIndex = GDF_16BIT_565RGB; - break; - default: - gdev->gdfIndex = GDF__8BIT_INDEX; - break; - } - - gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; - gdev->pciBase = vesa->phys_base_ptr; - - gdev->frameAdrs = vesa->phys_base_ptr; - gdev->memSize = vesa->bytes_per_scanline * vesa->y_resolution; - - gdev->vprBase = vesa->phys_base_ptr; - gdev->cprBase = vesa->phys_base_ptr; - - return gdev->winSizeX ? 0 : -ENOSYS; -#else - return -ENOSYS; -#endif -} - void setup_video(struct screen_info *screen_info) { struct vesa_mode_info *vesa = &mode_info.vesa; diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 1b6107fae6..32cbac963f 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -158,7 +158,7 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) if (!(config_val & IMX_NO_PAD_CTL)) { if (info->flags & SHARE_MUX_CONF_REG) { clrsetbits_le32(info->base + conf_reg, - info->mux_mask, config_val); + ~info->mux_mask, config_val); } else { writel(config_val, info->base + conf_reg); } diff --git a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c index 4a893e5a65..618ce6a0e1 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c @@ -12,7 +12,11 @@ #include "pinctrl-imx.h" -static struct imx_pinctrl_soc_info imx7ulp_pinctrl_soc_info = { +static struct imx_pinctrl_soc_info imx7ulp_pinctrl_soc_info0 = { + .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CONFIG_IBE_OBE, +}; + +static struct imx_pinctrl_soc_info imx7ulp_pinctrl_soc_info1 = { .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CONFIG_IBE_OBE, }; @@ -25,8 +29,8 @@ static int imx7ulp_pinctrl_probe(struct udevice *dev) } static const struct udevice_id imx7ulp_pinctrl_match[] = { - { .compatible = "fsl,imx7ulp-iomuxc-0", .data = (ulong)&imx7ulp_pinctrl_soc_info }, - { .compatible = "fsl,imx7ulp-iomuxc-1", .data = (ulong)&imx7ulp_pinctrl_soc_info }, + { .compatible = "fsl,imx7ulp-iomuxc-0", .data = (ulong)&imx7ulp_pinctrl_soc_info0 }, + { .compatible = "fsl,imx7ulp-iomuxc-1", .data = (ulong)&imx7ulp_pinctrl_soc_info1 }, { /* sentinel */ } }; diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 836be25507..47969f3f28 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -18,7 +18,7 @@ config SPL_RAM setting up RAM (e.g. SDRAM / DDR) within SPL. config TPL_RAM - bool "Enable RAM support in SPL" + bool "Enable RAM support in TPL" depends on RAM && TPL_DM help The RAM subsystem adds a small amount of overhead to the image. diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index ebb2cae5eb..c74d16fe20 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -77,6 +77,17 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { UNIPHIER_RESET_END, }; +static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { + UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ + UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ + UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */ + UNIPHIER_RESETX(12, 0x200c, 5), /* USB30 (GIO0) */ + UNIPHIER_RESETX(13, 0x200c, 6), /* USB31 (GIO1) */ + UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY */ + UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY */ + UNIPHIER_RESET_END, +}; + /* Media I/O reset data */ #define UNIPHIER_MIO_RESET_SD(id, ch) \ UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0) @@ -268,6 +279,10 @@ static const struct udevice_id uniphier_reset_match[] = { .compatible = "socionext,uniphier-ld20-reset", .data = (ulong)uniphier_ld20_sys_reset_data, }, + { + .compatible = "socionext,uniphier-pxs3-reset", + .data = (ulong)uniphier_pxs3_sys_reset_data, + }, /* Media I/O reset */ { .compatible = "socionext,uniphier-ld4-mio-reset", @@ -294,7 +309,15 @@ static const struct udevice_id uniphier_reset_match[] = { .data = (ulong)uniphier_mio_reset_data, }, { - .compatible = "socionext,uniphier-ld20-mio-reset", + .compatible = "socionext,uniphier-ld11-sd-reset", + .data = (ulong)uniphier_mio_reset_data, + }, + { + .compatible = "socionext,uniphier-ld20-sd-reset", + .data = (ulong)uniphier_mio_reset_data, + }, + { + .compatible = "socionext,uniphier-pxs3-sd-reset", .data = (ulong)uniphier_mio_reset_data, }, /* Peripheral reset */ @@ -326,6 +349,10 @@ static const struct udevice_id uniphier_reset_match[] = { .compatible = "socionext,uniphier-ld20-peri-reset", .data = (ulong)uniphier_pro4_peri_reset_data, }, + { + .compatible = "socionext,uniphier-pxs3-peri-reset", + .data = (ulong)uniphier_pro4_peri_reset_data, + }, { /* sentinel */ } }; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index a8e997834a..aeed538fa4 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -64,15 +64,20 @@ config DM_SERIAL implements serial_putc() etc. The uclass interface is defined in include/serial.h. -config SERIAL_IRQ_BUFFER - bool "Enable RX interrupt buffer for serial input" +config SERIAL_RX_BUFFER + bool "Enable RX buffer for serial input" depends on DM_SERIAL - default n help - Enable RX interrupt buffer support for the serial driver. - This enables pasting longer strings, even when the RX FIFO - of the UART is not big enough (e.g. 16 bytes on the normal - NS16550). + Enable RX buffer support for the serial driver. This enables + pasting longer strings, even when the RX FIFO of the UART is + not big enough (e.g. 16 bytes on the normal NS16550). + +config SERIAL_RX_BUFFER_SIZE + int "RX buffer size" + depends on SERIAL_RX_BUFFER + default 256 + help + The size of the RX buffer (needs to be power of 2) config SPL_DM_SERIAL bool "Enable Driver Model for serial drivers in SPL" diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 607a1b8c1d..c702304e79 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -314,80 +314,6 @@ DEBUG_UART_FUNCS #endif #ifdef CONFIG_DM_SERIAL - -#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER) - -#define BUF_COUNT 256 - -static void rx_fifo_to_buf(struct udevice *dev) -{ - struct NS16550 *const com_port = dev_get_priv(dev); - struct ns16550_platdata *plat = dev->platdata; - - /* Read all available chars into buffer */ - while ((serial_in(&com_port->lsr) & UART_LSR_DR)) { - plat->buf[plat->wr_ptr++] = serial_in(&com_port->rbr); - plat->wr_ptr %= BUF_COUNT; - } -} - -static int rx_pending(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev->platdata; - - /* - * At startup it may happen, that some already received chars are - * "stuck" in the RX FIFO, even with the interrupt enabled. This - * RX FIFO flushing makes sure, that these chars are read out and - * the RX interrupts works as expected. - */ - rx_fifo_to_buf(dev); - - return plat->rd_ptr != plat->wr_ptr ? 1 : 0; -} - -static int rx_get(struct udevice *dev) -{ - struct ns16550_platdata *plat = dev->platdata; - char val; - - val = plat->buf[plat->rd_ptr++]; - plat->rd_ptr %= BUF_COUNT; - - return val; -} - -void ns16550_handle_irq(void *data) -{ - struct udevice *dev = (struct udevice *)data; - struct NS16550 *const com_port = dev_get_priv(dev); - - /* Check if interrupt is pending */ - if (serial_in(&com_port->iir) & UART_IIR_NO_INT) - return; - - /* Flush all available characters from the RX FIFO into the RX buffer */ - rx_fifo_to_buf(dev); -} - -#else /* CONFIG_SERIAL_IRQ_BUFFER */ - -static int rx_pending(struct udevice *dev) -{ - struct NS16550 *const com_port = dev_get_priv(dev); - - return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0; -} - -static int rx_get(struct udevice *dev) -{ - struct NS16550 *const com_port = dev_get_priv(dev); - - return serial_in(&com_port->rbr); -} - -#endif /* CONFIG_SERIAL_IRQ_BUFFER */ - static int ns16550_serial_putc(struct udevice *dev, const char ch) { struct NS16550 *const com_port = dev_get_priv(dev); @@ -413,17 +339,19 @@ static int ns16550_serial_pending(struct udevice *dev, bool input) struct NS16550 *const com_port = dev_get_priv(dev); if (input) - return rx_pending(dev); + return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0; else return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1; } static int ns16550_serial_getc(struct udevice *dev) { - if (!ns16550_serial_pending(dev, true)) + struct NS16550 *const com_port = dev_get_priv(dev); + + if (!(serial_in(&com_port->lsr) & UART_LSR_DR)) return -EAGAIN; - return rx_get(dev); + return serial_in(&com_port->rbr); } static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) @@ -446,39 +374,8 @@ int ns16550_serial_probe(struct udevice *dev) com_port->plat = dev_get_platdata(dev); NS16550_init(com_port, -1); -#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER) - if (gd->flags & GD_FLG_RELOC) { - struct ns16550_platdata *plat = dev->platdata; - - /* Allocate the RX buffer */ - plat->buf = malloc(BUF_COUNT); - - /* Install the interrupt handler */ - irq_install_handler(plat->irq, ns16550_handle_irq, dev); - - /* Enable RX interrupts */ - serial_out(UART_IER_RDI, &com_port->ier); - } -#endif - - return 0; -} - -#if CONFIG_IS_ENABLED(SERIAL_PRESENT) && \ - (!defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL)) -static int ns16550_serial_remove(struct udevice *dev) -{ -#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER) - if (gd->flags & GD_FLG_RELOC) { - struct ns16550_platdata *plat = dev->platdata; - - irq_free_handler(plat->irq); - } -#endif - return 0; } -#endif #if CONFIG_IS_ENABLED(OF_CONTROL) enum { @@ -561,15 +458,6 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) if (port_type == PORT_JZ4780) plat->fcr |= UART_FCR_UME; -#if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER) - plat->irq = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "interrupts", 0); - if (!plat->irq) { - debug("ns16550 interrupt not provided\n"); - return -EINVAL; - } -#endif - return 0; } #endif @@ -617,7 +505,6 @@ U_BOOT_DRIVER(ns16550_serial) = { #endif .priv_auto_alloc_size = sizeof(struct NS16550), .probe = ns16550_serial_probe, - .remove = ns16550_serial_remove, .ops = &ns16550_serial_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 998d372da6..2e5116f7ce 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -160,7 +160,7 @@ static void _serial_puts(struct udevice *dev, const char *str) _serial_putc(dev, *str++); } -static int _serial_getc(struct udevice *dev) +static int __serial_getc(struct udevice *dev) { struct dm_serial_ops *ops = serial_get_ops(dev); int err; @@ -174,7 +174,7 @@ static int _serial_getc(struct udevice *dev) return err >= 0 ? err : 0; } -static int _serial_tstc(struct udevice *dev) +static int __serial_tstc(struct udevice *dev) { struct dm_serial_ops *ops = serial_get_ops(dev); @@ -184,6 +184,44 @@ static int _serial_tstc(struct udevice *dev) return 1; } +#if CONFIG_IS_ENABLED(SERIAL_RX_BUFFER) +static int _serial_tstc(struct udevice *dev) +{ + struct serial_dev_priv *upriv = dev_get_uclass_priv(dev); + + /* Read all available chars into the RX buffer */ + while (__serial_tstc(dev)) { + upriv->buf[upriv->wr_ptr++] = __serial_getc(dev); + upriv->wr_ptr %= CONFIG_SERIAL_RX_BUFFER_SIZE; + } + + return upriv->rd_ptr != upriv->wr_ptr ? 1 : 0; +} + +static int _serial_getc(struct udevice *dev) +{ + struct serial_dev_priv *upriv = dev_get_uclass_priv(dev); + char val; + + val = upriv->buf[upriv->rd_ptr++]; + upriv->rd_ptr %= CONFIG_SERIAL_RX_BUFFER_SIZE; + + return val; +} + +#else /* CONFIG_IS_ENABLED(SERIAL_RX_BUFFER) */ + +static int _serial_getc(struct udevice *dev) +{ + return __serial_getc(dev); +} + +static int _serial_tstc(struct udevice *dev) +{ + return __serial_tstc(dev); +} +#endif /* CONFIG_IS_ENABLED(SERIAL_RX_BUFFER) */ + void serial_putc(char ch) { if (gd->cur_serial_dev) @@ -359,6 +397,12 @@ static int serial_post_probe(struct udevice *dev) sdev.puts = serial_stub_puts; sdev.getc = serial_stub_getc; sdev.tstc = serial_stub_tstc; + +#if CONFIG_IS_ENABLED(SERIAL_RX_BUFFER) + /* Allocate the RX buffer */ + upriv->buf = malloc(CONFIG_SERIAL_RX_BUFFER_SIZE); +#endif + stdio_register_dev(&sdev, &upriv->sdev); #endif return 0; diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index bf2e99b5cc..22fc83dd72 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -126,8 +126,6 @@ static int ich_init_controller(struct udevice *dev, if (plat->ich_version == ICHV_7) { struct ich7_spi_regs *ich7_spi = sbase; - ich7_spi = (struct ich7_spi_regs *)sbase; - ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); ctlr->menubytes = sizeof(ich7_spi->opmenu); ctlr->optype = offsetof(struct ich7_spi_regs, optype); @@ -142,7 +140,6 @@ static int ich_init_controller(struct udevice *dev, } else if (plat->ich_version == ICHV_9) { struct ich9_spi_regs *ich9_spi = sbase; - ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); ctlr->menubytes = sizeof(ich9_spi->opmenu); ctlr->optype = offsetof(struct ich9_spi_regs, optype); @@ -187,6 +184,23 @@ static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) trans->bytesin -= bytes; } +static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase) +{ + int lock = 0; + + if (plat->ich_version == ICHV_7) { + struct ich7_spi_regs *ich7_spi = sbase; + + lock = readw(&ich7_spi->spis) & SPIS_LOCK; + } else if (plat->ich_version == ICHV_9) { + struct ich9_spi_regs *ich9_spi = sbase; + + lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; + } + + return lock != 0; +} + static void spi_setup_type(struct spi_trans *trans, int data_bytes) { trans->type = 0xFF; @@ -220,14 +234,15 @@ static void spi_setup_type(struct spi_trans *trans, int data_bytes) } } -static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans) +static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, + bool lock) { uint16_t optypes; uint8_t opmenu[ctlr->menubytes]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); - if (!ctlr->ichspi_lock) { + if (!lock) { /* The lock is off, so just use index 0. */ ich_writeb(ctlr, trans->opcode, ctlr->opmenu); optypes = ich_readw(ctlr, ctlr->optype); @@ -323,6 +338,21 @@ static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, return -ETIMEDOUT; } +void ich_spi_config_opcode(struct udevice *dev) +{ + struct ich_spi_priv *ctlr = dev_get_priv(dev); + + /* + * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down + * to prevent accidental or intentional writes. Before they get + * locked down, these registers should be initialized properly. + */ + ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop); + ich_writew(ctlr, SPI_OPTYPE, ctlr->optype); + ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu); + ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); +} + static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { @@ -337,6 +367,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, struct spi_trans *trans = &ctlr->trans; unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); int using_cmd = 0; + bool lock = spi_lock_status(plat, ctlr->base); int ret; /* We don't support writing partial bytes */ @@ -400,7 +431,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); spi_setup_type(trans, using_cmd ? bytes : 0); - opcode_index = spi_setup_opcode(ctlr, trans); + opcode_index = spi_setup_opcode(ctlr, trans, lock); if (opcode_index < 0) return -EINVAL; with_address = spi_setup_offset(trans); @@ -413,7 +444,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, * in order to prevent the Management Engine from * issuing a transaction between WREN and DATA. */ - if (!ctlr->ichspi_lock) + if (!lock) ich_writew(ctlr, trans->opcode, ctlr->preop); return 0; } @@ -437,8 +468,6 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, } /* Preset control fields */ - control = ich_readw(ctlr, ctlr->control); - control &= ~SSFC_RESERVED; control = SPIC_SCGO | ((opcode_index & 0x07) << 4); /* Issue atomic preop cycle if needed */ @@ -534,57 +563,8 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, } /* Clear atomic preop now that xfer is done */ - ich_writew(ctlr, 0, ctlr->preop); - - return 0; -} - -/* - * This uses the SPI controller from the Intel Cougar Point and Panther Point - * PCH to write-protect portions of the SPI flash until reboot. The changes - * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's - * done elsewhere. - */ -int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, - uint32_t length, int hint) -{ - struct udevice *bus = dev->parent; - struct ich_spi_priv *ctlr = dev_get_priv(bus); - uint32_t tmplong; - uint32_t upper_limit; - - if (!ctlr->pr) { - printf("%s: operation not supported on this chipset\n", - __func__); - return -ENOSYS; - } - - if (length == 0 || - lower_limit > (0xFFFFFFFFUL - length) + 1 || - hint < 0 || hint > 4) { - printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, - lower_limit, length, hint); - return -EPERM; - } - - upper_limit = lower_limit + length - 1; - - /* - * Determine bits to write, as follows: - * 31 Write-protection enable (includes erase operation) - * 30:29 reserved - * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) - * 15 Read-protection enable - * 14:13 reserved - * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) - */ - tmplong = 0x80000000 | - ((upper_limit & 0x01fff000) << 4) | - ((lower_limit & 0x01fff000) >> 12); - - printf("%s: writing 0x%08x to %p\n", __func__, tmplong, - &ctlr->pr[hint]); - ctlr->pr[hint] = tmplong; + if (!lock) + ich_writew(ctlr, 0, ctlr->preop); return 0; } @@ -619,16 +599,11 @@ static int ich_spi_probe(struct udevice *dev) static int ich_spi_remove(struct udevice *bus) { - struct ich_spi_priv *ctlr = dev_get_priv(bus); - /* * Configure SPI controller so that the Linux MTD driver can fully * access the SPI NOR chip */ - ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop); - ich_writew(ctlr, SPI_OPTYPE, ctlr->optype); - ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu); - ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); + ich_spi_config_opcode(bus); return 0; } diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index dcb8a9048f..c867c57be9 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -177,8 +177,6 @@ struct ich_spi_platdata { }; struct ich_spi_priv { - int ichspi_lock; - int locked; int opmenu; int menubytes; void *base; /* Base of register set */ diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 13f122350b..6305bbf01c 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -44,6 +44,14 @@ config ALTERA_TIMER Select this to enable a timer for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ATMEL_PIT_TIMER + bool "Atmel periodic interval timer support" + depends on TIMER + help + Select this to enable a periodic interval timer for Atmel devices, + it is designed to offer maximum accuracy and efficient management, + even for systems with long response time. + config SANDBOX_TIMER bool "Sandbox timer support" depends on SANDBOX && TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index fa7ce7c835..69e8961a7b 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o +obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c new file mode 100644 index 0000000000..999717b91f --- /dev/null +++ b/drivers/timer/atmel_pit_timer.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2017 Microchip Corporation + * Wenyou.Yang <wenyou.yang@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <timer.h> +#include <asm/io.h> + +#define AT91_PIT_VALUE 0xfffff +#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */ + +struct atmel_pit_regs { + u32 mode; + u32 status; + u32 value; + u32 value_image; +}; + +struct atmel_pit_platdata { + struct atmel_pit_regs *regs; +}; + +static int atmel_pit_get_count(struct udevice *dev, u64 *count) +{ + struct atmel_pit_platdata *plat = dev_get_platdata(dev); + struct atmel_pit_regs *const regs = plat->regs; + u32 val = readl(®s->value_image); + + *count = timer_conv_64(val); + + return 0; +} + +static int atmel_pit_probe(struct udevice *dev) +{ + struct atmel_pit_platdata *plat = dev_get_platdata(dev); + struct atmel_pit_regs *const regs = plat->regs; + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk clk; + ulong clk_rate; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return -EINVAL; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) + return -EINVAL; + + uc_priv->clock_rate = clk_rate / 16; + + writel(AT91_PIT_VALUE | AT91_PIT_PITEN, ®s->mode); + + return 0; +} + +static int atmel_pit_ofdata_to_platdata(struct udevice *dev) +{ + struct atmel_pit_platdata *plat = dev_get_platdata(dev); + + plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev); + + return 0; +} + +static const struct timer_ops atmel_pit_ops = { + .get_count = atmel_pit_get_count, +}; + +static const struct udevice_id atmel_pit_ids[] = { + { .compatible = "atmel,at91sam9260-pit" }, + { } +}; + +U_BOOT_DRIVER(atmel_pit) = { + .name = "atmel_pit", + .id = UCLASS_TIMER, + .of_match = atmel_pit_ids, + .ofdata_to_platdata = atmel_pit_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata), + .probe = atmel_pit_probe, + .ops = &atmel_pit_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index e93398fe7c..a291ceb6ae 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -1,7 +1,6 @@ config USB_DWC3 bool "DesignWare USB3 DRD Core Support" - depends on (USB && USB_GADGET) - select USB_GADGET_DUALSPEED + depends on USB_HOST || USB_GADGET help Say Y here if your system has a Dual Role SuperSpeed USB controller based on the DesignWare USB3 IP Core. @@ -21,6 +20,7 @@ config USB_DWC3_HOST config USB_DWC3_GADGET bool "Gadget only mode" depends on USB_GADGET + select USB_GADGET_DUALSPEED help Select this when you want to use DWC3 in gadget mode only, thereby the host feature will be regressed. diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 261ed128ac..225b66bc95 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -103,6 +103,13 @@ config USB_GADGET_DOWNLOAD if USB_GADGET_DOWNLOAD +config USB_FUNCTION_SDP + bool "Enable USB SDP (Serial Download Protocol)" + help + Enable Serial Download Protocol (SDP) device support in U-Boot. This + allows to download images into memory and execute (jump to) them + using the same protocol as implemented by the i.MX family's boot ROM. + config G_DNL_MANUFACTURER string "Vendor name of USB device" diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 5e316a7cff..7258099c1c 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += g_dnl.o obj-$(CONFIG_SPL_DFU_SUPPORT) += f_dfu.o +obj-$(CONFIG_SPL_USB_SDP_SUPPORT) += f_sdp.o endif # new USB gadget layer dependencies @@ -28,6 +29,7 @@ obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o obj-$(CONFIG_USB_FUNCTION_DFU) += f_dfu.o obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o +obj-$(CONFIG_USB_FUNCTION_SDP) += f_sdp.o endif endif ifdef CONFIG_USB_ETHER diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c new file mode 100644 index 0000000000..0fae66beab --- /dev/null +++ b/drivers/usb/gadget/f_sdp.c @@ -0,0 +1,737 @@ +/* + * f_sdp.c -- USB HID Serial Download Protocol + * + * Copyright (C) 2017 Toradex + * Author: Stefan Agner <stefan.agner@toradex.com> + * + * This file implements the Serial Download Protocol (SDP) as specified in + * the i.MX 6 Reference Manual. The SDP is a USB HID based protocol and + * allows to download images directly to memory. The implementation + * works with the imx_loader (imx_usb) USB client software on host side. + * + * Not all commands are implemented, e.g. WRITE_REGISTER, DCD_WRITE and + * SKIP_DCD_HEADER are only stubs. + * + * Parts of the implementation are based on f_dfu and f_thor. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <errno.h> +#include <common.h> +#include <console.h> +#include <malloc.h> + +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/composite.h> + +#include <asm/io.h> +#include <g_dnl.h> +#include <sdp.h> +#include <spl.h> +#include <image.h> +#include <imximage.h> + +#define HID_REPORT_ID_MASK 0x000000ff + +/* + * HID class requests + */ +#define HID_REQ_GET_REPORT 0x01 +#define HID_REQ_GET_IDLE 0x02 +#define HID_REQ_GET_PROTOCOL 0x03 +#define HID_REQ_SET_REPORT 0x09 +#define HID_REQ_SET_IDLE 0x0A +#define HID_REQ_SET_PROTOCOL 0x0B + +#define HID_USAGE_PAGE_LEN 76 + +struct hid_report { + u8 usage_page[HID_USAGE_PAGE_LEN]; +} __packed; + +#define SDP_READ_REGISTER 0x0101 +#define SDP_WRITE_REGISTER 0x0202 +#define SDP_WRITE_FILE 0x0404 +#define SDP_ERROR_STATUS 0x0505 +#define SDP_DCD_WRITE 0x0a0a +#define SDP_JUMP_ADDRESS 0x0b0b +#define SDP_SKIP_DCD_HEADER 0x0c0c + +#define SDP_SECURITY_CLOSED 0x12343412 +#define SDP_SECURITY_OPEN 0x56787856 + +#define SDP_WRITE_FILE_COMPLETE 0x88888888 +#define SDP_WRITE_REGISTER_COMPLETE 0x128A8A12 +#define SDP_SKIP_DCD_HEADER_COMPLETE 0x900DD009 +#define SDP_ERROR_IMXHEADER 0x000a0533 + +#define SDP_COMMAND_LEN 16 + +struct sdp_command { + u16 cmd; + u32 addr; + u8 format; + u32 cnt; + u32 data; + u8 rsvd; +} __packed; + +enum sdp_state { + SDP_STATE_IDLE, + SDP_STATE_RX_DCD_DATA, + SDP_STATE_RX_FILE_DATA, + SDP_STATE_TX_SEC_CONF, + SDP_STATE_TX_SEC_CONF_BUSY, + SDP_STATE_TX_REGISTER, + SDP_STATE_TX_REGISTER_BUSY, + SDP_STATE_TX_STATUS, + SDP_STATE_TX_STATUS_BUSY, + SDP_STATE_JUMP, +}; + +struct f_sdp { + struct usb_function usb_function; + + struct usb_descriptor_header **function; + + u8 altsetting; + enum sdp_state state; + enum sdp_state next_state; + u32 dnl_address; + u32 dnl_bytes_remaining; + u32 jmp_address; + bool always_send_status; + u32 error_status; + + /* EP0 request */ + struct usb_request *req; + + /* EP1 IN */ + struct usb_ep *in_ep; + struct usb_request *in_req; + + bool configuration_done; +}; + +static struct f_sdp *sdp_func; + +static inline struct f_sdp *func_to_sdp(struct usb_function *f) +{ + return container_of(f, struct f_sdp, usb_function); +} + +static struct usb_interface_descriptor sdp_intf_runtime = { + .bLength = sizeof(sdp_intf_runtime), + .bDescriptorType = USB_DT_INTERFACE, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_HID, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, + /* .iInterface = DYNAMIC */ +}; + +/* HID configuration */ +static struct usb_class_hid_descriptor sdp_hid_desc = { + .bLength = sizeof(sdp_hid_desc), + .bDescriptorType = USB_DT_CS_DEVICE, + + .bcdCDC = __constant_cpu_to_le16(0x0110), + .bCountryCode = 0, + .bNumDescriptors = 1, + + .bDescriptorType0 = USB_DT_HID_REPORT, + .wDescriptorLength0 = HID_USAGE_PAGE_LEN, +}; + +static struct usb_endpoint_descriptor in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, /*USB_DT_CS_ENDPOINT*/ + + .bEndpointAddress = 1 | USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = 64, + .bInterval = 1, +}; + +static struct usb_descriptor_header *sdp_runtime_descs[] = { + (struct usb_descriptor_header *)&sdp_intf_runtime, + (struct usb_descriptor_header *)&sdp_hid_desc, + (struct usb_descriptor_header *)&in_desc, + NULL, +}; + +/* This is synchronized with what the SoC implementation reports */ +static struct hid_report sdp_hid_report = { + .usage_page = { + 0x06, 0x00, 0xff, /* Usage Page */ + 0x09, 0x01, /* Usage (Pointer?) */ + 0xa1, 0x01, /* Collection */ + + 0x85, 0x01, /* Report ID */ + 0x19, 0x01, /* Usage Minimum */ + 0x29, 0x01, /* Usage Maximum */ + 0x15, 0x00, /* Local Minimum */ + 0x26, 0xFF, 0x00, /* Local Maximum? */ + 0x75, 0x08, /* Report Size */ + 0x95, 0x10, /* Report Count */ + 0x91, 0x02, /* Output Data */ + + 0x85, 0x02, /* Report ID */ + 0x19, 0x01, /* Usage Minimum */ + 0x29, 0x01, /* Usage Maximum */ + 0x15, 0x00, /* Local Minimum */ + 0x26, 0xFF, 0x00, /* Local Maximum? */ + 0x75, 0x80, /* Report Size 128 */ + 0x95, 0x40, /* Report Count */ + 0x91, 0x02, /* Output Data */ + + 0x85, 0x03, /* Report ID */ + 0x19, 0x01, /* Usage Minimum */ + 0x29, 0x01, /* Usage Maximum */ + 0x15, 0x00, /* Local Minimum */ + 0x26, 0xFF, 0x00, /* Local Maximum? */ + 0x75, 0x08, /* Report Size 8 */ + 0x95, 0x04, /* Report Count */ + 0x81, 0x02, /* Input Data */ + + 0x85, 0x04, /* Report ID */ + 0x19, 0x01, /* Usage Minimum */ + 0x29, 0x01, /* Usage Maximum */ + 0x15, 0x00, /* Local Minimum */ + 0x26, 0xFF, 0x00, /* Local Maximum? */ + 0x75, 0x08, /* Report Size 8 */ + 0x95, 0x40, /* Report Count */ + 0x81, 0x02, /* Input Data */ + 0xc0 + }, +}; + +static const char sdp_name[] = "Serial Downloader Protocol"; + +/* + * static strings, in UTF-8 + */ +static struct usb_string strings_sdp_generic[] = { + [0].s = sdp_name, + { } /* end of list */ +}; + +static struct usb_gadget_strings stringtab_sdp_generic = { + .language = 0x0409, /* en-us */ + .strings = strings_sdp_generic, +}; + +static struct usb_gadget_strings *sdp_generic_strings[] = { + &stringtab_sdp_generic, + NULL, +}; + +static void sdp_rx_command_complete(struct usb_ep *ep, struct usb_request *req) +{ + struct f_sdp *sdp = req->context; + int status = req->status; + u8 *data = req->buf; + u8 report = data[0]; + + if (status != 0) { + error("Status: %d", status); + return; + } + + if (report != 1) { + error("Unexpected report %d", report); + return; + } + + struct sdp_command *cmd = req->buf + 1; + + debug("%s: command: %04x, addr: %08x, cnt: %u\n", + __func__, be16_to_cpu(cmd->cmd), + be32_to_cpu(cmd->addr), be32_to_cpu(cmd->cnt)); + + switch (be16_to_cpu(cmd->cmd)) { + case SDP_READ_REGISTER: + sdp->always_send_status = false; + sdp->error_status = 0x0; + + sdp->state = SDP_STATE_TX_SEC_CONF; + sdp->dnl_address = be32_to_cpu(cmd->addr); + sdp->dnl_bytes_remaining = be32_to_cpu(cmd->cnt); + sdp->next_state = SDP_STATE_TX_REGISTER; + printf("Reading %d registers at 0x%08x... ", + sdp->dnl_bytes_remaining, sdp->dnl_address); + break; + case SDP_WRITE_FILE: + sdp->always_send_status = true; + sdp->error_status = SDP_WRITE_FILE_COMPLETE; + + sdp->state = SDP_STATE_RX_FILE_DATA; + sdp->dnl_address = be32_to_cpu(cmd->addr); + sdp->dnl_bytes_remaining = be32_to_cpu(cmd->cnt); + sdp->next_state = SDP_STATE_IDLE; + + printf("Downloading file of size %d to 0x%08x... ", + sdp->dnl_bytes_remaining, sdp->dnl_address); + + break; + case SDP_ERROR_STATUS: + sdp->always_send_status = true; + sdp->error_status = 0; + + sdp->state = SDP_STATE_TX_SEC_CONF; + sdp->next_state = SDP_STATE_IDLE; + break; + case SDP_DCD_WRITE: + sdp->always_send_status = true; + sdp->error_status = SDP_WRITE_REGISTER_COMPLETE; + + sdp->state = SDP_STATE_RX_DCD_DATA; + sdp->dnl_bytes_remaining = be32_to_cpu(cmd->cnt); + sdp->next_state = SDP_STATE_IDLE; + break; + case SDP_JUMP_ADDRESS: + sdp->always_send_status = false; + sdp->error_status = 0; + + sdp->jmp_address = be32_to_cpu(cmd->addr); + sdp->state = SDP_STATE_TX_SEC_CONF; + sdp->next_state = SDP_STATE_JUMP; + break; + case SDP_SKIP_DCD_HEADER: + sdp->always_send_status = true; + sdp->error_status = SDP_SKIP_DCD_HEADER_COMPLETE; + + /* Ignore command, DCD not supported anyway */ + sdp->state = SDP_STATE_TX_SEC_CONF; + sdp->next_state = SDP_STATE_IDLE; + break; + default: + error("Unknown command: %04x\n", be16_to_cpu(cmd->cmd)); + } +} + +static void sdp_rx_data_complete(struct usb_ep *ep, struct usb_request *req) +{ + struct f_sdp *sdp = req->context; + int status = req->status; + u8 *data = req->buf; + u8 report = data[0]; + int datalen = req->length - 1; + + if (status != 0) { + error("Status: %d", status); + return; + } + + if (report != 2) { + error("Unexpected report %d", report); + return; + } + + if (sdp->dnl_bytes_remaining < datalen) { + /* + * Some USB stacks require to send a complete buffer as + * specified in the HID descriptor. This leads to longer + * transfers than the file length, no problem for us. + */ + sdp->dnl_bytes_remaining = 0; + } else { + sdp->dnl_bytes_remaining -= datalen; + } + + if (sdp->state == SDP_STATE_RX_FILE_DATA) { + memcpy((void *)sdp->dnl_address, req->buf + 1, datalen); + sdp->dnl_address += datalen; + } + + if (sdp->dnl_bytes_remaining) + return; + + printf("done\n"); + + switch (sdp->state) { + case SDP_STATE_RX_FILE_DATA: + sdp->state = SDP_STATE_TX_SEC_CONF; + break; + case SDP_STATE_RX_DCD_DATA: + sdp->state = SDP_STATE_TX_SEC_CONF; + break; + default: + error("Invalid state: %d", sdp->state); + } +} + +static void sdp_tx_complete(struct usb_ep *ep, struct usb_request *req) +{ + struct f_sdp *sdp = req->context; + int status = req->status; + + if (status != 0) { + error("Status: %d", status); + return; + } + + switch (sdp->state) { + case SDP_STATE_TX_SEC_CONF_BUSY: + /* Not all commands require status report */ + if (sdp->always_send_status || sdp->error_status) + sdp->state = SDP_STATE_TX_STATUS; + else + sdp->state = sdp->next_state; + + break; + case SDP_STATE_TX_STATUS_BUSY: + sdp->state = sdp->next_state; + break; + case SDP_STATE_TX_REGISTER_BUSY: + if (sdp->dnl_bytes_remaining) + sdp->state = SDP_STATE_TX_REGISTER; + else + sdp->state = SDP_STATE_IDLE; + break; + default: + error("Wrong State: %d", sdp->state); + sdp->state = SDP_STATE_IDLE; + break; + } + debug("%s complete --> %d, %d/%d\n", ep->name, + status, req->actual, req->length); +} + +static int sdp_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) +{ + struct usb_gadget *gadget = f->config->cdev->gadget; + struct usb_request *req = f->config->cdev->req; + struct f_sdp *sdp = f->config->cdev->req->context; + u16 len = le16_to_cpu(ctrl->wLength); + u16 w_value = le16_to_cpu(ctrl->wValue); + int value = 0; + u8 req_type = ctrl->bRequestType & USB_TYPE_MASK; + + debug("w_value: 0x%04x len: 0x%04x\n", w_value, len); + debug("req_type: 0x%02x ctrl->bRequest: 0x%02x sdp->state: %d\n", + req_type, ctrl->bRequest, sdp->state); + + if (req_type == USB_TYPE_STANDARD) { + if (ctrl->bRequest == USB_REQ_GET_DESCRIPTOR) { + /* Send HID report descriptor */ + value = min(len, (u16) sizeof(sdp_hid_report)); + memcpy(req->buf, &sdp_hid_report, value); + sdp->configuration_done = true; + } + } + + if (req_type == USB_TYPE_CLASS) { + int report = w_value & HID_REPORT_ID_MASK; + + /* HID (SDP) request */ + switch (ctrl->bRequest) { + case HID_REQ_SET_REPORT: + switch (report) { + case 1: + value = SDP_COMMAND_LEN + 1; + req->complete = sdp_rx_command_complete; + break; + case 2: + value = len; + req->complete = sdp_rx_data_complete; + break; + } + } + } + + if (value >= 0) { + req->length = value; + req->zero = value < len; + value = usb_ep_queue(gadget->ep0, req, 0); + if (value < 0) { + debug("ep_queue --> %d\n", value); + req->status = 0; + } + } + + return value; +} + +static int sdp_bind(struct usb_configuration *c, struct usb_function *f) +{ + struct usb_gadget *gadget = c->cdev->gadget; + struct usb_composite_dev *cdev = c->cdev; + struct f_sdp *sdp = func_to_sdp(f); + int rv = 0, id; + + id = usb_interface_id(c, f); + if (id < 0) + return id; + sdp_intf_runtime.bInterfaceNumber = id; + + struct usb_ep *ep; + + /* allocate instance-specific endpoints */ + ep = usb_ep_autoconfig(gadget, &in_desc); + if (!ep) { + rv = -ENODEV; + goto error; + } + + sdp->in_ep = ep; /* Store IN EP for enabling @ setup */ + + cdev->req->context = sdp; + +error: + return rv; +} + +static void sdp_unbind(struct usb_configuration *c, struct usb_function *f) +{ + free(sdp_func); + sdp_func = NULL; +} + +static struct usb_request *alloc_ep_req(struct usb_ep *ep, unsigned length) +{ + struct usb_request *req; + + req = usb_ep_alloc_request(ep, 0); + if (!req) + return req; + + req->length = length; + req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, length); + if (!req->buf) { + usb_ep_free_request(ep, req); + req = NULL; + } + + return req; +} + + +static struct usb_request *sdp_start_ep(struct usb_ep *ep) +{ + struct usb_request *req; + + req = alloc_ep_req(ep, 64); + debug("%s: ep:%p req:%p\n", __func__, ep, req); + + if (!req) + return NULL; + + memset(req->buf, 0, req->length); + req->complete = sdp_tx_complete; + + return req; +} +static int sdp_set_alt(struct usb_function *f, unsigned intf, unsigned alt) +{ + struct f_sdp *sdp = func_to_sdp(f); + struct usb_composite_dev *cdev = f->config->cdev; + int result; + + debug("%s: intf: %d alt: %d\n", __func__, intf, alt); + + result = usb_ep_enable(sdp->in_ep, &in_desc); + if (result) + return result; + sdp->in_req = sdp_start_ep(sdp->in_ep); + sdp->in_req->context = sdp; + + sdp->in_ep->driver_data = cdev; /* claim */ + + sdp->altsetting = alt; + sdp->state = SDP_STATE_IDLE; + + return 0; +} + +static int sdp_get_alt(struct usb_function *f, unsigned intf) +{ + struct f_sdp *sdp = func_to_sdp(f); + + return sdp->altsetting; +} + +static void sdp_disable(struct usb_function *f) +{ + struct f_sdp *sdp = func_to_sdp(f); + + usb_ep_disable(sdp->in_ep); + + if (sdp->in_req) { + free(sdp->in_req); + sdp->in_req = NULL; + } +} + +static int sdp_bind_config(struct usb_configuration *c) +{ + int status; + + if (!sdp_func) { + sdp_func = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*sdp_func)); + if (!sdp_func) + return -ENOMEM; + } + + memset(sdp_func, 0, sizeof(*sdp_func)); + + sdp_func->usb_function.name = "sdp"; + sdp_func->usb_function.hs_descriptors = sdp_runtime_descs; + sdp_func->usb_function.descriptors = sdp_runtime_descs; + sdp_func->usb_function.bind = sdp_bind; + sdp_func->usb_function.unbind = sdp_unbind; + sdp_func->usb_function.set_alt = sdp_set_alt; + sdp_func->usb_function.get_alt = sdp_get_alt; + sdp_func->usb_function.disable = sdp_disable; + sdp_func->usb_function.strings = sdp_generic_strings; + sdp_func->usb_function.setup = sdp_setup; + + status = usb_add_function(c, &sdp_func->usb_function); + + return status; +} + +int sdp_init(int controller_index) +{ + printf("SDP: initialize...\n"); + while (!sdp_func->configuration_done) { + if (ctrlc()) { + puts("\rCTRL+C - Operation aborted.\n"); + return 1; + } + usb_gadget_handle_interrupts(controller_index); + } + + return 0; +} + +static u32 sdp_jump_imxheader(void *address) +{ + flash_header_v2_t *headerv2 = address; + ulong (*entry)(void); + + if (headerv2->header.tag != IVT_HEADER_TAG) { + printf("Header Tag is not an IMX image\n"); + return SDP_ERROR_IMXHEADER; + } + + printf("Jumping to 0x%08x\n", headerv2->entry); + entry = (void *)headerv2->entry; + entry(); + + /* The image probably never returns hence we won't reach that point */ + return 0; +} + +static void sdp_handle_in_ep(void) +{ + u8 *data = sdp_func->in_req->buf; + u32 status; + int datalen; + + switch (sdp_func->state) { + case SDP_STATE_TX_SEC_CONF: + debug("Report 3: HAB security\n"); + data[0] = 3; + + status = SDP_SECURITY_OPEN; + memcpy(&data[1], &status, 4); + sdp_func->in_req->length = 5; + usb_ep_queue(sdp_func->in_ep, sdp_func->in_req, 0); + sdp_func->state = SDP_STATE_TX_SEC_CONF_BUSY; + break; + + case SDP_STATE_TX_STATUS: + debug("Report 4: Status\n"); + data[0] = 4; + + memcpy(&data[1], &sdp_func->error_status, 4); + sdp_func->in_req->length = 65; + usb_ep_queue(sdp_func->in_ep, sdp_func->in_req, 0); + sdp_func->state = SDP_STATE_TX_STATUS_BUSY; + break; + case SDP_STATE_TX_REGISTER: + debug("Report 4: Register Values\n"); + data[0] = 4; + + datalen = sdp_func->dnl_bytes_remaining; + + if (datalen > 64) + datalen = 64; + + memcpy(&data[1], (void *)sdp_func->dnl_address, datalen); + sdp_func->in_req->length = 65; + + sdp_func->dnl_bytes_remaining -= datalen; + sdp_func->dnl_address += datalen; + + usb_ep_queue(sdp_func->in_ep, sdp_func->in_req, 0); + sdp_func->state = SDP_STATE_TX_REGISTER_BUSY; + break; + case SDP_STATE_JUMP: + printf("Jumping to header at 0x%08x\n", sdp_func->jmp_address); + status = sdp_jump_imxheader((void *)sdp_func->jmp_address); + + /* If imx header fails, try some U-Boot specific headers */ + if (status) { +#ifdef CONFIG_SPL_BUILD + /* In SPL, allow jumps to U-Boot images */ + struct spl_image_info spl_image = {}; + spl_parse_image_header(&spl_image, + (struct image_header *)sdp_func->jmp_address); + jump_to_image_no_args(&spl_image); +#else + /* In U-Boot, allow jumps to scripts */ + source(sdp_func->jmp_address, "script@1"); +#endif + } + + sdp_func->next_state = SDP_STATE_IDLE; + sdp_func->error_status = status; + + /* Only send Report 4 if there was an error */ + if (status) + sdp_func->state = SDP_STATE_TX_STATUS; + else + sdp_func->state = SDP_STATE_IDLE; + break; + default: + break; + }; +} + +void sdp_handle(int controller_index) +{ + printf("SDP: handle requests...\n"); + while (1) { + if (ctrlc()) { + puts("\rCTRL+C - Operation aborted.\n"); + return; + } + + usb_gadget_handle_interrupts(controller_index); + + sdp_handle_in_ep(); + } +} + +int sdp_add(struct usb_configuration *c) +{ + int id; + + id = usb_string_id(c->cdev); + if (id < 0) + return id; + strings_sdp_generic[0].id = id; + sdp_intf_runtime.iInterface = id; + + debug("%s: cdev: %p gadget: %p gadget->ep0: %p\n", __func__, + c->cdev, c->cdev->gadget, c->cdev->gadget->ep0); + + return sdp_bind_config(c); +} + +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_sdp, sdp_add); |