diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/hi6220_dw_mmc.c | 2 | ||||
| -rw-r--r-- | drivers/mtd/stm32_flash.c | 2 | ||||
| -rw-r--r-- | drivers/phy/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/pinctrl/pinctrl_stm32.c | 62 |
4 files changed, 53 insertions, 17 deletions
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c index fdaf1e40bc..d795198534 100644 --- a/drivers/mmc/hi6220_dw_mmc.c +++ b/drivers/mmc/hi6220_dw_mmc.c @@ -20,7 +20,7 @@ static int hi6220_dwmci_core_init(struct dwmci_host *host, int index) { - host->name = "HiKey DWMMC"; + host->name = "Hisilicon DWMMC"; host->dev_index = index; diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c index e16b6cd674..472499d83c 100644 --- a/drivers/mtd/stm32_flash.c +++ b/drivers/mtd/stm32_flash.c @@ -17,7 +17,7 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; void stm32_flash_latency_cfg(int latency) { /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */ - writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN + writel(FLASH_ACR_WS(latency) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN, &STM32_FLASH->acr); } diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a91a6946b8..7841554d09 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -43,7 +43,7 @@ config PHY_SANDBOX config PIPE3_PHY bool "Support omap's PIPE3 PHY" - depends on PHY && ARCH_OMAP2 + depends on PHY && ARCH_OMAP2PLUS help Support for the omap PIPE3 phy for sata @@ -52,7 +52,7 @@ config PIPE3_PHY config SPL_PIPE3_PHY bool "Support omap's PIPE3 PHY in SPL" - depends on SPL_PHY && ARCH_OMAP2 + depends on SPL_PHY && ARCH_OMAP2PLUS help Support for the omap PIPE3 phy for sata in SPL diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 5bee7fb12a..fb2593c690 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -93,39 +93,31 @@ static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node) return 0; } -static int stm32_pinctrl_set_state_simple(struct udevice *dev, - struct udevice *periph) +static int stm32_pinctrl_config(int offset) { u32 pin_mux[MAX_PINS_ONE_IP]; - struct fdtdec_phandle_args args; int rv, len; - /* Get node pinctrl-0 */ - rv = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(periph), - "pinctrl-0", 0, 0, 0, &args); - if (rv) - return rv; /* * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for * usart1) of pin controller phandle "pinctrl-0" * */ - fdt_for_each_subnode(args.node, gd->fdt_blob, args.node) { + fdt_for_each_subnode(offset, gd->fdt_blob, offset) { struct stm32_gpio_dsc gpio_dsc; struct stm32_gpio_ctl gpio_ctl; int i; - len = fdtdec_get_int_array_count(gd->fdt_blob, args.node, + len = fdtdec_get_int_array_count(gd->fdt_blob, offset, "pinmux", pin_mux, ARRAY_SIZE(pin_mux)); - debug("%s: periph->name = %s, no of pinmux entries= %d\n", - __func__, periph->name, len); + debug("%s: no of pinmux entries= %d\n", __func__, len); if (len < 0) return -EINVAL; for (i = 0; i < len; i++) { struct gpio_desc desc; debug("%s: pinmux = %x\n", __func__, *(pin_mux + i)); prep_gpio_dsc(&gpio_dsc, *(pin_mux + i)); - prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), args.node); + prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset); rv = uclass_get_device_by_seq(UCLASS_GPIO, gpio_dsc.port, &desc.dev); if (rv) @@ -141,8 +133,52 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev, return 0; } +#if CONFIG_IS_ENABLED(PINCTRL_FULL) +static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + return stm32_pinctrl_config(dev_of_offset(config)); +} +#else /* PINCTRL_FULL */ +static int stm32_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + const void *fdt = gd->fdt_blob; + const fdt32_t *list; + uint32_t phandle; + int config_node; + int size, i, ret; + + list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size); + if (!list) + return -EINVAL; + + debug("%s: periph->name = %s\n", __func__, periph->name); + + size /= sizeof(*list); + for (i = 0; i < size; i++) { + phandle = fdt32_to_cpu(*list++); + + config_node = fdt_node_offset_by_phandle(fdt, phandle); + if (config_node < 0) { + error("prop pinctrl-0 index %d invalid phandle\n", i); + return -EINVAL; + } + + ret = stm32_pinctrl_config(config_node); + if (ret) + return ret; + } + + return 0; +} +#endif /* PINCTRL_FULL */ + static struct pinctrl_ops stm32_pinctrl_ops = { +#if CONFIG_IS_ENABLED(PINCTRL_FULL) + .set_state = stm32_pinctrl_set_state, +#else /* PINCTRL_FULL */ .set_state_simple = stm32_pinctrl_set_state_simple, +#endif /* PINCTRL_FULL */ }; static const struct udevice_id stm32_pinctrl_ids[] = { |