diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/clk_stm32f7.c | 100 | ||||
| -rw-r--r-- | drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 21 | ||||
| -rw-r--r-- | drivers/pinctrl/meson/pinctrl-meson.c | 167 | ||||
| -rw-r--r-- | drivers/pinctrl/meson/pinctrl-meson.h | 63 | ||||
| -rw-r--r-- | drivers/ram/stm32_sdram.c | 338 | ||||
| -rw-r--r-- | drivers/serial/serial_stm32x7.c | 18 | ||||
| -rw-r--r-- | drivers/serial/serial_stm32x7.h | 5 | ||||
| -rw-r--r-- | drivers/spi/stm32_qspi.c | 10 |
8 files changed, 603 insertions, 119 deletions
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index fcdc3c052b..255a583c95 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -12,6 +12,8 @@ #include <asm/arch/stm32.h> #include <asm/arch/stm32_periph.h> +#include <dt-bindings/mfd/stm32f7-rcc.h> + #define RCC_CR_HSION BIT(0) #define RCC_CR_HSEON BIT(16) #define RCC_CR_HSERDY BIT(17) @@ -83,6 +85,10 @@ struct pll_psc { #define APB_PSC_8 0x6 #define APB_PSC_16 0x7 +struct stm32_clk { + struct stm32_rcc_regs *base; +}; + #if !defined(CONFIG_STM32_HSE_HZ) #error "CONFIG_STM32_HSE_HZ not defined!" #else @@ -104,23 +110,26 @@ struct pll_psc sys_pll_psc = { #endif #endif -int configure_clocks(void) +static int configure_clocks(struct udevice *dev) { + struct stm32_clk *priv = dev_get_priv(dev); + struct stm32_rcc_regs *regs = priv->base; + /* Reset RCC configuration */ - setbits_le32(&STM32_RCC->cr, RCC_CR_HSION); - writel(0, &STM32_RCC->cfgr); /* Reset CFGR */ - clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON + setbits_le32(®s->cr, RCC_CR_HSION); + writel(0, ®s->cfgr); /* Reset CFGR */ + clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON)); - writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */ - clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP); - writel(0, &STM32_RCC->cir); /* Disable all interrupts */ + writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */ + clrbits_le32(®s->cr, RCC_CR_HSEBYP); + writel(0, ®s->cir); /* Disable all interrupts */ /* Configure for HSE+PLL operation */ - setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON); - while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) + setbits_le32(®s->cr, RCC_CR_HSEON); + while (!(readl(®s->cr) & RCC_CR_HSERDY)) ; - setbits_le32(&STM32_RCC->cfgr, (( + setbits_le32(®s->cfgr, (( sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); @@ -132,15 +141,15 @@ int configure_clocks(void) pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT; pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT; pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT; - writel(pllcfgr, &STM32_RCC->pllcfgr); + writel(pllcfgr, ®s->pllcfgr); /* Enable the main PLL */ - setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON); - while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) + setbits_le32(®s->cr, RCC_CR_PLLON); + while (!(readl(®s->cr) & RCC_CR_PLLRDY)) ; /* Enable high performance mode, System frequency up to 200 MHz */ - setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); + setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN); /* Infinite wait! */ while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY)) @@ -152,18 +161,20 @@ int configure_clocks(void) ; stm32_flash_latency_cfg(5); - clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); - setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); + clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); + setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL); - while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) != + while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) ; return 0; } -unsigned long clock_get(enum clock clck) +static unsigned long stm32_clk_get_rate(struct clk *clk) { + struct stm32_clk *priv = dev_get_priv(clk->dev); + struct stm32_rcc_regs *regs = priv->base; u32 sysclk = 0; u32 shift = 0; /* Prescaler table lookups for clock computation */ @@ -174,53 +185,61 @@ unsigned long clock_get(enum clock clck) 0, 0, 0, 0, 1, 2, 3, 4 }; - if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) == + if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL) { u16 pllm, plln, pllp; - pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); - plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) + pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); + plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) >> RCC_PLLCFGR_PLLN_SHIFT); - pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) + pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; + } else { + return -EINVAL; } - switch (clck) { - case CLOCK_CORE: - return sysclk; - break; - case CLOCK_AHB: + switch (clk->id) { + /* + * AHB CLOCK: 3 x 32 bits consecutive registers are used : + * AHB1, AHB2 and AHB3 + */ + case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI): shift = ahb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) + (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK) >> RCC_CFGR_HPRE_SHIFT)]; return sysclk >>= shift; break; - case CLOCK_APB1: + /* APB1 CLOCK */ + case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8): shift = apb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK) + (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK) >> RCC_CFGR_PPRE1_SHIFT)]; return sysclk >>= shift; break; - case CLOCK_APB2: + /* APB2 CLOCK */ + case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): shift = apb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK) + (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK) >> RCC_CFGR_PPRE2_SHIFT)]; return sysclk >>= shift; break; default: - return 0; + error("clock index %ld out of range\n", clk->id); + return -EINVAL; break; } } static int stm32_clk_enable(struct clk *clk) { + struct stm32_clk *priv = dev_get_priv(clk->dev); + struct stm32_rcc_regs *regs = priv->base; u32 offset = clk->id / 32; u32 bit_index = clk->id % 32; debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", __func__, clk->id, offset, bit_index); - setbits_le32(&STM32_RCC->ahb1enr + offset, BIT(bit_index)); + setbits_le32(®s->ahb1enr + offset, BIT(bit_index)); return 0; } @@ -247,7 +266,17 @@ void clock_setup(int peripheral) static int stm32_clk_probe(struct udevice *dev) { debug("%s: stm32_clk_probe\n", __func__); - configure_clocks(); + + struct stm32_clk *priv = dev_get_priv(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = (struct stm32_rcc_regs *)addr; + + configure_clocks(dev); return 0; } @@ -272,6 +301,7 @@ static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) static struct clk_ops stm32_clk_ops = { .of_xlate = stm32_clk_of_xlate, .enable = stm32_clk_enable, + .get_rate = stm32_clk_get_rate, }; static const struct udevice_id stm32_clk_ids[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 2fa840c21a..87c9912c02 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -391,14 +391,33 @@ static struct meson_pmx_func meson_gxbb_aobus_functions[] = { FUNCTION(i2c_slave_ao), }; +static struct meson_bank meson_gxbb_periphs_banks[] = { + /* name first last pullen pull dir out in */ + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_16, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_3, EE_OFF), 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_17, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_3, EE_OFF), 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), +}; + +static struct meson_bank meson_gxbb_aobus_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), +}; + struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { .name = "periphs-banks", .pin_base = 14, .groups = meson_gxbb_periphs_groups, .funcs = meson_gxbb_periphs_functions, + .banks = meson_gxbb_periphs_banks, .num_pins = 120, .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions), + .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), }; struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { @@ -406,9 +425,11 @@ struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { .pin_base = 0, .groups = meson_gxbb_aobus_groups, .funcs = meson_gxbb_aobus_functions, + .banks = meson_gxbb_aobus_banks, .num_pins = 14, .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions), + .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), }; static const struct udevice_id meson_gxbb_pinctrl_match[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 6281f529ea..a860200dfb 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -6,11 +6,14 @@ #include <common.h> #include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> #include <dm/pinctrl.h> #include <fdt_support.h> #include <linux/err.h> #include <linux/io.h> #include <linux/sizes.h> +#include <asm/gpio.h> #include "pinctrl-meson.h" @@ -117,6 +120,143 @@ const struct pinctrl_ops meson_pinctrl_ops = { .set_state = pinctrl_generic_set_state, }; +static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset, + enum meson_reg_type reg_type, + unsigned int *reg, unsigned int *bit) +{ + struct meson_pinctrl *priv = dev_get_priv(dev->parent); + struct meson_bank *bank = NULL; + struct meson_reg_desc *desc; + unsigned int pin; + int i; + + pin = priv->data->pin_base + offset; + + for (i = 0; i < priv->data->num_banks; i++) { + if (pin >= priv->data->banks[i].first && + pin <= priv->data->banks[i].last) { + bank = &priv->data->banks[i]; + break; + } + } + + if (!bank) + return -EINVAL; + + desc = &bank->regs[reg_type]; + *reg = desc->reg * 4; + *bit = desc->bit + pin - bank->first; + + return 0; +} + +static int meson_gpio_get(struct udevice *dev, unsigned int offset) +{ + struct meson_pinctrl *priv = dev_get_priv(dev->parent); + unsigned int reg, bit; + int ret; + + ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_IN, ®, &bit); + if (ret) + return ret; + + return !!(readl(priv->reg_gpio + reg) & BIT(bit)); +} + +static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value) +{ + struct meson_pinctrl *priv = dev_get_priv(dev->parent); + unsigned int reg, bit; + int ret; + + ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit); + if (ret) + return ret; + + clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0); + + return 0; +} + +static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset) +{ + struct meson_pinctrl *priv = dev_get_priv(dev->parent); + unsigned int reg, bit, val; + int ret; + + ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit); + if (ret) + return ret; + + val = readl(priv->reg_gpio + reg); + + return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT; +} + +static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct meson_pinctrl *priv = dev_get_priv(dev->parent); + unsigned int reg, bit; + int ret; + + ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit); + if (ret) + return ret; + + clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 1); + + return 0; +} + +static int meson_gpio_direction_output(struct udevice *dev, + unsigned int offset, int value) +{ + struct meson_pinctrl *priv = dev_get_priv(dev->parent); + unsigned int reg, bit; + int ret; + + ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit); + if (ret) + return ret; + + clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 0); + + ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit); + if (ret) + return ret; + + clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0); + + return 0; +} + +static int meson_gpio_probe(struct udevice *dev) +{ + struct meson_pinctrl *priv = dev_get_priv(dev->parent); + struct gpio_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + uc_priv->bank_name = priv->data->name; + uc_priv->gpio_count = priv->data->num_pins; + + return 0; +} + +static const struct dm_gpio_ops meson_gpio_ops = { + .set_value = meson_gpio_set, + .get_value = meson_gpio_get, + .get_function = meson_gpio_get_direction, + .direction_input = meson_gpio_direction_input, + .direction_output = meson_gpio_direction_output, +}; + +static struct driver meson_gpio_driver = { + .name = "meson-gpio", + .id = UCLASS_GPIO, + .probe = meson_gpio_probe, + .ops = &meson_gpio_ops, +}; + static fdt_addr_t parse_address(int offset, const char *name, int na, int ns) { int index, len = 0; @@ -138,9 +278,12 @@ static fdt_addr_t parse_address(int offset, const char *name, int na, int ns) int meson_pinctrl_probe(struct udevice *dev) { struct meson_pinctrl *priv = dev_get_priv(dev); + struct uclass_driver *drv; + struct udevice *gpio_dev; fdt_addr_t addr; int node, gpio = -1, len; int na, ns; + char *name; na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent)); if (na < 1) { @@ -168,12 +311,32 @@ int meson_pinctrl_probe(struct udevice *dev) addr = parse_address(gpio, "mux", na, ns); if (addr == FDT_ADDR_T_NONE) { - debug("mux not found\n"); + debug("mux address not found\n"); return -EINVAL; } - priv->reg_mux = (void __iomem *)addr; + + addr = parse_address(gpio, "gpio", na, ns); + if (addr == FDT_ADDR_T_NONE) { + debug("gpio address not found\n"); + return -EINVAL; + } + priv->reg_gpio = (void __iomem *)addr; priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev); + /* Lookup GPIO driver */ + drv = lists_uclass_lookup(UCLASS_GPIO); + if (!drv) { + puts("Cannot find GPIO driver\n"); + return -ENOENT; + } + + name = calloc(1, 32); + sprintf(name, "meson-gpio"); + + /* Create child device UCLASS_GPIO and bind it */ + device_bind(dev, &meson_gpio_driver, name, NULL, gpio, &gpio_dev); + dev_set_of_offset(gpio_dev, gpio); + return 0; } diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index 4127a60f48..90d2369842 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -28,15 +28,64 @@ struct meson_pinctrl_data { const char *name; struct meson_pmx_group *groups; struct meson_pmx_func *funcs; + struct meson_bank *banks; unsigned int pin_base; unsigned int num_pins; unsigned int num_groups; unsigned int num_funcs; + unsigned int num_banks; }; struct meson_pinctrl { struct meson_pinctrl_data *data; void __iomem *reg_mux; + void __iomem *reg_gpio; +}; + +/** + * struct meson_reg_desc - a register descriptor + * + * @reg: register offset in the regmap + * @bit: bit index in register + * + * The structure describes the information needed to control pull, + * pull-enable, direction, etc. for a single pin + */ +struct meson_reg_desc { + unsigned int reg; + unsigned int bit; +}; + +/** + * enum meson_reg_type - type of registers encoded in @meson_reg_desc + */ +enum meson_reg_type { + REG_PULLEN, + REG_PULL, + REG_DIR, + REG_OUT, + REG_IN, + NUM_REG, +}; + +/** + * struct meson bank + * + * @name: bank name + * @first: first pin of the bank + * @last: last pin of the bank + * @regs: array of register descriptors + * + * A bank represents a set of pins controlled by a contiguous set of + * bits in the domain registers. The structure specifies which bits in + * the regmap control the different functionalities. Each member of + * the @regs array refers to the first pin of the bank. + */ +struct meson_bank { + const char *name; + unsigned int first; + unsigned int last; + struct meson_reg_desc regs[NUM_REG]; }; #define PIN(x, b) (b + x) @@ -65,6 +114,20 @@ struct meson_pinctrl { .num_groups = ARRAY_SIZE(fn ## _groups), \ } +#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ + { \ + .name = n, \ + .first = f, \ + .last = l, \ + .regs = { \ + [REG_PULLEN] = { per, peb }, \ + [REG_PULL] = { pr, pb }, \ + [REG_DIR] = { dr, db }, \ + [REG_OUT] = { or, ob }, \ + [REG_IN] = { ir, ib }, \ + }, \ + } + #define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x) extern const struct pinctrl_ops meson_pinctrl_ops; diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 902de2b6c4..b1b0289a1b 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -10,11 +10,99 @@ #include <dm.h> #include <ram.h> #include <asm/io.h> -#include <asm/arch/fmc.h> -#include <asm/arch/stm32.h> DECLARE_GLOBAL_DATA_PTR; +struct stm32_fmc_regs { + /* 0x0 */ + u32 bcr1; /* NOR/PSRAM Chip select control register 1 */ + u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */ + u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */ + u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */ + u32 bcr3; /* NOR/PSRAMChip select Control register 3 */ + u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */ + u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */ + u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */ + u32 reserved1[24]; + + /* 0x80 */ + u32 pcr; /* NAND Flash control register */ + u32 sr; /* FIFO status and interrupt register */ + u32 pmem; /* Common memory space timing register */ + u32 patt; /* Attribute memory space timing registers */ + u32 reserved2[1]; + u32 eccr; /* ECC result registers */ + u32 reserved3[27]; + + /* 0x104 */ + u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */ + u32 reserved4[1]; + u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */ + u32 reserved5[1]; + u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */ + u32 reserved6[1]; + u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */ + u32 reserved7[8]; + + /* 0x140 */ + u32 sdcr1; /* SDRAM Control register 1 */ + u32 sdcr2; /* SDRAM Control register 2 */ + u32 sdtr1; /* SDRAM Timing register 1 */ + u32 sdtr2; /* SDRAM Timing register 2 */ + u32 sdcmr; /* SDRAM Mode register */ + u32 sdrtr; /* SDRAM Refresh timing register */ + u32 sdsr; /* SDRAM Status register */ +}; + +/* + * NOR/PSRAM Control register BCR1 + * FMC controller Enable, only availabe for H7 + */ +#define FMC_BCR1_FMCEN BIT(31) + +/* Control register SDCR */ +#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ +#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ +#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ +#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ +#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ +#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ +#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ +#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ +#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ + +/* Timings register SDTR */ +#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ +#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ +#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ +#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ +#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ +#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ +#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ + +#define FMC_SDCMR_NRFS_SHIFT 5 + +#define FMC_SDCMR_MODE_NORMAL 0 +#define FMC_SDCMR_MODE_START_CLOCK 1 +#define FMC_SDCMR_MODE_PRECHARGE 2 +#define FMC_SDCMR_MODE_AUTOREFRESH 3 +#define FMC_SDCMR_MODE_WRITE_MODE 4 +#define FMC_SDCMR_MODE_SELFREFRESH 5 +#define FMC_SDCMR_MODE_POWERDOWN 6 + +#define FMC_SDCMR_BANK_1 BIT(4) +#define FMC_SDCMR_BANK_2 BIT(3) + +#define FMC_SDCMR_MODE_REGISTER_SHIFT 9 + +#define FMC_SDSR_BUSY BIT(5) + +#define FMC_BUSY_WAIT(regs) do { \ + __asm__ __volatile__ ("dsb" : : : "memory"); \ + while (regs->sdsr & FMC_SDSR_BUSY) \ + ; \ + } while (0) + struct stm32_sdram_control { u8 no_columns; u8 no_rows; @@ -35,11 +123,29 @@ struct stm32_sdram_timing { u8 twr; u8 trcd; }; +enum stm32_fmc_bank { + SDRAM_BANK1, + SDRAM_BANK2, + MAX_SDRAM_BANK, +}; + +enum stm32_fmc_family { + STM32F7_FMC, + STM32H7_FMC, +}; + +struct bank_params { + struct stm32_sdram_control *sdram_control; + struct stm32_sdram_timing *sdram_timing; + u32 sdram_ref_count; + enum stm32_fmc_bank target_bank; +}; + struct stm32_sdram_params { + struct stm32_fmc_regs *base; u8 no_sdram_banks; - struct stm32_sdram_control sdram_control; - struct stm32_sdram_timing sdram_timing; - u32 sdram_ref_count; + struct bank_params bank_params[MAX_SDRAM_BANK]; + enum stm32_fmc_family family; }; #define SDRAM_MODE_BL_SHIFT 0 @@ -49,90 +155,179 @@ struct stm32_sdram_params { int stm32_sdram_init(struct udevice *dev) { struct stm32_sdram_params *params = dev_get_platdata(dev); + struct stm32_sdram_control *control; + struct stm32_sdram_timing *timing; + struct stm32_fmc_regs *regs = params->base; + enum stm32_fmc_bank target_bank; + u32 ctb; /* SDCMR register: Command Target Bank */ + u32 ref_count; + u8 i; + + /* disable the FMC controller */ + if (params->family == STM32H7_FMC) + clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN); + + for (i = 0; i < params->no_sdram_banks; i++) { + control = params->bank_params[i].sdram_control; + timing = params->bank_params[i].sdram_timing; + target_bank = params->bank_params[i].target_bank; + ref_count = params->bank_params[i].sdram_ref_count; + + writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT + | control->cas_latency << FMC_SDCR_CAS_SHIFT + | control->no_banks << FMC_SDCR_NB_SHIFT + | control->memory_width << FMC_SDCR_MWID_SHIFT + | control->no_rows << FMC_SDCR_NR_SHIFT + | control->no_columns << FMC_SDCR_NC_SHIFT + | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT + | control->rd_burst << FMC_SDCR_RBURST_SHIFT, + ®s->sdcr1); + + if (target_bank == SDRAM_BANK2) + writel(control->cas_latency << FMC_SDCR_CAS_SHIFT + | control->no_banks << FMC_SDCR_NB_SHIFT + | control->memory_width << FMC_SDCR_MWID_SHIFT + | control->no_rows << FMC_SDCR_NR_SHIFT + | control->no_columns << FMC_SDCR_NC_SHIFT, + ®s->sdcr2); - writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT - | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT - | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT - | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT - | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT - | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT - | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT - | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, - &STM32_SDRAM_FMC->sdcr1); - - writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT - | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT - | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT - | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT - | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT - | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT - | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT, - &STM32_SDRAM_FMC->sdtr1); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, - &STM32_SDRAM_FMC->sdcmr); - udelay(200); /* 200 us delay, page 10, "Power-Up" */ - FMC_BUSY_WAIT(); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, - &STM32_SDRAM_FMC->sdcmr); - udelay(100); - FMC_BUSY_WAIT(); - - writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH - | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); - udelay(100); - FMC_BUSY_WAIT(); - - writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT - | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT) - << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, - &STM32_SDRAM_FMC->sdcmr); - udelay(100); - FMC_BUSY_WAIT(); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, - &STM32_SDRAM_FMC->sdcmr); - FMC_BUSY_WAIT(); - - /* Refresh timer */ - writel((params->sdram_ref_count) << 1, &STM32_SDRAM_FMC->sdrtr); + writel(timing->trcd << FMC_SDTR_TRCD_SHIFT + | timing->trp << FMC_SDTR_TRP_SHIFT + | timing->twr << FMC_SDTR_TWR_SHIFT + | timing->trc << FMC_SDTR_TRC_SHIFT + | timing->tras << FMC_SDTR_TRAS_SHIFT + | timing->txsr << FMC_SDTR_TXSR_SHIFT + | timing->tmrd << FMC_SDTR_TMRD_SHIFT, + ®s->sdtr1); + + if (target_bank == SDRAM_BANK2) + writel(timing->trcd << FMC_SDTR_TRCD_SHIFT + | timing->trp << FMC_SDTR_TRP_SHIFT + | timing->twr << FMC_SDTR_TWR_SHIFT + | timing->trc << FMC_SDTR_TRC_SHIFT + | timing->tras << FMC_SDTR_TRAS_SHIFT + | timing->txsr << FMC_SDTR_TXSR_SHIFT + | timing->tmrd << FMC_SDTR_TMRD_SHIFT, + ®s->sdtr2); + + if (target_bank == SDRAM_BANK1) + ctb = FMC_SDCMR_BANK_1; + else + ctb = FMC_SDCMR_BANK_2; + + writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr); + udelay(200); /* 200 us delay, page 10, "Power-Up" */ + FMC_BUSY_WAIT(regs); + + writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT), + ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT + | control->cas_latency << SDRAM_MODE_CAS_SHIFT) + << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, + ®s->sdcmr); + udelay(100); + FMC_BUSY_WAIT(regs); + + writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr); + FMC_BUSY_WAIT(regs); + + /* Refresh timer */ + writel(ref_count << 1, ®s->sdrtr); + } + + /* enable the FMC controller */ + if (params->family == STM32H7_FMC) + setbits_le32(®s->bcr1, FMC_BCR1_FMCEN); return 0; } static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) { - int ret; - int node = dev_of_offset(dev); - const void *blob = gd->fdt_blob; struct stm32_sdram_params *params = dev_get_platdata(dev); + struct bank_params *bank_params; + ofnode bank_node; + char *bank_name; + u8 bank = 0; - params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1); - debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + dev_for_each_subnode(bank_node, dev) { + /* extract the bank index from DT */ + bank_name = (char *)ofnode_get_name(bank_node); + strsep(&bank_name, "@"); + if (!bank_name) { + error("missing sdram bank index"); + return -EINVAL; + } + + bank_params = ¶ms->bank_params[bank]; + strict_strtoul(bank_name, 10, + (long unsigned int *)&bank_params->target_bank); + + if (bank_params->target_bank >= MAX_SDRAM_BANK) { + error("Found bank %d , but only bank 0 and 1 are supported", + bank_params->target_bank); + return -EINVAL; + } - fdt_for_each_subnode(node, blob, node) { - ret = fdtdec_get_byte_array(blob, node, "st,sdram-control", - (u8 *)¶ms->sdram_control, - sizeof(params->sdram_control)); - if (ret) - return ret; - ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing", - (u8 *)¶ms->sdram_timing, - sizeof(params->sdram_timing)); - if (ret) - return ret; - - params->sdram_ref_count = fdtdec_get_int(blob, node, + debug("Find bank %s %u\n", bank_name, bank_params->target_bank); + + params->bank_params[bank].sdram_control = + (struct stm32_sdram_control *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-control", + sizeof(struct stm32_sdram_control)); + + if (!params->bank_params[bank].sdram_control) { + error("st,sdram-control not found for %s", + ofnode_get_name(bank_node)); + return -EINVAL; + } + + + params->bank_params[bank].sdram_timing = + (struct stm32_sdram_timing *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-timing", + sizeof(struct stm32_sdram_timing)); + + if (!params->bank_params[bank].sdram_timing) { + error("st,sdram-timing not found for %s", + ofnode_get_name(bank_node)); + return -EINVAL; + } + + + bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, "st,sdram-refcount", 8196); + bank++; } + params->no_sdram_banks = bank; + debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + return 0; } static int stm32_fmc_probe(struct udevice *dev) { + struct stm32_sdram_params *params = dev_get_platdata(dev); int ret; + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + params->base = (struct stm32_fmc_regs *)addr; + params->family = dev_get_driver_data(dev); + #ifdef CONFIG_CLK struct clk clk; @@ -164,7 +359,8 @@ static struct ram_ops stm32_fmc_ops = { }; static const struct udevice_id stm32_fmc_ids[] = { - { .compatible = "st,stm32-fmc" }, + { .compatible = "st,stm32-fmc", .data = STM32F7_FMC }, + { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC }, { } }; diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c index 61e8167a3b..bf118a78cf 100644 --- a/drivers/serial/serial_stm32x7.c +++ b/drivers/serial/serial_stm32x7.c @@ -11,7 +11,6 @@ #include <asm/io.h> #include <serial.h> #include <asm/arch/stm32.h> -#include <dm/platform_data/serial_stm32x7.h> #include "serial_stm32x7.h" DECLARE_GLOBAL_DATA_PTR; @@ -20,16 +19,9 @@ static int stm32_serial_setbrg(struct udevice *dev, int baudrate) { struct stm32x7_serial_platdata *plat = dev->platdata; struct stm32_usart *const usart = plat->base; - u32 clock, int_div, mantissa, fraction, oversampling; + u32 int_div, mantissa, fraction, oversampling; - if (((u32)usart & STM32_BUS_MASK) == APB1_PERIPH_BASE) - clock = clock_get(CLOCK_APB1); - else if (((u32)usart & STM32_BUS_MASK) == APB2_PERIPH_BASE) - clock = clock_get(CLOCK_APB2); - else - return -EINVAL; - - int_div = DIV_ROUND_CLOSEST(clock, baudrate); + int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate); if (int_div < 16) { oversampling = 8; @@ -102,6 +94,12 @@ static int stm32_serial_probe(struct udevice *dev) } #endif + plat->clock_rate = clk_get_rate(&clk); + if (plat->clock_rate < 0) { + clk_disable(&clk); + return plat->clock_rate; + }; + /* Disable usart-> disable overrun-> enable usart */ clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); setbits_le32(&usart->cr3, USART_CR3_OVRDIS); diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h index facfdbabe8..9fe37af5cc 100644 --- a/drivers/serial/serial_stm32x7.h +++ b/drivers/serial/serial_stm32x7.h @@ -22,6 +22,11 @@ struct stm32_usart { u32 tx_dr; }; +/* Information about a serial port */ +struct stm32x7_serial_platdata { + struct stm32_usart *base; /* address of registers in physical memory */ + unsigned long int clock_rate; +}; #define USART_CR1_OVER8 (1 << 15) #define USART_CR1_TE (1 << 3) diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index f0434a4413..ef2b64ec5f 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -165,6 +165,7 @@ struct stm32_qspi_platdata { struct stm32_qspi_priv { struct stm32_qspi_regs *regs; + ulong clock_rate; u32 max_hz; u32 mode; @@ -471,6 +472,13 @@ static int stm32_qspi_probe(struct udevice *bus) dev_err(bus, "failed to enable clock\n"); return ret; } + + priv->clock_rate = clk_get_rate(&clk); + if (priv->clock_rate < 0) { + clk_disable(&clk); + return priv->clock_rate; + } + #endif setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); @@ -536,7 +544,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed) if (speed > plat->max_hz) speed = plat->max_hz; - u32 qspi_clk = clock_get(CLOCK_AHB); + u32 qspi_clk = priv->clock_rate; u32 prescaler = 255; if (speed > 0) { prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1; |