diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/altera/sdram_gen5.c | 12 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_s10.c | 6 | ||||
| -rw-r--r-- | drivers/fpga/socfpga_arria10.c | 7 | ||||
| -rw-r--r-- | drivers/fpga/socfpga_gen5.c | 4 | ||||
| -rw-r--r-- | drivers/mmc/socfpga_dw_mmc.c | 6 |
5 files changed, 13 insertions, 22 deletions
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 8c8ea19eb9..435f42bc0a 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -40,9 +40,6 @@ struct sdram_prot_rule { u32 hi_prot_id; }; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl); /** @@ -455,12 +452,14 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl, SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; int ret; - writel(rows, &sysmgr_regs->iswgrp_handoff[4]); + writel(rows, + socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(4)); sdr_load_regs(sdr_ctrl, cfg); /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ - writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); + writel(cfg->fpgaport_rst, + socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(3)); /* only enable if the FPGA is programmed */ if (fpgamgr_test_fpga_ready()) { @@ -516,7 +515,8 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) * since the FB specifies we modify ROWBITs to work around SDRAM * controller issue. */ - row = readl(&sysmgr_regs->iswgrp_handoff[4]); + row = readl(socfpga_get_sysmgr_addr() + + SYSMGR_ISWGRP_HANDOFF_OFFSET(4)); if (row == 0) row = rowbits; /* diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 82d9a13efa..5cf7d97592 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -33,9 +33,6 @@ struct altera_sdram_platdata { DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_system_manager *sysmgr_regs = - (void *)SOCFPGA_SYSMGR_ADDRESS; - #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) #define PGTABLE_OFF 0x4000 @@ -151,7 +148,8 @@ static int emif_reset(struct altera_sdram_platdata *plat) static int poll_hmc_clock_status(void) { - return wait_for_bit_le32(&sysmgr_regs->hmc_clk, + return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + + SYSMGR_S10_HMC_CLK), SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); } diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 5fb9d6a191..2853581b97 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -30,9 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_fpga_manager *fpga_manager_base = (void *)SOCFPGA_FPGAMGRREGS_ADDRESS; -static const struct socfpga_system_manager *system_manager_base = - (void *)SOCFPGA_SYSMGR_ADDRESS; - static void fpgamgr_set_cd_ratio(unsigned long ratio); static uint32_t fpgamgr_get_msel(void) @@ -818,7 +815,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, } /* Disable all signals from HPS peripheral controller to FPGA */ - writel(0, &system_manager_base->fpgaintf_en_global); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL); /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(); @@ -910,7 +907,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) memset(&rbfinfo, 0, sizeof(rbfinfo)); /* Disable all signals from hps peripheral controller to fpga */ - writel(0, &system_manager_base->fpgaintf_en_global); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL); /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(); diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c index 6d16e0b37f..d73474f29e 100644 --- a/drivers/fpga/socfpga_gen5.c +++ b/drivers/fpga/socfpga_gen5.c @@ -15,8 +15,6 @@ static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; /* Set CD ratio */ static void fpgamgr_set_cd_ratio(unsigned long ratio) @@ -214,7 +212,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Prior programming the FPGA, all bridges need to be shut off */ /* Disable all signals from hps peripheral controller to fpga */ - writel(0, &sysmgr_regs->fpgaintfgrp_module); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_FPGAINFGRP_MODULE); /* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 739c1629a2..df9e8ccb1e 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -20,8 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_clock_manager *clock_manager_base = (void *)SOCFPGA_CLKMGR_ADDRESS; -static const struct socfpga_system_manager *system_manager_base = - (void *)SOCFPGA_SYSMGR_ADDRESS; struct socfpga_dwmci_plat { struct mmc_config cfg; @@ -61,10 +59,10 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); - writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl); + writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC); debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, - readl(&system_manager_base->sdmmcgrp_ctrl)); + readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); /* Enable SDMMC clock */ setbits_le32(&clock_manager_base->per_pll.en, |