diff options
Diffstat (limited to 'drivers/ddr/marvell')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_debug.c | 1 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_init.c | 3 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training.c | 11 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c | 8 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_leveling.c | 3 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr_ml_wrapper.h | 2 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_plat.c | 9 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_plat.h | 2 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_spd.h | 8 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h | 22 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/xor.c | 2 | ||||
| -rw-r--r-- | drivers/ddr/marvell/axp/ddr3_dfs.c | 4 | ||||
| -rw-r--r-- | drivers/ddr/marvell/axp/ddr3_sdram.c | 2 | ||||
| -rw-r--r-- | drivers/ddr/marvell/axp/xor.c | 4 | ||||
| -rw-r--r-- | drivers/ddr/marvell/axp/xor.h | 4 |
15 files changed, 20 insertions, 65 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c index 22e0cc4d91..f5fc964d6f 100644 --- a/drivers/ddr/marvell/a38x/ddr3_debug.c +++ b/drivers/ddr/marvell/a38x/ddr3_debug.c @@ -6,7 +6,6 @@ #include "ddr3_init.h" #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" -#include <log.h> u8 is_reg_dump = 0; u8 debug_pbs = DEBUG_LEVEL_ERROR; diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c index 7488770268..f878b4512b 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.c +++ b/drivers/ddr/marvell/a38x/ddr3_init.c @@ -77,9 +77,6 @@ int ddr3_init(void) return status; } -#if defined(CONFIG_PHY_STATIC_PRINT) - mv_ddr_phy_static_print(); -#endif /* Post MC/PHY initializations */ mv_ddr_post_training_soc_config(ddr_type); diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 2b3af23202..2512b58cb7 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -7,8 +7,6 @@ #include "mv_ddr_common.h" #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" -#include <log.h> -#include <linux/delay.h> #define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask]) #define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num]) @@ -207,7 +205,6 @@ static int ddr3_tip_pad_inv(void) if (tm->interface_params[0].as_bus_params[sphy]. is_ck_swap == 1 && sphy == 0) { /* TODO: move this code to per platform one */ -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) /* clock swap for both cs0 and cs1 */ data = (INVERT_PAD << INV_PAD2_OFFS | INVERT_PAD << INV_PAD6_OFFS | @@ -219,9 +216,6 @@ static int ddr3_tip_pad_inv(void) DDR_PHY_CONTROL, PHY_CTRL_PHY_REG, data, data); -#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */ -#pragma message "unknown platform to configure ddr clock swap" -#endif } } @@ -2014,9 +2008,7 @@ int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2) static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) { /* TODO: enable this functionality for other platforms */ -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) struct init_cntr_param init_cntr_prm; -#endif int ret = MV_OK; int adll_bypass_flag = 0; u32 if_id; @@ -2050,7 +2042,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) } /* TODO: enable this functionality for other platforms */ -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) if (is_adll_calib_before_init != 0) { DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("with adll calib before init\n")); @@ -2081,7 +2072,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) return MV_FAIL; } } -#endif ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq); if (ret != MV_OK) { @@ -2905,3 +2895,4 @@ unsigned int mv_ddr_misl_phy_odt_n_get(void) return odt_n; } + diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c index 5fd9a052fa..102f9bd633 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c @@ -6,8 +6,6 @@ #include "ddr3_init.h" #include "mv_ddr_regs.h" #include "ddr_training_ip_db.h" -#include <image.h> -#include <linux/delay.h> #define PATTERN_1 0x55555555 #define PATTERN_2 0xaaaaaaaa @@ -614,9 +612,9 @@ int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type, MASK_ALL_BITS)); } - CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, - ODPG_DATA_BUFFER_OFFS_REG, - load_addr, MASK_ALL_BITS)); + CHECK_STATUS(ddr3_tip_if_write + (dev_num, access_type, if_id, + ODPG_DATA_BUFFER_OFFS_REG, load_addr, MASK_ALL_BITS)); return MV_OK; } diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c index dadb06b318..6523281f2b 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c @@ -7,7 +7,6 @@ #include "mv_ddr_training_db.h" #include "ddr_training_ip_db.h" #include "mv_ddr_regs.h" -#include <linux/delay.h> #define WL_ITERATION_NUM 10 @@ -916,10 +915,8 @@ int ddr3_tip_dynamic_write_leveling(u32 dev_num, int phase_remove) DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("training done failed\n")); } else { /* check for training pass */ reg_data = data_read[0]; -#if defined(CONFIG_ARMADA_38X) /* JIRA #1498 for 16 bit with ECC */ if (tm->bus_act_mask == 0xb) /* set to data to 0 to skip the check */ reg_data = 0; -#endif if (reg_data != PASS) DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("training result failed\n")); diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h index ac9250f74e..7357311965 100644 --- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h +++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h @@ -13,9 +13,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) #define INTER_REGS_BASE SOC_REGS_PHY_BASE -#endif /* * MV_DEBUG_INIT need to be defines, otherwise the output of the diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 0d1df189e8..faafc86ea2 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -8,7 +8,6 @@ #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" #include "mv_ddr_sys_env_lib.h" -#include <linux/delay.h> #define DDR_INTERFACES_NUM 1 #define DDR_INTERFACE_OCTETS_NUM 5 @@ -560,11 +559,7 @@ static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum mv_ddr_freq *freq) static int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr) { -#if defined(CONFIG_ARMADA_39X) - info_ptr->device_id = 0x6900; -#else info_ptr->device_id = 0x6800; -#endif info_ptr->ck_delay = ck_delay; return MV_OK; @@ -667,11 +662,7 @@ static int mv_ddr_sw_db_init(u32 dev_num, u32 board_id) ddr3_tip_dev_attr_set(dev_num, MV_ATTR_TIP_REV, MV_TIP_REV_4); ddr3_tip_dev_attr_set(dev_num, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_POSITIVE); ddr3_tip_dev_attr_set(dev_num, MV_ATTR_OCTET_PER_INTERFACE, DDR_INTERFACE_OCTETS_NUM); -#ifdef CONFIG_ARMADA_39X - ddr3_tip_dev_attr_set(dev_num, MV_ATTR_INTERLEAVE_WA, 1); -#else ddr3_tip_dev_attr_set(dev_num, MV_ATTR_INTERLEAVE_WA, 0); -#endif ca_delay = 0; delay_enable = 1; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h index 281d4c2301..44998847c2 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h @@ -6,6 +6,8 @@ #ifndef _MV_DDR_PLAT_H #define _MV_DDR_PLAT_H +#include <linux/delay.h> + #define MAX_DEVICE_NUM 1 #define MAX_INTERFACE_NUM 1 #define MAX_BUS_NUM 5 diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h index b4bfef3103..6043f11b28 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h @@ -40,7 +40,10 @@ */ union mv_ddr_spd_data { unsigned char all_bytes[MV_DDR_SPD_DATA_BLOCK0_SIZE + - MV_DDR_SPD_DATA_BLOCK1M_SIZE]; + MV_DDR_SPD_DATA_BLOCK1M_SIZE + + MV_DDR_SPD_DATA_BLOCK1H_SIZE + + MV_DDR_SPD_DATA_BLOCK2E_SIZE + + MV_DDR_SPD_DATA_BLOCK2M_SIZE]; struct { /* block 0 */ union { /* num of bytes used/num of bytes in spd device/crc coverage */ @@ -271,6 +274,9 @@ union mv_ddr_spd_data { } bit_fields; } byte_131; unsigned char bytes_132_191[60]; /* reserved; all 0s */ + unsigned char bytes_192_255[MV_DDR_SPD_DATA_BLOCK1H_SIZE]; + unsigned char bytes_256_319[MV_DDR_SPD_DATA_BLOCK2E_SIZE]; + unsigned char bytes_320_383[MV_DDR_SPD_DATA_BLOCK2M_SIZE]; } byte_fields; }; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h b/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h index dc6977c334..10b0d45b35 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h @@ -78,22 +78,7 @@ enum suspend_wakeup_status { * set '-2' * If suspend to RAM is not supported set '-1' */ -#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT -#ifdef CONFIG_ARMADA_38X -#define MV_BOARD_WAKEUP_GPIO_INFO { \ - {A38X_CUSTOMER_BOARD_ID0, -1 }, \ - {A38X_CUSTOMER_BOARD_ID0, -1 }, \ -}; -#else -#define MV_BOARD_WAKEUP_GPIO_INFO { \ - {A39X_CUSTOMER_BOARD_ID0, -1 }, \ - {A39X_CUSTOMER_BOARD_ID0, -1 }, \ -}; -#endif /* CONFIG_ARMADA_38X */ - -#else -#ifdef CONFIG_ARMADA_38X #define MV_BOARD_WAKEUP_GPIO_INFO { \ {RD_NAS_68XX_ID, -2 }, \ {DB_68XX_ID, -1 }, \ @@ -103,13 +88,6 @@ enum suspend_wakeup_status { {DB_BP_6821_ID, -2 }, \ {DB_AMC_6820_ID, -2 }, \ }; -#else -#define MV_BOARD_WAKEUP_GPIO_INFO { \ - {A39X_RD_69XX_ID, -1 }, \ - {A39X_DB_69XX_ID, -1 }, \ -}; -#endif /* CONFIG_ARMADA_38X */ -#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ enum suspend_wakeup_status mv_ddr_sys_env_suspend_wakeup_check(void); u32 mv_ddr_sys_env_get_cs_ena_from_reg(void); diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c index 98fb39eaf0..7bc6268293 100644 --- a/drivers/ddr/marvell/a38x/xor.c +++ b/drivers/ddr/marvell/a38x/xor.c @@ -347,10 +347,8 @@ void ddr3_new_tip_ecc_scrub(void) for (cs_c = 0; cs_c < max_cs; cs_c++) cs_ena |= 1 << cs_c; -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) /* all chip-selects are of same size */ ddr3_calc_mem_cs_size(0, &cs_mem_size_mb); -#endif cs_mem_size = cs_mem_size_mb * _1M; mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); total_mem_size = max_cs * cs_mem_size; diff --git a/drivers/ddr/marvell/axp/ddr3_dfs.c b/drivers/ddr/marvell/axp/ddr3_dfs.c index b58c0fe01e..2a4596680b 100644 --- a/drivers/ddr/marvell/axp/ddr3_dfs.c +++ b/drivers/ddr/marvell/axp/ddr3_dfs.c @@ -42,8 +42,8 @@ extern u8 div_ratio[CLK_VCO][CLK_DDR]; extern void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps); #else extern u16 odt_dynamic[ODT_OPT][MAX_CS]; -extern u8 div_ratio1to1[CLK_CPU][CLK_DDR]; -extern u8 div_ratio2to1[CLK_CPU][CLK_DDR]; +extern u8 div_ratio1to1[CLK_VCO][CLK_DDR]; +extern u8 div_ratio2to1[CLK_VCO][CLK_DDR]; #endif extern u16 odt_static[ODT_OPT][MAX_CS]; diff --git a/drivers/ddr/marvell/axp/ddr3_sdram.c b/drivers/ddr/marvell/axp/ddr3_sdram.c index 3a266c6de4..0b150b20f3 100644 --- a/drivers/ddr/marvell/axp/ddr3_sdram.c +++ b/drivers/ddr/marvell/axp/ddr3_sdram.c @@ -21,7 +21,7 @@ extern u32 pbs_pattern_32b[2][LEN_PBS_PATTERN]; #if defined(MV88F78X60) extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN]; #endif -extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM]; +extern u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM]; #if defined(MV88F78X60) || defined(MV88F672X) /* PBS locked dq (per pup) */ diff --git a/drivers/ddr/marvell/axp/xor.c b/drivers/ddr/marvell/axp/xor.c index 17bfe6a7bf..76aea96682 100644 --- a/drivers/ddr/marvell/axp/xor.c +++ b/drivers/ddr/marvell/axp/xor.c @@ -152,8 +152,8 @@ static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl) return MV_OK; } -int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high, - u32 init_val_low) +int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long block_size, + u32 init_val_high, u32 init_val_low) { u32 tmp; diff --git a/drivers/ddr/marvell/axp/xor.h b/drivers/ddr/marvell/axp/xor.h index 97d1056432..a7c6ae840c 100644 --- a/drivers/ddr/marvell/axp/xor.h +++ b/drivers/ddr/marvell/axp/xor.h @@ -64,7 +64,7 @@ int mv_xor_state_get(u32 chan); void mv_sys_xor_init(MV_DRAM_INFO *dram_info); void mv_sys_xor_finish(void); int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr); -int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high, - u32 init_val_low); +int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long block_size, + u32 init_val_high, u32 init_val_low); #endif /* __XOR_H */ |