diff options
Diffstat (limited to 'drivers/clk/rockchip/clk_rk3399.c')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3399.c | 27 |
1 files changed, 16 insertions, 11 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 53d2a3f85d..3edafea140 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -676,8 +676,8 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) const struct spi_clkreg *spiclk = NULL; int src_clk_div; - src_clk_div = RATE_TO_DIV(GPLL_HZ, hz); - assert(src_clk_div < 127); + src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; + assert(src_clk_div < 128); switch (clk_id) { case SCLK_SPI1 ... SCLK_SPI5: @@ -750,18 +750,21 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) case HCLK_SDMMC: case SCLK_SDMMC: con = readl(&cru->clksel_con[16]); + /* dwmmc controller have internal div 2 */ + div = 2; break; case SCLK_EMMC: con = readl(&cru->clksel_con[21]); + div = 1; break; default: return -EINVAL; } - div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; + div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT == CLK_EMMC_PLL_SEL_24M) - return DIV_TO_RATE(24*1000*1000, div); + return DIV_TO_RATE(OSC_HZ, div); else return DIV_TO_RATE(GPLL_HZ, div); } @@ -776,11 +779,13 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, case HCLK_SDMMC: case SCLK_SDMMC: /* Select clk_sdmmc source from GPLL by default */ - src_clk_div = GPLL_HZ / set_rate; + /* mmc clock defaulg div 2 internal, provide double in cru */ + src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); - if (src_clk_div > 127) { + if (src_clk_div > 128) { /* use 24MHz source for 400KHz clock */ - src_clk_div = 24*1000*1000 / set_rate; + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); + assert(src_clk_div - 1 < 128); rk_clrsetreg(&cru->clksel_con[16], CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | @@ -794,8 +799,8 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, break; case SCLK_EMMC: /* Select aclk_emmc source from GPLL */ - src_clk_div = GPLL_HZ / aclk_emmc; - assert(src_clk_div - 1 < 31); + src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); + assert(src_clk_div - 1 < 32); rk_clrsetreg(&cru->clksel_con[21], ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, @@ -803,8 +808,8 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); /* Select clk_emmc source from GPLL too */ - src_clk_div = GPLL_HZ / set_rate; - assert(src_clk_div - 1 < 127); + src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); + assert(src_clk_div - 1 < 128); rk_clrsetreg(&cru->clksel_con[22], CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, |