diff options
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.AMCC-eval-boards-cleanup | 31 | ||||
| -rw-r--r-- | doc/README.PlanetCore | 163 | ||||
| -rw-r--r-- | doc/README.mpc83xxads | 98 | ||||
| -rw-r--r-- | doc/README.mpc85xxads | 10 | ||||
| -rw-r--r-- | doc/README.mpc85xxcds | 43 | ||||
| -rw-r--r-- | doc/README.stxxtc | 59 |
6 files changed, 397 insertions, 7 deletions
diff --git a/doc/README.AMCC-eval-boards-cleanup b/doc/README.AMCC-eval-boards-cleanup new file mode 100644 index 0000000000..901bd875c6 --- /dev/null +++ b/doc/README.AMCC-eval-boards-cleanup @@ -0,0 +1,31 @@ +--------------------------------------------------------------------- +Cleanup of AMCC eval boards (Walnut/Sycamore, Bubinga, Ebony, Ocotea) +--------------------------------------------------------------------- + +Changes to all AMCC eval boards: +-------------------------------- + +o Changed u-boot image size to 256 kBytes instead of 512 kBytes on most + boards. + +o Use 115200 baud as default console baudrate. + +o Added config option to use redundant environment in flash. This is also + the default setting. Option for environment in nvram is still available + for backward compatibility. + +o Merged board specific flash drivers to common flash driver: + board/amcc/common/flash.c + + +Sycamore/Walnut (one port supporting both eval boards): +------------------------------------------------------- + +o Cleanup to allow easier "cloning" for different (custom) boards: + + o Moved EBC configuration from board specific asm-file "init.S" + using defines in board configuration file. No board specific + asm file needed anymore. + + +August 01 2005, Stefan Roese <sr@denx.de> diff --git a/doc/README.PlanetCore b/doc/README.PlanetCore new file mode 100644 index 0000000000..b73c5f5a87 --- /dev/null +++ b/doc/README.PlanetCore @@ -0,0 +1,163 @@ +After several heart-struck failure, I got one workable way to program +each other in FLASH between PlanetCore and U-Boot. + +Hardware Platform : RPXlite DW(EP 823 H1 DW) + +1. From U-Boot to PlanetCore + +Utilities : PlanetCore Boot Loader - PCL200.mot + +[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot +PCL200.mot pcl200.bin + +[Target Operation] +u-boot>t 100000 pcl200.bin +u-boot>go 0x100000 +## Starting application at 0x00100000 ... + +MPC8xx PlanetCore Flash Burner v2.00 +Copyright 2001 Embedded Planet. All rights reserved. + +Construct Flash Device.....done. + + +Program MPC8xx PlanetCore Boot Loader v2.00 +Built Sep 19, 2001 at 14:34:42 +Image located from FC000000 to FC01B5D1. +(Skipping an image, only loading low boot image) + +Low boot board detected, skipping high boot image. +Erasing, programming and verifying will start in 20 +seconds +Press P to start immediately or ESC to cancel +Press Space or Enter for more options. +.............. + +Erasing +Programming +FLASH programmed successfully! +Press R to induce a hard reset + +MPC8xx PlanetCore Boot Loader v2.00 +Copyright 2001 Embedded Planet. All rights reserved. +DRAM available size = 64 MB +wvCV +DRAM OK +> + +2. From PlanetCore to U-Boot + +Utilities : PlanetCore FLASH Burner - PCB200.mot + +Use Flash Burner to finish the work: + +First, TFTP the U-Boot image file to RAM; For example, +RPXlite_DW.bin to 0x400000 +Second, TFTP FLASH Burner to RAM; For example, +0x100000 +Third, run the FLASH Burner and Program the U-Boot +image into the correct location in FLASH. + +[Target Operation] +MPC8xx PlanetCore Boot Loader v2.00 +Copyright 2001 Embedded Planet. All rights reserved. +DRAM available size = 64 MB +wvCV +DRAM OK +>t +Load using tftp via Ethernet +Enter server IP address <172.16.115.6> : +Enter server filename <PCL200.mot> : RPXlite_DW.bin +Enter (B)inary or (S)record input mode <S> : B +Enter address offset : <00400000 hex> : + +Total bytes = 120096 in 232184 uSecs +Loaded addresses 00400000 through 0041D51F. +Start address = 00400000 +>t +Load using tftp via Ethernet +Enter server IP address <172.16.115.6> : +Enter server filename <RPXlite_DW.bin> : PCB200.mot +Enter (B)inary or (S)record input mode <B> : S +Enter address offset : <00000000 hex> : +.512.1024..2048....4096..... +Total bytes = 326280 in 2570249 uSecs +Loaded addresses 00100000 through 0011BB51. +Start address = 00100000 +>go +[Go 00100000] + +MPC8xx PlanetCore Flash Burner v2.00 +Copyright 2001 Embedded Planet. All rights reserved. + +Construct Flash Device.....done. + +Bad start address +Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length = +0xFFFFFFFF +Forcing Menu Interface + +h[elp] Show commands. +c[ode] Show information on code to be loaded. +di[splay] Display all flash sections. +du[mp] Dump memory. d ? for more info. +e[rase] Erase flash sections. +f[ill] Fill flash sections. +im[age] Toggle load high, low, or both flash +images. +in[fo] Show flash information. +ma[p] Show memory map. +mo[dify] Modify memory. m ? for more info. +p[rogram] Erase, program, and verify now. +reset Restart the loader. +s[how] Show flash sections to erase and program. +t[est] Test flash sections. +q[uit] Quit without programming. +#program 400000 ff000000 1D51F +doProgram( 400000 ff000000 1D51F ) + +Start = 0x00400000, target = 0xFF000000, length = +0x0001D51F +Erasing sector 0xFF000000, length 0x008000. +Erasing sector 0xFF008000, length 0x008000. +Erasing sector 0xFF010000, length 0x008000. +Erasing sector 0xFF018000, length 0x008000. +Programming FF000000 through FF01D51E +FLASH programmed successfully! +Press R to induce a hard reset + +Forcing Hard Reset by MachineCheck and +ResetOnCheckstop... + +U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) + +CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB +D-Cache +Board: RPXlite_DW +DRAM: 64 MB +FLASH: 16 MB +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET +u-boot> + +------------------------------------------------- + +Well, sometimes network function of PlanetCore couldn't work when +switching from U-Boot to PlanetCore. For example, you couldn't +download a file from HOST PC via TFTP. Don't worry, just restart your +HOST PC and everything would work as smooth as clockwork. I don't +know the reason WHY:-) + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Merry Christmas and Happy New Year! + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +===== +Best regards, + +Sam diff --git a/doc/README.mpc83xxads b/doc/README.mpc83xxads new file mode 100644 index 0000000000..d4561034b8 --- /dev/null +++ b/doc/README.mpc83xxads @@ -0,0 +1,98 @@ +Freescale MPC83xx ADS Boards +----------------------------------------- + +0. Toolchain / Building + + $ PATH=$PATH:/usr/powerpc/bin + $ CROSS_COMPILE=powerpc-linux- + $ export PATH CROSS_COMPILE + + $ powerpc-linux-gcc -v + Reading specs from /usr/powerpc/lib/gcc/powerpc-linux/3.4.3/specs + Configured with: ../configure --prefix=/usr/powerpc + --exec-prefix=/usr/powerpc --target=powerpc-linux --enable-shared + --disable-nls --disable-multilib --enable-languages=c,c++,ada,f77,objc + Thread model: posix + gcc version 3.4.3 (Debian) + + $ powerpc-linux-as -v + GNU assembler version 2.15 (powerpc-linux) using BFD version 2.15 + + + $ make MPC8349ADS_config + Configuring for MPC8349ADS board... + + $ make + + +1. Board Switches and Jumpers + + +2. Memory Map + +2.1. The memory map should look pretty much like this: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x9fff_ffff PCI MEM 512M + 0xc000_0000 0xdfff_ffff Rapid IO 512M + 0xe000_0000 0xe00f_ffff CCSR 1M + 0xe200_0000 0xe2ff_ffff PCI IO 16M + 0xf000_0000 0xf7ff_ffff SDRAM 128M + 0xf800_0000 0xf80f_ffff BCSR 1M + 0xfe00_0000 0xffff_ffff FLASH (boot bank) 16M + + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC8349ADS.h + + CONFIG_MPC83xx MPC83xx family + CONFIG_MPC8349 MPC8349 specific + CONFIG_MPC8349ADS MPC8349ADS board specific + CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet + + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC8349ADS_config + make + +5. Downloading and Flashing Images + +5.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp 10000 u-boot.bin + protect off fe000000 fe09ffff + erase fe000000 fe09ffff + + cp.b 10000 fe000000 xxxx +or + cp.b 10000 fe000000 a0000 + +You might have to supply the correct byte count for 'xxxx' from +the TFTP. Maybe a0000 will work too, that corresponds to the +erased sectors. + + +6. Notes diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index 939de20e8f..08d6831fb6 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -134,7 +134,6 @@ Updated 13-July-2004 Jon Loeliger CONFIG_E500 BOOKE e500 family(Motorola) CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives CONFIG_MPC8540 MPC8540 specific - CONFIG_MPC8560 MPC8560 specific CONFIG_MPC8540ADS MPC8540ADS board specific CONFIG_MPC8560ADS MPC8560ADS board specific CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking @@ -144,6 +143,7 @@ Updated 13-July-2004 Jon Loeliger CONFIG_DDR_ECC only for ECC DDR module CONFIG_DDR_DLL DLL fix on some ADS boards needed for more stability. + CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0. Other than the above definitions, the rest in the config files are straightforward. @@ -191,10 +191,10 @@ straightforward. 4.4 Reflash U-boot Image using U-boot - => tftp 10000 u-boot.bin - => protect off fff80000 ffffffff - => erase fff80000 ffffffff - => cp.b 10000 fff80000 80000 + tftp 10000 u-boot.bin + protect off fff80000 ffffffff + erase fff80000 ffffffff + cp.b 10000 fff80000 80000 4.5 Reflash U-Boot with a BDI-2000 diff --git a/doc/README.mpc85xxcds b/doc/README.mpc85xxcds index e0f49163ed..bc5db0ca8e 100644 --- a/doc/README.mpc85xxcds +++ b/doc/README.mpc85xxcds @@ -135,8 +135,8 @@ The default setting of all switches on the carrier board is: SW4=10001000 -CPU Card Switches ------------------ +8555/41 CPU Card Switches +------------------------- Most switches on the CPU Card should not be changed. However, the frequency can be changed by setting SW3: @@ -160,6 +160,45 @@ A safe default setting for all switches on the CPU board is: SW4=11111110 +8548 CPU Card Switches +---------------------- +And, just to be confusing, in this set of switches: + + ON = 1 + OFF = 0 + +Default + SW1=11111101 + SW2=10011111 + SW3=11001000 (8X) (2:1) + SW4=11110011 + + SW3=X000XXXX == CORE:CCB 4:1 + X001XXXX == CORE:CCB 9:2 + X010XXXX == CORE:CCB 1:1 + X011XXXX == CORE:CCB 3:2 + X100XXXX == CORE:CCB 2:1 + X101XXXX == CORE:CCB 5:2 + X110XXXX == CORE:CCB 3:1 + X111XXXX == CORE:CCB 7:2 + XXXX0000 == CCB:SYSCLK 16:1 + XXXX0001 == RESERVED + XXXX0010 == CCB:SYSCLK 2:1 + XXXX0011 == CCB:SYSCLK 3:1 + XXXX0100 == CCB:SYSCLK 4:1 + XXXX0101 == CCB:SYSCLK 5:1 + XXXX0110 == CCB:SYSCLK 6:1 + XXXX0111 == RESERVED + XXXX1000 == CCB:SYSCLK 8:1 + XXXX1001 == CCB:SYSCLK 9:1 + XXXX1010 == CCB:SYSCLK 10:1 + XXXX1011 == RESERVED + XXXX1100 == CCB:SYSCLK 12:1 + XXXX1101 == CCB:SYSCLK 20:1 + XXXX1110 == RESERVED + XXXX1111 == RESERVED + + eDINK Info ---------- diff --git a/doc/README.stxxtc b/doc/README.stxxtc new file mode 100644 index 0000000000..7d9d4d3a2e --- /dev/null +++ b/doc/README.stxxtc @@ -0,0 +1,59 @@ + + +First, some build notes on the Silicon Turnkey eXpress XTc. + +This board has both 87x/88x procesor options at various +frequencies. The configuration file has some macros for setting +the clock speed, not all have been tested. They all have +a 10MHz input clock. Please do not check in a configuration +file that selects a high speed not available on all processors. +We chose the 66MHz core and bus speed, which should be OK on +all boards. If you have a processor, lucky you! :-) +Just build a new configuration with that speed, check +the macro configuration to ensure it's correct. If the +macro is updated, please check that in, but keep default +processor speed. + +The board is likely to have more than 1Mbyte of NOR boot flash. +It was also configured with a high boot vector (Dan's fault) +so the standard 8xx mapping doesn't work well. We had to move +the addresses around a little bit so one copy would work. The +flash got fragmented, and we are working on a better solution. +There is an "xtc.cfg" floating around for the BDI2000, use +that for programming a new version of U-Boot. You can probably +find it on the Silicon Turnkey eXpress (www.silicontkx.com), +Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de) +servers. + +The board will also have various SDRAM sizes, but the code +should automatically determine the amount of memory. + +There are a couple of different board versions, visually +they use different BGA or surface mount memory parts. However, +they are logically the same board. + +Now, some operational notes. + +The board has the option of sporting two FEC Ethernet ports. +The second port isn't configured to be automatically available +because it would cause U-Boot to generate a board data structure +(the bd_t) with multiple MAC addresses and be incompatible with +standard 8xx kernel builds. You can use/test the second FEC +in U-Boot by assigning an 'eth1addr' and selecting the second +FEC as the port to use. + +Since this is just a development board and not a product, STx +does not assign unique MAC addresses. We just pilfer the +"default" ones used by Wolfgang on some other boards. Please +ensure you assign unique MAC addresses when using these boards. + +The serial port baud rate is 38400, because that's the way +I like it :-) + +Thanks to Pantelis for lots of the work on this board port. + +Have Fun! + + -- Dan + +15 August 2005 |