diff options
Diffstat (limited to 'board')
36 files changed, 887 insertions, 220 deletions
diff --git a/board/Synology/ds414/cmd_syno.c b/board/Synology/ds414/cmd_syno.c index 34643ff538..59e6fe0310 100644 --- a/board/Synology/ds414/cmd_syno.c +++ b/board/Synology/ds414/cmd_syno.c @@ -14,7 +14,6 @@ #include <asm/io.h> #include "../drivers/ddr/marvell/axp/ddr3_init.h" -#define ETH_ALEN 6 #define ETHADDR_MAX 4 #define SYNO_SN_TAG "SN=" #define SYNO_CHKSUM_TAG "CHK=" diff --git a/board/amlogic/khadas-vim2/Kconfig b/board/amlogic/khadas-vim2/Kconfig new file mode 100644 index 0000000000..d0af36264d --- /dev/null +++ b/board/amlogic/khadas-vim2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KHADAS_VIM2 + +config SYS_BOARD + default "khadas-vim2" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "khadas-vim2" + +endif diff --git a/board/amlogic/khadas-vim2/MAINTAINERS b/board/amlogic/khadas-vim2/MAINTAINERS new file mode 100644 index 0000000000..ca63e311c6 --- /dev/null +++ b/board/amlogic/khadas-vim2/MAINTAINERS @@ -0,0 +1,6 @@ +KHADAS-VIM2 +M: Neil Armstrong <narmstrong@baylibre.com> +S: Maintained +F: board/amlogic/khadas-vim2/ +F: include/configs/khadas-vim2.h +F: configs/khadas-vim2_defconfig diff --git a/board/amlogic/khadas-vim2/Makefile b/board/amlogic/khadas-vim2/Makefile new file mode 100644 index 0000000000..4e7c9a0592 --- /dev/null +++ b/board/amlogic/khadas-vim2/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 BayLibre, SAS +# Author: Neil Armstrong <narmstrong@baylibre.com> + +obj-y := khadas-vim2.o diff --git a/board/amlogic/khadas-vim2/README b/board/amlogic/khadas-vim2/README new file mode 100644 index 0000000000..578693fd2d --- /dev/null +++ b/board/amlogic/khadas-vim2/README @@ -0,0 +1,103 @@ +U-Boot for Khadas VIM2 +======================= + +Khadas VIM2 is an Open Source DIY Box manufactured by Shenzhen Wesion +Technology Co., Ltd with the following specifications: + + - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz + - ARM Mali T860 GPU + - 2/3GB DDR4 SDRAM + - 10/100/1000 Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG + - 16GB/32GB/64GB eMMC + - 2MB SPI Flash + - microSD + - SDIO Wifi Module, Bluetooth + - Two channels IR receiver + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC + +U-Boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make khadas-vim2_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot + > cd vim-u-boot + > make kvim_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxl/bl2.bin fip/ + > cp $FIPDIR/gxl/acs.bin fip/ + > cp $FIPDIR/gxl/bl21.bin fip/ + > cp $FIPDIR/gxl/bl30.bin fip/ + > cp $FIPDIR/gxl/bl301.bin fip/ + > cp $FIPDIR/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/khadas-vim2/khadas-vim2.c b/board/amlogic/khadas-vim2/khadas-vim2.c new file mode 100644 index 0000000000..ff56569f17 --- /dev/null +++ b/board/amlogic/khadas-vim2/khadas-vim2.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <dm.h> +#include <environment.h> +#include <asm/io.h> +#include <asm/arch/gx.h> +#include <asm/arch/mem.h> +#include <asm/arch/sm.h> +#include <asm/arch/eth.h> + +#define EFUSE_SN_OFFSET 20 +#define EFUSE_SN_SIZE 16 +#define EFUSE_MAC_OFFSET 52 +#define EFUSE_MAC_SIZE 6 + +int board_init(void) +{ + return 0; +} + +int misc_init_r(void) +{ + u8 mac_addr[EFUSE_MAC_SIZE]; + char serial[EFUSE_SN_SIZE]; + ssize_t len; + + meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0); + + /* Reset PHY on GPIOZ_14 */ + clrbits_le32(GX_GPIO_EN(3), BIT(14)); + clrbits_le32(GX_GPIO_OUT(3), BIT(14)); + mdelay(10); + setbits_le32(GX_GPIO_OUT(3), BIT(14)); + + if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { + len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, + mac_addr, EFUSE_MAC_SIZE); + if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) + eth_env_set_enetaddr("ethaddr", mac_addr); + } + + if (!env_get("serial#")) { + len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, + EFUSE_SN_SIZE); + if (len == EFUSE_SN_SIZE) + env_set("serial#", serial); + } + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + meson_gx_init_reserved_memory(blob); + + return 0; +} diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c index 3063884014..7ecfa49c70 100644 --- a/board/armltd/integrator/timer.c +++ b/board/armltd/integrator/timer.c @@ -93,31 +93,10 @@ int timer_init (void) /* * timer without interrupts */ -ulong get_timer (ulong base_ticks) -{ - return get_timer_masked () - base_ticks; -} - -/* delay usec useconds */ -void __udelay (unsigned long usec) -{ - ulong tmo, tmp; - - /* Convert to U-Boot ticks */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000000L); - - tmp = get_timer_masked(); /* get current timestamp */ - tmo += tmp; /* form target timestamp */ - - while (get_timer_masked () < tmo) {/* loop till event */ - /*NOP*/; - } -} /* converts the timer reading to U-Boot ticks */ /* the timestamp is the number of ticks since reset */ -ulong get_timer_masked (void) +static ulong get_timer_masked (void) { /* get current count */ unsigned long long now = READ_TIMER; @@ -138,10 +117,26 @@ ulong get_timer_masked (void) return timestamp; } -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) +ulong get_timer (ulong base_ticks) +{ + return get_timer_masked () - base_ticks; +} + +/* delay usec useconds */ +void __udelay (unsigned long usec) { - udelay(usec); + ulong tmo, tmp; + + /* Convert to U-Boot ticks */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000000L); + + tmp = get_timer_masked(); /* get current timestamp */ + tmo += tmp; /* form target timestamp */ + + while (get_timer_masked () < tmo) {/* loop till event */ + /*NOP*/; + } } /* diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 3bb5cd667e..0856786a0f 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -20,6 +20,9 @@ DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations */ + +void at91_prepare_cpu_var(void); + #ifdef CONFIG_CMD_NAND static void at91sam9x5ek_nand_hw_init(void) { @@ -85,6 +88,7 @@ int board_late_init(void) #ifdef CONFIG_DM_VIDEO at91_video_show_board_info(); #endif + at91_prepare_cpu_var(); return 0; } #endif diff --git a/board/atmel/common/board.c b/board/atmel/common/board.c index 8f9b5e137c..fc300a4210 100644 --- a/board/atmel/common/board.c +++ b/board/atmel/common/board.c @@ -13,6 +13,8 @@ #define AT91_PDA_EEPROM_ID_LENGTH 5 #define AT91_PDA_EEPROM_DEFAULT_BUS 0 +char *get_cpu_name(void); + void dummy(void) { } @@ -66,3 +68,8 @@ void at91_pda_detect(void) { } #endif + +void at91_prepare_cpu_var(void) +{ + env_set("cpu", get_cpu_name()); +} diff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c index 7dd7b85556..c7d3f8addc 100644 --- a/board/atmel/common/video_display.c +++ b/board/atmel/common/video_display.c @@ -18,6 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; int at91_video_show_board_info(void) { + struct vidconsole_priv *priv; ulong dram_size, nand_size; int i; u32 len = 0; @@ -63,7 +64,9 @@ int at91_video_show_board_info(void) if (ret) return ret; - vidconsole_position_cursor(con, 0, logo_info.logo_height); + priv = dev_get_uclass_priv(con); + vidconsole_position_cursor(con, 0, (logo_info.logo_height + + priv->y_charsize - 1) / priv->y_charsize); for (s = buf, i = 0; i < len; s++, i++) vidconsole_put_char(con, *s); diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index e8ec553f99..b0b29b3887 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -49,6 +49,33 @@ DECLARE_GLOBAL_DATA_PTR; #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) +#ifdef CONFIG_SPL_BUILD +#include <ns16550.h> +#include <dm/platform_data/spi_davinci.h> + +static const struct ns16550_platdata da850evm_serial = { + .base = DAVINCI_UART2_BASE, + .reg_shift = 2, + .clock = 150000000, + .fcr = UART_FCR_DEFVAL, +}; + +U_BOOT_DEVICE(da850evm_uart) = { + .name = "ns16550_serial", + .platdata = &da850evm_serial, +}; + +static const struct davinci_spi_platdata davinci_spi_data = { + .regs = (struct davinci_spi_regs *)0x01f0e000, + .num_cs = 4, +}; + +U_BOOT_DEVICE(davinci_spi) = { + .name = "davinci_spi", + .platdata = &davinci_spi_data, +}; +#endif + #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH static int get_mac_addr(u8 *addr) { diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index 40b1a0e631..f16b78cf03 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -487,16 +487,16 @@ void ls1088a_handle_phy_interface_sgmii(int dpmac_id) case 0x3A: switch (dpmac_id) { case 1: - wriop_set_phy_address(dpmac_id, riser_phy_addr[1]); + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]); break; case 2: - wriop_set_phy_address(dpmac_id, riser_phy_addr[0]); + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]); break; case 3: - wriop_set_phy_address(dpmac_id, riser_phy_addr[3]); + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]); break; case 7: - wriop_set_phy_address(dpmac_id, riser_phy_addr[2]); + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]); break; default: printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id); @@ -532,13 +532,13 @@ void ls1088a_handle_phy_interface_qsgmii(int dpmac_id) case 4: case 5: case 6: - wriop_set_phy_address(dpmac_id, dpmac_id + 9); + wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9); break; case 7: case 8: case 9: case 10: - wriop_set_phy_address(dpmac_id, dpmac_id + 1); + wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1); break; } @@ -567,7 +567,7 @@ void ls1088a_handle_phy_interface_xsgmii(int i) case 0x15: case 0x1D: case 0x1E: - wriop_set_phy_address(i, i + 26); + wriop_set_phy_address(i, 0, i + 26); ls1088a_qds_enable_SFP_TX(SFP_TX); break; default: @@ -590,13 +590,13 @@ static void ls1088a_handle_phy_interface_rgmii(int dpmac_id) switch (dpmac_id) { case 4: - wriop_set_phy_address(dpmac_id, RGMII_PHY1_ADDR); + wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR); dpmac_info[dpmac_id].board_mux = EMI1_RGMII1; bus = mii_dev_for_muxval(EMI1_RGMII1); wriop_set_mdio(dpmac_id, bus); break; case 5: - wriop_set_phy_address(dpmac_id, RGMII_PHY2_ADDR); + wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR); dpmac_info[dpmac_id].board_mux = EMI1_RGMII2; bus = mii_dev_for_muxval(EMI1_RGMII2); wriop_set_mdio(dpmac_id, bus); diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c index 418f362e9a..a2b52a879b 100644 --- a/board/freescale/ls1088a/eth_ls1088ardb.c +++ b/board/freescale/ls1088a/eth_ls1088ardb.c @@ -55,16 +55,17 @@ int board_eth_init(bd_t *bis) * a MAC has no PHY address, we give a PHY address to XFI * MAC error. */ - wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a); - wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1); - wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR); - wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR); - wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR); - wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR); - wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR); - wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR); - wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR); - wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR); + wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a); + wriop_set_phy_address(WRIOP1_DPMAC2, 0, AQ_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC3, 0, QSGMII1_PORT1_PHY_ADDR); + wriop_set_phy_address(WRIOP1_DPMAC4, 0, QSGMII1_PORT2_PHY_ADDR); + wriop_set_phy_address(WRIOP1_DPMAC5, 0, QSGMII1_PORT3_PHY_ADDR); + wriop_set_phy_address(WRIOP1_DPMAC6, 0, QSGMII1_PORT4_PHY_ADDR); + wriop_set_phy_address(WRIOP1_DPMAC7, 0, QSGMII2_PORT1_PHY_ADDR); + wriop_set_phy_address(WRIOP1_DPMAC8, 0, QSGMII2_PORT2_PHY_ADDR); + wriop_set_phy_address(WRIOP1_DPMAC9, 0, QSGMII2_PORT3_PHY_ADDR); + wriop_set_phy_address(WRIOP1_DPMAC10, 0, + QSGMII2_PORT4_PHY_ADDR); break; default: diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 989d57e09b..f706fd4cb6 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -623,7 +623,7 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) switch (++slot) { case 1: /* Slot housing a SGMII riser card? */ - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 1]); dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; bus = mii_dev_for_muxval(EMI1_SLOT1); @@ -631,7 +631,7 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) break; case 2: /* Slot housing a SGMII riser card? */ - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 1]); dpmac_info[dpmac_id].board_mux = EMI1_SLOT2; bus = mii_dev_for_muxval(EMI1_SLOT2); @@ -641,18 +641,18 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) if (slot == EMI_NONE) return; if (serdes1_prtcl == 0x39) { - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 2]); if (dpmac_id >= 6 && hwconfig_f("xqsgmii", env_hwconfig)) - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 3]); } else { - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 2]); if (dpmac_id >= 7 && hwconfig_f("xqsgmii", env_hwconfig)) - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 3]); } dpmac_info[dpmac_id].board_mux = EMI1_SLOT3; @@ -691,7 +691,7 @@ serdes2: break; case 4: /* Slot housing a SGMII riser card? */ - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 9]); dpmac_info[dpmac_id].board_mux = EMI1_SLOT4; bus = mii_dev_for_muxval(EMI1_SLOT4); @@ -701,14 +701,14 @@ serdes2: if (slot == EMI_NONE) return; if (serdes2_prtcl == 0x47) { - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 10]); if (dpmac_id >= 14 && hwconfig_f("xqsgmii", env_hwconfig)) - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 11]); } else { - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 11]); } dpmac_info[dpmac_id].board_mux = EMI1_SLOT5; @@ -717,7 +717,7 @@ serdes2: break; case 6: /* Slot housing a SGMII riser card? */ - wriop_set_phy_address(dpmac_id, + wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[dpmac_id - 13]); dpmac_info[dpmac_id].board_mux = EMI1_SLOT6; bus = mii_dev_for_muxval(EMI1_SLOT6); @@ -775,7 +775,7 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id) switch (++slot) { case 1: /* Slot housing a QSGMII riser card? */ - wriop_set_phy_address(dpmac_id, dpmac_id - 1); + wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1); dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; bus = mii_dev_for_muxval(EMI1_SLOT1); wriop_set_mdio(dpmac_id, bus); @@ -819,7 +819,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i) * the XAUI card is used for the XFI MAC, which will cause * error. */ - wriop_set_phy_address(i, i + 4); + wriop_set_phy_address(i, 0, i + 4); ls2080a_qds_enable_SFP_TX(SFP_TX); break; diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 45f1d60322..62c7a7a315 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -50,21 +50,21 @@ int board_eth_init(bd_t *bis) switch (srds_s1) { case 0x2A: - wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); - wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); - wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); - wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); - wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1); - wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2); - wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3); - wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); + wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4); + wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4); break; case 0x4B: - wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); - wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); - wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); - wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); + wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4); break; default: diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 4507b1ed99..691d38fdf2 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -40,6 +40,22 @@ DECLARE_GLOBAL_DATA_PTR; +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50 + +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50 + /* This is only needed until SPL gets OF support */ #ifdef CONFIG_SPL_BUILD static const struct ns16550_platdata omap3logic_serial = { @@ -50,7 +66,7 @@ static const struct ns16550_platdata omap3logic_serial = { }; U_BOOT_DEVICE(omap3logic_uart) = { - "ns16550_serial", + "omap_serial", &omap3logic_serial }; @@ -63,7 +79,7 @@ static const struct omap_hsmmc_plat omap3_logic_mmc0_platdata = { .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, }; -U_BOOT_DEVICE(am335x_mmc0) = { +U_BOOT_DEVICE(omap3_logic_mmc0) = { .name = "omap_hsmmc", .platdata = &omap3_logic_mmc0_platdata, }; @@ -89,11 +105,21 @@ int spl_start_uboot(void) void get_board_mem_timings(struct board_sdrc_timings *timings) { timings->mr = MICRON_V_MR_165; - /* 256MB DDR */ - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + + if (get_cpu_family() == CPU_OMAP36XX) { + /* 200 MHz works for OMAP36/DM37 */ + /* 256MB DDR */ + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } else { + /* 165 MHz works for OMAP35 */ + timings->mcfg = MICRON_V_MCFG_165(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } } #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c) @@ -138,6 +164,7 @@ void spl_board_prepare_for_linux(void) } #endif +#if !CONFIG_IS_ENABLED(DM_USB) #ifdef CONFIG_USB_MUSB_OMAP2PLUS static struct musb_hdrc_config musb_config = { .multipoint = 1, @@ -191,7 +218,7 @@ int ehci_hcd_stop(int index) } #endif /* CONFIG_USB_EHCI_HCD */ - +#endif /* !DM_USB*/ /* * Routine: misc_init_r * Description: Configure board specific parts @@ -201,13 +228,36 @@ int misc_init_r(void) twl4030_power_init(); omap_die_id_display(); +#if !CONFIG_IS_ENABLED(DM_USB) #ifdef CONFIG_USB_MUSB_OMAP2PLUS musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); #endif - +#endif return 0; } +#if defined(CONFIG_FLASH_CFI_DRIVER) +static const u32 gpmc_dm37_c2nor_config[] = { + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 +}; + +static const u32 gpmc_omap35_c2nor_config[] = { + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 +}; +#endif + /* * Routine: board_init * Description: Early hardware init. @@ -218,7 +268,16 @@ int board_init(void) /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - +#if defined(CONFIG_FLASH_CFI_DRIVER) + if (get_cpu_family() == CPU_OMAP36XX) { + /* Enable CS2 for NOR Flash */ + enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2], + 0x10000000, GPMC_SIZE_64M); + } else { + enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2], + 0x10000000, GPMC_SIZE_64M); + } +#endif return 0; } diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c index 648d191523..6f7b2b8cb1 100644 --- a/board/omicron/calimain/calimain.c +++ b/board/omicron/calimain/calimain.c @@ -22,6 +22,7 @@ #include <asm/arch/pinmux_defs.h> #include <asm/arch/davinci_misc.h> #include <asm/arch/timer_defs.h> +#include "../../../drivers/gpio/da8xx_gpio.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 852fdda843..8f3d3915f7 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -26,48 +26,24 @@ DECLARE_GLOBAL_DATA_PTR; -#define CPGWPCR 0xE6150904 -#define CPGWPR 0xE615090C - -#define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) { - struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; - struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; - - /* Watchdog init */ - writel(0xA5A5A500, &rwdt->rwtcsra); - writel(0xA5A5A500, &swdt->swtcsra); - - writel(0xA5A50000, CPGWPCR); - writel(0xFFFFFFFF, CPGWPR); } #define GSX_MSTP112 BIT(12) /* 3DG */ -#define TMU0_MSTP125 BIT(25) /* secure */ -#define TMU1_MSTP124 BIT(24) /* non-secure */ #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ #define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ int board_early_init_f(void) { - /* TMU0,1 */ /* which use ? */ - mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); - #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) /* DVFS for reset */ - mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); + mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); #endif return 0; } -/* SYSC */ -/* R/- 32 Power status register 2(3DG) */ -#define SYSC_PWRSR2 0xE6180100 -/* -/W 32 Power resume control register 2 (3DG) */ -#define SYSC_PWRONCR2 0xE618010C - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) @@ -84,7 +60,7 @@ int board_init(void) setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); /* Configure the HSUSB block */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); + mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); /* Choice USB0SEL */ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, HSUSB_REG_UGCTRL2_USB0SEL_EHCI); diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c index 9317410071..0e5efea19d 100644 --- a/board/renesas/eagle/eagle.c +++ b/board/renesas/eagle/eagle.c @@ -50,17 +50,12 @@ void s_init(void) clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); } -#define TMU0_MSTP125 BIT(25) /* secure */ - int board_early_init_f(void) { /* Unlock CPG access */ writel(0xA5A5FFFF, CPGWPR); writel(0x5A5A0000, CPGWPCR); - /* TMU0 */ - mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - return 0; } diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c index 248223b444..5d8b79eee3 100644 --- a/board/renesas/ebisu/ebisu.c +++ b/board/renesas/ebisu/ebisu.c @@ -30,13 +30,8 @@ void s_init(void) { } -#define TMU0_MSTP125 BIT(25) /* secure */ - int board_early_init_f(void) { - /* TMU0 */ - mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - return 0; } diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 00256bc1a3..8b15267d7b 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -27,48 +27,23 @@ DECLARE_GLOBAL_DATA_PTR; -#define CPGWPCR 0xE6150904 -#define CPGWPR 0xE615090C - -#define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) { - struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; - struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; - - /* Watchdog init */ - writel(0xA5A5A500, &rwdt->rwtcsra); - writel(0xA5A5A500, &swdt->swtcsra); - - writel(0xA5A50000, CPGWPCR); - writel(0xFFFFFFFF, CPGWPR); } -#define GSX_MSTP112 BIT(12) /* 3DG */ -#define TMU0_MSTP125 BIT(25) /* secure */ -#define TMU1_MSTP124 BIT(24) /* non-secure */ #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ #define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ int board_early_init_f(void) { - /* TMU0,1 */ /* which use ? */ - mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); - #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) /* DVFS for reset */ - mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); + mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); #endif return 0; } -/* SYSC */ -/* R/- 32 Power status register 2(3DG) */ -#define SYSC_PWRSR2 0xE6180100 -/* -/W 32 Power resume control register 2 (3DG) */ -#define SYSC_PWRONCR2 0xE618010C - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) @@ -78,25 +53,14 @@ int board_early_init_f(void) int board_init(void) { - u32 cpu_type = rmobile_get_cpu_type(); - /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) { - /* GSX: force power and clock supply */ - writel(0x0000001F, SYSC_PWRONCR2); - while (readl(SYSC_PWRSR2) != 0x000003E0) - mdelay(20); - - mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); - } - /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); /* Configure the HSUSB block */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); + mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); /* Choice USB0SEL */ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, HSUSB_REG_UGCTRL2_USB0SEL_EHCI); diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 213e869ebe..63550af1f0 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -26,48 +26,24 @@ DECLARE_GLOBAL_DATA_PTR; -#define CPGWPCR 0xE6150904 -#define CPGWPR 0xE615090C - -#define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) { - struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; - struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; - - /* Watchdog init */ - writel(0xA5A5A500, &rwdt->rwtcsra); - writel(0xA5A5A500, &swdt->swtcsra); - - writel(0xA5A50000, CPGWPCR); - writel(0xFFFFFFFF, CPGWPR); } #define GSX_MSTP112 BIT(12) /* 3DG */ -#define TMU0_MSTP125 BIT(25) /* secure */ -#define TMU1_MSTP124 BIT(24) /* non-secure */ #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ #define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ int board_early_init_f(void) { - /* TMU0,1 */ /* which use ? */ - mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); - #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) /* DVFS for reset */ - mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); + mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); #endif return 0; } -/* SYSC */ -/* R/- 32 Power status register 2(3DG) */ -#define SYSC_PWRSR2 0xE6180100 -/* -/W 32 Power resume control register 2 (3DG) */ -#define SYSC_PWRONCR2 0xE618010C - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) @@ -84,7 +60,7 @@ int board_init(void) setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); /* Configure the HSUSB block */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); + mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); /* Choice USB0SEL */ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, HSUSB_REG_UGCTRL2_USB0SEL_EHCI); diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c index 4473968db6..7a86e91877 100644 --- a/board/samsung/common/exynos5-dt-types.c +++ b/board/samsung/common/exynos5-dt-types.c @@ -24,14 +24,15 @@ static const struct udevice_id board_ids[] = { }; /** - * Odroix XU3/XU4/HC1 board revisions (from HC1_MAIN_REV0.1_20170630.pdf): + * Odroix XU3/XU4/HC1/HC2 board revisions (from HC1+_HC2_MAIN_REV0.1_20171017.pdf): * Rev ADCmax Board * 0.1 0 XU3 0.1 * 0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231) * 0.3 1280 XU4 0.1 * 0.4 739 XU4 0.2 * 0.5 1016 XU4+Air0.1 (Passive cooling) - * 0.6 1308 XU4S 0.1 (HC1) + * 0.6 1309 XU4-HC1 0.1 + * 0.7 1470 XU4-HC1+ 0.1 (HC2) * Use +1% for ADC value tolerance in the array below, the code loops until * the measured ADC value is lower than then ADCmax from the array. */ @@ -39,7 +40,8 @@ struct odroid_rev_info odroid_info[] = { { EXYNOS5_BOARD_ODROID_XU3_REV01, 1, 10, "xu3" }, { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 375, "xu3" }, { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1293, "xu4" }, - { EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1321, "hc1" }, + { EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1322, "hc1" }, + { EXYNOS5_BOARD_ODROID_HC2_REV01, 1, 1484, "hc1" }, { EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" }, }; @@ -144,6 +146,14 @@ bool board_is_odroidhc1(void) return false; } +bool board_is_odroidhc2(void) +{ + if (gd->board_type == EXYNOS5_BOARD_ODROID_HC2_REV01) + return true; + + return false; +} + bool board_is_generic(void) { if (gd->board_type == EXYNOS5_BOARD_GENERIC) diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 8c3a9ea564..c183965b92 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -179,7 +179,7 @@ char *get_dfu_alt_system(char *interface, char *devstr) { char *info = "Not supported!"; - if (board_is_odroidxu4() || board_is_odroidhc1()) + if (board_is_odroidxu4() || board_is_odroidhc1() || board_is_odroidhc2()) return info; return env_get("dfu_alt_system"); @@ -192,7 +192,7 @@ char *get_dfu_alt_boot(char *interface, char *devstr) char *alt_boot; int dev_num; - if (board_is_odroidxu4() || board_is_odroidhc1()) + if (board_is_odroidxu4() || board_is_odroidhc1() || board_is_odroidhc2()) return info; dev_num = simple_strtoul(devstr, NULL, 10); diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c index af78127dde..c95f7af7a7 100644 --- a/board/synopsys/axs10x/axs10x.c +++ b/board/synopsys/axs10x/axs10x.c @@ -33,6 +33,13 @@ int board_mmc_init(bd_t *bis) return 0; } +int board_mmc_getcd(struct mmc *mmc) +{ + struct dwmci_host *host = mmc->priv; + + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); +} + #define AXS_MB_CREG 0xE0011000 int board_early_init_f(void) diff --git a/board/synopsys/emdk/emdk.c b/board/synopsys/emdk/emdk.c index bbb946a700..79cafefb8b 100644 --- a/board/synopsys/emdk/emdk.c +++ b/board/synopsys/emdk/emdk.c @@ -34,6 +34,13 @@ int board_mmc_init(bd_t *bis) return 0; } +int board_mmc_getcd(struct mmc *mmc) +{ + struct dwmci_host *host = mmc->priv; + + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); +} + #define CREG_BASE 0xF0001000 #define CREG_BOOT_OFFSET 0 #define CREG_BOOT_WP_OFFSET 8 diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index fb4286f71b..b6aefdbe6d 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -1019,6 +1019,13 @@ int board_late_init(void) return 0; } +int board_mmc_getcd(struct mmc *mmc) +{ + struct dwmci_host *host = mmc->priv; + + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); +} + int board_mmc_init(bd_t *bis) { struct dwmci_host *host = NULL; @@ -1046,3 +1053,11 @@ int board_mmc_init(bd_t *bis) return 0; } + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + printf("CPU: ARC HS38 v2.1c\n"); + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/board/synopsys/iot_devkit/iot_devkit.c b/board/synopsys/iot_devkit/iot_devkit.c index c185d5cdb5..f8838fb3ce 100644 --- a/board/synopsys/iot_devkit/iot_devkit.c +++ b/board/synopsys/iot_devkit/iot_devkit.c @@ -17,6 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; #define AHBCKDIV (void *)(SYSCON_BASE + 0x04) #define APBCKDIV (void *)(SYSCON_BASE + 0x08) #define APBCKEN (void *)(SYSCON_BASE + 0x0C) +#define RESET_REG (void *)(SYSCON_BASE + 0x18) #define CLKSEL (void *)(SYSCON_BASE + 0x24) #define CLKSTAT (void *)(SYSCON_BASE + 0x28) #define PLLCON (void *)(SYSCON_BASE + 0x2C) @@ -67,6 +68,14 @@ static int set_cpu_freq(unsigned int clk) writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON); break; + case 136: + writel(readl(PLLCON) & PLL_MASK_0, PLLCON); + /* pll_off=1, M=17, N=1, OD=1, PLL_OUT_CLK=136M */ + writel((readl(PLLCON) & PLL_MASK_1) | 0x100111, PLLCON); + /* pll_off=0, M=17, N=1, OD=1, PLL_OUT_CLK=136M */ + writel((readl(PLLCON) & PLL_MASK_2) | 0x100111, PLLCON); + break; + case 144: writel(readl(PLLCON) & PLL_MASK_0, PLLCON); /* pll_off=1, M=18, N=1, OD=1, PLL_OUT_CLK=144M */ @@ -99,7 +108,7 @@ extern u8 __ram_end[]; */ int mach_cpu_init(void) { - int offset, freq; + int offset; /* Don't relocate U-Boot */ gd->flags |= GD_FLG_SKIP_RELOC; @@ -120,12 +129,12 @@ int mach_cpu_init(void) if (offset < 0) return offset; - freq = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0); - if (!freq) + gd->cpu_clk = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0); + if (!gd->cpu_clk) return -EINVAL; /* If CPU freq > 100 MHz, divide eFLASH clock by 2 */ - if (freq > 100000000) { + if (gd->cpu_clk > 100000000) { u32 reg = readl(AHBCKDIV); reg &= ~(0xF << 8); @@ -133,7 +142,7 @@ int mach_cpu_init(void) writel(reg, AHBCKDIV); } - return set_cpu_freq(freq); + return set_cpu_freq(gd->cpu_clk); } #define ARC_PERIPHERAL_BASE 0xF0000000 @@ -161,8 +170,32 @@ int board_mmc_init(bd_t *bis) return 0; } +int board_mmc_getcd(struct mmc *mmc) +{ + struct dwmci_host *host = mmc->priv; + + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); +} + +#define IOTDK_RESET_SEQ 0x55AA6699 + +void reset_cpu(ulong addr) +{ + writel(IOTDK_RESET_SEQ, RESET_REG); +} + int checkboard(void) { puts("Board: Synopsys IoT Development Kit\n"); return 0; }; + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + char mhz[8]; + + printf("CPU: ARC EM9D at %s MHz\n", strmhz(mhz, gd->cpu_clk)); + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 274f18e942..d81c8e621f 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -146,14 +146,10 @@ int ft_board_setup(void *blob, bd_t *bd) int nbanks; u64 size[2]; u64 start[2]; - int nodeoffset; u32 ddr3a_size; - int unitrd_fixup = 0; env = env_get("mem_lpae"); lpae = env && simple_strtol(env, NULL, 0); - env = env_get("uinitrd_fixup"); - unitrd_fixup = env && simple_strtol(env, NULL, 0); ddr3a_size = 0; if (lpae) { @@ -191,24 +187,41 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, start, size, nbanks); + return 0; +} + +void ft_board_setup_ex(void *blob, bd_t *bd) +{ + int lpae; + u64 size; + char *env; + u64 *reserve_start; + int unitrd_fixup = 0; + + env = env_get("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + env = env_get("uinitrd_fixup"); + unitrd_fixup = env && simple_strtol(env, NULL, 0); + /* Fix up the initrd */ if (lpae && unitrd_fixup) { + int nodeoffset; int err; - u32 *prop1, *prop2; + u64 *prop1, *prop2; u64 initrd_start, initrd_end; nodeoffset = fdt_path_offset(blob, "/chosen"); if (nodeoffset >= 0) { - prop1 = (u32 *)fdt_getprop(blob, nodeoffset, + prop1 = (u64 *)fdt_getprop(blob, nodeoffset, "linux,initrd-start", NULL); - prop2 = (u32 *)fdt_getprop(blob, nodeoffset, + prop2 = (u64 *)fdt_getprop(blob, nodeoffset, "linux,initrd-end", NULL); if (prop1 && prop2) { - initrd_start = __be32_to_cpu(*prop1); + initrd_start = __be64_to_cpu(*prop1); initrd_start -= CONFIG_SYS_SDRAM_BASE; initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; initrd_start = __cpu_to_be64(initrd_start); - initrd_end = __be32_to_cpu(*prop2); + initrd_end = __be64_to_cpu(*prop2); initrd_end -= CONFIG_SYS_SDRAM_BASE; initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; initrd_end = __cpu_to_be64(initrd_end); @@ -240,19 +253,6 @@ int ft_board_setup(void *blob, bd_t *bd) } } - return 0; -} - -void ft_board_setup_ex(void *blob, bd_t *bd) -{ - int lpae; - u64 size; - char *env; - u64 *reserve_start; - - env = env_get("mem_lpae"); - lpae = env && simple_strtol(env, NULL, 0); - if (lpae) { /* * the initrd and other reserved memory areas are diff --git a/board/timll/devkit3250/Kconfig b/board/timll/devkit3250/Kconfig index e3bd4569d6..5129c2dcae 100644 --- a/board/timll/devkit3250/Kconfig +++ b/board/timll/devkit3250/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "timll" -config SYS_SOC - default "lpc32xx" - config SYS_CONFIG_NAME default "devkit3250" diff --git a/board/work-microwave/work_92105/Kconfig b/board/work-microwave/work_92105/Kconfig index 4bc34ed01f..32632f5ab5 100644 --- a/board/work-microwave/work_92105/Kconfig +++ b/board/work-microwave/work_92105/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "work-microwave" -config SYS_SOC - default "lpc32xx" - config SYS_CONFIG_NAME default "work_92105" diff --git a/board/xilinx/versal/MAINTAINERS b/board/xilinx/versal/MAINTAINERS new file mode 100644 index 0000000000..2d2b808245 --- /dev/null +++ b/board/xilinx/versal/MAINTAINERS @@ -0,0 +1,7 @@ +XILINX_VERSAL BOARDS +M: Michal Simek <michal.simek@xilinx.com> +S: Maintained +F: arch/arm/dts/versal* +F: board/xilinx/versal/ +F: include/configs/xilinx_versal* +F: configs/xilinx_versal* diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile new file mode 100644 index 0000000000..2b812765ee --- /dev/null +++ b/board/xilinx/versal/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 - 2018 Xilinx, Inc. +# Michal Simek <michal.simek@xilinx.com> +# + +obj-y := board.o diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c new file mode 100644 index 0000000000..2b3a40b73a --- /dev/null +++ b/board/xilinx/versal/board.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2018 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + */ + +#include <common.h> +#include <fdtdec.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + printf("EL Level:\tEL%d\n", current_el()); + + return 0; +} + +int board_early_init_r(void) +{ + if (current_el() == 3) { + u32 val; + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); + } + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + + return 0; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c new file mode 100644 index 0000000000..5366956e5b --- /dev/null +++ b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + */ + +#include <asm/arch/ps7_init_gpl.h> + +static unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000002U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000004U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U), + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A02U), + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U), + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01EC044DU), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U), + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159AU), + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U), + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U), + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U), + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0FF66666U), + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00029000U), + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029000U), + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00029000U), + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00029000U), + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000F9U), + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000F9U), + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F9U), + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000F9U), + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0xF8000B74, 0x00002000U), + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0xF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U), + EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U), + EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U), + EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U), + EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U), + EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000200U), + EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x000002E0U), + EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001240U), + EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001240U), + EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00001201U), + EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U), + EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001218U), + EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + int ret = -1; + + ret = ps7_config(ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + return PS7_INIT_SUCCESS; +} diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index f8c8674f87..3e039ccb13 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -6,6 +6,7 @@ #include <common.h> #include <malloc.h> +#include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> @@ -102,10 +103,36 @@ static int do_zynqmp_mmio_write(cmd_tbl_t *cmdtp, int flag, int argc, return ret; } +#ifdef CONFIG_DEFINE_TCM_OCM_MMAP +static int do_zynqmp_tcm_init(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + u8 mode; + + if (argc != cmdtp->maxargs) + return CMD_RET_USAGE; + + mode = simple_strtoul(argv[2], NULL, 16); + if (mode != TCM_LOCK && mode != TCM_SPLIT) { + printf("Mode should be either 0(lock)/1(split)\n"); + return CMD_RET_FAILURE; + } + + dcache_disable(); + tcm_init(mode); + dcache_enable(); + + return CMD_RET_SUCCESS; +} +#endif + static cmd_tbl_t cmd_zynqmp_sub[] = { U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""), U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""), U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""), +#ifdef CONFIG_DEFINE_TCM_OCM_MMAP + U_BOOT_CMD_MKENT(tcminit, 3, 0, do_zynqmp_tcm_init, "", ""), +#endif }; /** @@ -145,7 +172,15 @@ static char zynqmp_help_text[] = " be used for decryption\n" "zynqmp mmio_read address - read from address\n" "zynqmp mmio_write address mask value - write value after masking to\n" - " address\n"; + " address\n" +#ifdef CONFIG_DEFINE_TCM_OCM_MMAP + "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n" + " initialized before accessing to avoid ECC\n" + " errors. mode specifies in which mode TCM has\n" + " to be initialized. Supported modes will be\n" + " lock(0)/split(1)\n" +#endif + ; #endif U_BOOT_CMD( |