diff options
Diffstat (limited to 'board')
33 files changed, 471 insertions, 98 deletions
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h index e4896fba14..ded69e7785 100644 --- a/board/BuR/common/bur_common.h +++ b/board/BuR/common/bur_common.h @@ -3,7 +3,7 @@ * * common board information header for B&R boards * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 5b356fbbbd..7830d1a200 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -3,7 +3,7 @@ * * common board functions for B&R boards * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/kwb/MAINTAINERS b/board/BuR/kwb/MAINTAINERS index c28fb49fe4..ca7d329144 100644 --- a/board/BuR/kwb/MAINTAINERS +++ b/board/BuR/kwb/MAINTAINERS @@ -1,5 +1,5 @@ KWB BOARD -M: Hannes Petermaier <hannes.petermaier@br-automation.com> +M: Hannes Schmelzer <hannes.schmelzer@br-automation.com> S: Maintained F: board/BuR/kwb/ F: include/configs/kwb.h diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile index 7b04b26ae4..782664c36e 100644 --- a/board/BuR/kwb/Makefile +++ b/board/BuR/kwb/Makefile @@ -1,7 +1,7 @@ # # Makefile # -# Copyright (C) 2014 Hannes Petermaier <oe5hpm@oevsv.at> - +# Copyright (C) 2014 Hannes Schmelzer <oe5hpm@oevsv.at> - # Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/ # # SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c index 01dd1d9915..640aca4cde 100644 --- a/board/BuR/kwb/board.c +++ b/board/BuR/kwb/board.c @@ -3,7 +3,7 @@ * * Board functions for B&R KWB Board * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c index 2b1d8d3b1d..40224f76f6 100644 --- a/board/BuR/kwb/mux.c +++ b/board/BuR/kwb/mux.c @@ -3,7 +3,7 @@ * * Pinmux Setting for B&R LEIT Board(s) * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/tseries/MAINTAINERS b/board/BuR/tseries/MAINTAINERS index e57326aaf3..e2e67e6bbf 100644 --- a/board/BuR/tseries/MAINTAINERS +++ b/board/BuR/tseries/MAINTAINERS @@ -1,5 +1,5 @@ TSERIES BOARD -M: Hannes Petermaier <hannes.petermaier@br-automation.com> +M: Hannes Schmelzer <hannes.schmelzer@br-automation.com> S: Maintained F: board/BuR/tseries/ F: include/configs/tseries.h diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile index ec0d27a7aa..43945d285d 100644 --- a/board/BuR/tseries/Makefile +++ b/board/BuR/tseries/Makefile @@ -1,7 +1,7 @@ # # Makefile # -# Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> +# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> # Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com # # SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c index d1d698e7d2..bc119e6973 100644 --- a/board/BuR/tseries/board.c +++ b/board/BuR/tseries/board.c @@ -3,7 +3,7 @@ * * Board functions for B&R LEIT Board * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c index c5dc4b7625..349788a835 100644 --- a/board/BuR/tseries/mux.c +++ b/board/BuR/tseries/mux.c @@ -3,7 +3,7 @@ * * Pinmux Setting for B&R LEIT Board(s) * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index 45dd788805..0f3734587a 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -227,8 +227,6 @@ static void erase_environment(void) static void rescue_mode(void) { - uchar enetaddr[6]; - printf("Entering rescue mode..\n"); setenv("bootsource", "rescue"); } diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index 6a04158f16..3ff64f4084 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -16,21 +16,21 @@ comment "coreboot-specific options" config SYS_CONFIG_NAME string "Board configuration file" - default "chromebook_link" + default "qemu-x86" help This option selects the board configuration file in include/configs/ directory to be used to build U-Boot for coreboot. config DEFAULT_DEVICE_TREE string "Board Device Tree Source (dts) file" - default "chromebook_link" + default "qemu-x86_i440fx" help This option selects the board Device Tree Source (dts) file in arch/x86/dts/ directory to be used to build U-Boot for coreboot. config SYS_CAR_ADDR hex "Board specific Cache-As-RAM (CAR) address" - default 0x19200000 + default 0x01920000 help This option specifies the board specific Cache-As-RAM (CAR) address. diff --git a/board/emulation/Kconfig b/board/emulation/Kconfig new file mode 100644 index 0000000000..36809fd376 --- /dev/null +++ b/board/emulation/Kconfig @@ -0,0 +1,25 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_EMULATION + +choice + prompt "Mainboard model" + +config TARGET_QEMU_X86 + bool "QEMU x86" + help + This is the QEMU emulated x86 board. U-Boot supports running + as a coreboot payload as well as bare boot without coreboot. + There are two types of x86 boards supported by QEMU which are + supported by U-Boot. They are via QEMU '-M pc', an i440FX/PIIX + chipset platform and '-M q35', a Q35/ICH9 chipset platform. + +endchoice + +source "board/emulation/qemu-x86/Kconfig" + +endif diff --git a/board/emulation/qemu-x86/Kconfig b/board/emulation/qemu-x86/Kconfig new file mode 100644 index 0000000000..e777ef4409 --- /dev/null +++ b/board/emulation/qemu-x86/Kconfig @@ -0,0 +1,24 @@ +if TARGET_QEMU_X86 + +config SYS_BOARD + default "qemu-x86" + +config SYS_VENDOR + default "emulation" + +config SYS_SOC + default "qemu" + +config SYS_CONFIG_NAME + default "qemu-x86" + +config SYS_TEXT_BASE + default 0xfff00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select QEMU + select BOARD_ROMSIZE_KB_1024 + +endif diff --git a/board/emulation/qemu-x86/MAINTAINERS b/board/emulation/qemu-x86/MAINTAINERS new file mode 100644 index 0000000000..ea4dd19354 --- /dev/null +++ b/board/emulation/qemu-x86/MAINTAINERS @@ -0,0 +1,6 @@ +QEMU X86 BOARD +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/emulation/qemu-x86/ +F: include/configs/qemu-x86.h +F: configs/qemu-x86_defconfig diff --git a/board/emulation/qemu-x86/Makefile b/board/emulation/qemu-x86/Makefile new file mode 100644 index 0000000000..ad2bbb94a2 --- /dev/null +++ b/board/emulation/qemu-x86/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += qemu-x86.o start.o diff --git a/board/emulation/qemu-x86/qemu-x86.c b/board/emulation/qemu-x86/qemu-x86.c new file mode 100644 index 0000000000..fedea81abc --- /dev/null +++ b/board/emulation/qemu-x86/qemu-x86.c @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/emulation/qemu-x86/start.S b/board/emulation/qemu-x86/start.S new file mode 100644 index 0000000000..a71db69be9 --- /dev/null +++ b/board/emulation/qemu-x86/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 31bb320213..ad2d5b69d6 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -12,8 +12,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, 4) -DECLARE_GLOBAL_DATA_PTR; - int board_early_init_f(void) { lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ); diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c index f2e74687ed..746ab277cb 100644 --- a/board/intel/galileo/galileo.c +++ b/board/intel/galileo/galileo.c @@ -6,8 +6,6 @@ #include <common.h> -DECLARE_GLOBAL_DATA_PTR; - int board_early_init_f(void) { return 0; diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index fd2070afb2..383cae068b 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <asm/gpio.h> #include <asm/ibmpc.h> #include <asm/pnp_def.h> #include <netdev.h> @@ -12,7 +13,13 @@ #define SERIAL_DEV PNP_DEV(0x2e, 4) -DECLARE_GLOBAL_DATA_PTR; +int arch_early_init_r(void) +{ + /* do the pin-muxing */ + gpio_ich6_pinctrl_init(); + + return 0; +} int board_early_init_f(void) { diff --git a/board/renesas/alt/Kconfig b/board/renesas/alt/Kconfig index 957962de20..39d53c185b 100644 --- a/board/renesas/alt/Kconfig +++ b/board/renesas/alt/Kconfig @@ -9,4 +9,13 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "alt" +config R8A7794_ETHERNET_B + bool "Use ethernet B function" + depends on TARGET_ALT + default n + help + ALT board can use default ethernet and etnernet B function. + This config set pin function of ethenet B. You also needt to change + DIP switch of board in order to use this function. + endif diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index f0010db814..3501a17044 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -1,7 +1,7 @@ /* * board/renesas/alt/alt.c * - * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2014, 2015 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -94,6 +94,20 @@ int board_init(void) r8a7794_pinmux_init(); /* Ether Enable */ +#if defined(CONFIG_R8A7794_ETHERNET_B) + gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL); + gpio_request(GPIO_FN_ETH_RX_ER_B, NULL); + gpio_request(GPIO_FN_ETH_RXD0_B, NULL); + gpio_request(GPIO_FN_ETH_RXD1_B, NULL); + gpio_request(GPIO_FN_ETH_LINK_B, NULL); + gpio_request(GPIO_FN_ETH_REFCLK_B, NULL); + gpio_request(GPIO_FN_ETH_MDIO_B, NULL); + gpio_request(GPIO_FN_ETH_TXD1_B, NULL); + gpio_request(GPIO_FN_ETH_TX_EN_B, NULL); + gpio_request(GPIO_FN_ETH_MAGIC_B, NULL); + gpio_request(GPIO_FN_ETH_TXD0_B, NULL); + gpio_request(GPIO_FN_ETH_MDC_B, NULL); +#else gpio_request(GPIO_FN_ETH_CRS_DV, NULL); gpio_request(GPIO_FN_ETH_RX_ER, NULL); gpio_request(GPIO_FN_ETH_RXD0, NULL); @@ -106,6 +120,7 @@ int board_init(void) gpio_request(GPIO_FN_ETH_MAGIC, NULL); gpio_request(GPIO_FN_ETH_TXD0, NULL); gpio_request(GPIO_FN_ETH_MDC, NULL); +#endif gpio_request(GPIO_FN_IRQ8, NULL); /* PHY reset */ diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c index f0b349f18f..b6324c8fd7 100644 --- a/board/renesas/alt/qos.c +++ b/board/renesas/alt/qos.c @@ -14,7 +14,7 @@ #include <asm/arch/rmobile.h> #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) -/* QoS version 0.11 */ +/* QoS version 0.311 for ES1 and version 0.321 for ES2 */ enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -62,6 +62,24 @@ static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { [DBSC3_15] = DBSC3_0_QOS_W15_BASE, }; +#if defined(CONFIG_QOS_PRI_MEDIA) +#define is_qos_pri_media() 1 +#else +#define is_qos_pri_media() 0 +#endif + +#if defined(CONFIG_QOS_PRI_NORMAL) +#define is_qos_pri_normal() 1 +#else +#define is_qos_pri_normal() 0 +#endif + +#if defined(CONFIG_QOS_PRI_GFX) +#define is_qos_pri_gfx() 1 +#else +#define is_qos_pri_gfx() 0 +#endif + void qos_init(void) { int i; @@ -77,30 +95,57 @@ void qos_init(void) /* S3C -QoS */ s3c = (struct rcar_s3c *)S3C_BASE; - writel(0x1F0D0B0A, &s3c->s3crorr); - writel(0x1F0D0B09, &s3c->s3cworr); - + if (is_qos_pri_media()) { + writel(0x1F0B0604, &s3c->s3crorr); + writel(0x1F0E0705, &s3c->s3cworr); + } else if (is_qos_pri_normal()) { + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0E0A08, &s3c->s3cworr); + } else if (is_qos_pri_media()) { + writel(0x1F0B0B0B, &s3c->s3crorr); + writel(0x1F0E0C0C, &s3c->s3cworr); + } /* QoS Control Registers */ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_media()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_media()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_media()) + writel(0x20AA2100, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; @@ -115,7 +160,7 @@ void qos_init(void) writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x00820092, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20FA, &s3c_qos->s3cqos3); @@ -157,8 +202,13 @@ void qos_init(void) } /* CCI-400 -QoS */ - writel(0x20000800, CCI_400_MAXOT_1); - writel(0x20000800, CCI_400_MAXOT_2); + if (IS_R8A7794_ES2()) { + writel(0x20001000, CCI_400_MAXOT_1); + writel(0x20001000, CCI_400_MAXOT_2); + } else { + writel(0x20000800, CCI_400_MAXOT_1); + writel(0x20000800, CCI_400_MAXOT_2); + } writel(0x0000000C, CCI_400_QOSCNTL_1); writel(0x0000000C, CCI_400_QOSCNTL_2); @@ -166,7 +216,7 @@ void qos_init(void) /* Transaction Control (MXI) */ mxi = (struct rcar_mxi *)MXI_BASE; writel(0x00000013, &mxi->mxrtcr); - writel(0x00000013, &mxi->mxwtcr); + writel(0x00000016, &mxi->mxwtcr); writel(0x00780080, &mxi->mxsaar0); writel(0x02000800, &mxi->mxsaar1); @@ -449,7 +499,7 @@ void qos_init(void) /* QoS Register (RT-AXI) */ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; - writel(0x00000000, &axi_qos->qosconf); + writel(0x00000001, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); diff --git a/board/renesas/gose/qos.c b/board/renesas/gose/qos.c index 64e52cf3a4..413ad1124b 100644 --- a/board/renesas/gose/qos.c +++ b/board/renesas/gose/qos.c @@ -14,7 +14,7 @@ #include <asm/arch/rmobile.h> #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) -/* QoS version 0.20 */ +/* QoS version 0.311 */ enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, @@ -61,6 +61,24 @@ static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { [DBSC3_15] = DBSC3_0_QOS_W15_BASE, }; +#if defined(CONFIG_QOS_PRI_MEDIA) +#define is_qos_pri_media() 1 +#else +#define is_qos_pri_media() 0 +#endif + +#if defined(CONFIG_QOS_PRI_NORMAL) +#define is_qos_pri_normal() 1 +#else +#define is_qos_pri_normal() 0 +#endif + +#if defined(CONFIG_QOS_PRI_GFX) +#define is_qos_pri_gfx() 1 +#else +#define is_qos_pri_gfx() 0 +#endif + void qos_init(void) { int i; @@ -77,34 +95,62 @@ void qos_init(void) /* S3C -QoS */ s3c = (struct rcar_s3c *)S3C_BASE; writel(0x00000000, &s3c->s3cadsplcr); - writel(0x1F0B0908, &s3c->s3crorr); - writel(0x1F0C0A08, &s3c->s3cworr); - + if (is_qos_pri_media()) { + writel(0x1F0B0604, &s3c->s3crorr); + writel(0x1F0E0705, &s3c->s3cworr); + } else if (is_qos_pri_normal()) { + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0C0A08, &s3c->s3cworr); + } else if (is_qos_pri_gfx()) { + writel(0x1F0B0B0B, &s3c->s3crorr); + writel(0x1F0E0C0C, &s3c->s3cworr); + } /* QoS Control Registers */ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos4); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x00820092, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20DC, &s3c_qos->s3cqos3); @@ -115,7 +161,7 @@ void qos_init(void) writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x00820092, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20FA, &s3c_qos->s3cqos3); @@ -166,11 +212,13 @@ void qos_init(void) /* Transaction Control (MXI) */ mxi = (struct rcar_mxi *)MXI_BASE; writel(0x00000013, &mxi->mxrtcr); - writel(0x00000013, &mxi->mxwtcr); + writel(0x00000016, &mxi->mxwtcr); writel(0x00200000, &mxi->mxs3cracr); writel(0x00200000, &mxi->mxs3cwacr); writel(0x00200000, &mxi->mxaxiracr); writel(0x00200000, &mxi->mxaxiwacr); + writel(0x00780080, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); /* QoS Control (MXI) */ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; @@ -554,7 +602,7 @@ void qos_init(void) /* QoS Register (RT-AXI) */ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; - writel(0x00000000, &axi_qos->qosconf); + writel(0x00000001, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c index d293e3d7fc..8cb2b48f57 100644 --- a/board/renesas/koelsch/qos.c +++ b/board/renesas/koelsch/qos.c @@ -13,7 +13,7 @@ #include <asm/io.h> #include <asm/arch/rmobile.h> -/* QoS version 0.240 for ES1 and version 0.334 for ES2 */ +/* QoS version 0.240 for ES1 and version 0.411 for ES2 */ #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -99,6 +99,24 @@ static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = { [DBSC3_15] = DBSC3_1_QOS_W15_BASE, }; +#if defined(CONFIG_QOS_PRI_MEDIA) +#define is_qos_pri_media() 1 +#else +#define is_qos_pri_media() 0 +#endif + +#if defined(CONFIG_QOS_PRI_NORMAL) +#define is_qos_pri_normal() 1 +#else +#define is_qos_pri_normal() 0 +#endif + +#if defined(CONFIG_QOS_PRI_GFX) +#define is_qos_pri_gfx() 1 +#else +#define is_qos_pri_gfx() 0 +#endif + void qos_init(void) { int i; @@ -124,8 +142,17 @@ void qos_init(void) /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */ /* Ssplit All mode */ /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */ - writel(0x1F0B0908, &s3c->s3crorr); - writel(0x1F0C0A08, &s3c->s3cworr); + + if (is_qos_pri_media()) { + writel(0x1F0B0604, &s3c->s3crorr); + writel(0x1F0E0705, &s3c->s3cworr); + } else if (is_qos_pri_normal()) { + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0E0A08, &s3c->s3cworr); + } else if (is_qos_pri_gfx()) { + writel(0x1F0B0B0B, &s3c->s3crorr); + writel(0x1F0E0C0C, &s3c->s3cworr); + } } else { writel(0x00FF1B1D, &s3c->s3cadsplcr); writel(0x1F0D0C0C, &s3c->s3crorr); @@ -136,26 +163,67 @@ void qos_init(void) writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + + if (IS_R8A7791_ES2()) { + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); + } else { + writel(0x20AA2200, &s3c_qos->s3cqos3); + } writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + + if (IS_R8A7791_ES2()) { + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); + } else { + writel(0x20AA2200, &s3c_qos->s3cqos7); + } writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (IS_R8A7791_ES2()) { + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); + } else { + writel(0x20AA2200, &s3c_qos->s3cqos3); + } writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (IS_R8A7791_ES2()) { + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); + } else { + writel(0x20AA2200, &s3c_qos->s3cqos7); + } writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + if (IS_R8A7791_ES2()) + writel(0x80928092, &s3c_qos->s3cqos0); + else + writel(0x00820082, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20DC, &s3c_qos->s3cqos3); @@ -166,7 +234,10 @@ void qos_init(void) writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + if (IS_R8A7791_ES2()) + writel(0x80928092, &s3c_qos->s3cqos0); + else + writel(0x00820082, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20FA, &s3c_qos->s3cqos3); @@ -245,9 +316,15 @@ void qos_init(void) /* MXI -QoS */ /* Transaction Control (MXI) */ - mxi = (struct rcar_mxi *)MXI_BASE; + mxi = (struct rcar_mxi *)XI_BASE; writel(0x00000013, &mxi->mxrtcr); - writel(0x00000013, &mxi->mxwtcr); + if (IS_R8A7791_ES2()) { + writel(0x00000016, &mxi->mxwtcr); + writel(0x00780080, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + } else { + writel(0x00000013, &mxi->mxwtcr); + } /* QoS Control (MXI) */ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; @@ -632,7 +709,10 @@ void qos_init(void) /* QoS Register (RT-AXI) */ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; - writel(0x00000000, &axi_qos->qosconf); + if (IS_R8A7791_ES2()) + writel(0x00000001, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c index dec37d2bf9..ae155512f5 100644 --- a/board/renesas/lager/qos.c +++ b/board/renesas/lager/qos.c @@ -12,7 +12,7 @@ #include <asm/io.h> #include <asm/arch/rmobile.h> -/* QoS version 0.955 for ES1 and version 0.963 for ES2 */ +/* QoS version 0.955 for ES1 and version 0.973 for ES2 */ #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -1133,6 +1133,24 @@ static void qos_init_es1(void) writel(0x00000000, &axi_qos->qosqon); } +#if defined(CONFIG_QOS_PRI_MEDIA) +#define is_qos_pri_media() 1 +#else +#define is_qos_pri_media() 0 +#endif + +#if defined(CONFIG_QOS_PRI_NORMAL) +#define is_qos_pri_normal() 1 +#else +#define is_qos_pri_normal() 0 +#endif + +#if defined(CONFIG_QOS_PRI_GFX) +#define is_qos_pri_gfx() 1 +#else +#define is_qos_pri_gfx() 0 +#endif + /* QoS version 0.963 for ES2 */ static void qos_init_es2(void) { @@ -1150,30 +1168,57 @@ static void qos_init_es2(void) /* S3C -QoS */ s3c = (struct rcar_s3c *)S3C_BASE; writel(0x80000000, &s3c->s3cadsplcr); - writel(0x1F060504, &s3c->s3crorr); - writel(0x1F060503, &s3c->s3cworr); - + if (is_qos_pri_media()) { + writel(0x1F060302, &s3c->s3crorr); + writel(0x07070302, &s3c->s3cworr); + } else if (is_qos_pri_normal()) { + writel(0x1F060504, &s3c->s3crorr); + writel(0x07070503, &s3c->s3cworr); + } else if (is_qos_pri_gfx()) { + writel(0x1F060606, &s3c->s3crorr); + writel(0x07070606, &s3c->s3cworr); + } /* QoS Control Registers */ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; @@ -1188,7 +1233,7 @@ static void qos_init_es2(void) writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x00828092, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20FA, &s3c_qos->s3cqos3); @@ -1198,7 +1243,7 @@ static void qos_init_es2(void) writel(0x20AA20FA, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); - writel(0x00200808, &s3c->s3carcr11); + writel(0x00310808, &s3c->s3carcr11); /* DBSC -QoS */ /* DBSC0 - Read */ @@ -1235,7 +1280,7 @@ static void qos_init_es2(void) /* Transaction Control (MXI) */ mxi = (struct rcar_mxi *)MXI_BASE; writel(0x00000013, &mxi->mxrtcr); - writel(0x00000013, &mxi->mxwtcr); + writel(0x00000016, &mxi->mxwtcr); writel(0x00B800C0, &mxi->mxsaar0); writel(0x02000800, &mxi->mxsaar1); @@ -1622,7 +1667,7 @@ static void qos_init_es2(void) /* QoS Register (RT-AXI) */ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; - writel(0x00000000, &axi_qos->qosconf); + writel(0x00000001, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index cc0ac6b0bd..fb2de48fbc 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -43,6 +43,11 @@ void set_mux_conf_regs(void) /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_set_bus_num(0); + + /* enable early the console */ + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; if (read_eeprom() < 0) puts("Could not get board ID.\n"); diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index a6bbf6e786..b2eca51ffb 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -35,8 +35,11 @@ config MACH_SUN5I config MACH_SUN6I bool "sun6i (Allwinner A31)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN7I bool "sun7i (Allwinner A20)" @@ -50,14 +53,25 @@ config MACH_SUN7I config MACH_SUN8I_A23 bool "sun8i (Allwinner A23)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN8I_A33 bool "sun8i (Allwinner A33)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + +config MACH_SUN9I + bool "sun9i (Allwinner A80)" + select CPU_V7 + select SUNXI_GEN_SUN6I endchoice @@ -187,6 +201,7 @@ config SYS_CONFIG_NAME default "sun6i" if MACH_SUN6I default "sun7i" if MACH_SUN7I default "sun8i" if MACH_SUN8I + default "sun9i" if MACH_SUN9I config SYS_BOARD default "sunxi" @@ -194,24 +209,8 @@ config SYS_BOARD config SYS_SOC default "sunxi" -config SPL_FEL - bool "SPL/FEL mode support" - depends on SPL - default n - help - This enables support for Fast Early Loader (FEL) mode. This - allows U-Boot to be loaded to the board over USB by the on-chip - boot rom. U-Boot should be sent in two parts: SPL first, with - 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with - 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option - shrinks the amount of SRAM available to SPL, so only enable it if - you need FEL. Note that enabling this option only allows FEL to be - used; it is still possible to boot U-Boot from boot media. U-Boot - SPL detects when it is being loaded using FEL. - config UART0_PORT_F bool "UART0 on MicroSD breakout board" - depends on SPL_FEL default n ---help--- Repurpose the SD card slot for getting access to the UART0 serial @@ -281,6 +280,18 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. +config SPL_NAND_SUPPORT + bool "SPL/NAND mode support" + depends on SPL + default n + ---help--- + This enables support for booting from NAND internal + memory. U-Boot SPL doesn't detect where is it load from, + therefore this option is needed to properly load image from + flash. Option also disables MMC functionality on U-Boot due to + initialization errors encountered, when both controllers are + enabled. + config USB0_VBUS_PIN string "Vbus enable pin for usb0 (otg)" default "" @@ -558,9 +569,6 @@ config GMAC_TX_DELAY config SYS_MALLOC_CLEAR_ON_INIT default n -config NET - default y - config NETDEVICES default y @@ -573,4 +581,10 @@ config DM_SERIAL config DM_USB default y if !USB_MUSB_SUNXI +config CMD_SETEXPR + default y + +config CMD_NET + default y + endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index a650554938..7a42055559 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -10,6 +10,7 @@ F: configs/Cubieboard_defconfig F: configs/Hyundai_A7HD_defconfig F: configs/jesurun_q5_defconfig F: configs/Mele_A1000_defconfig +F: configs/Mele_A1000G_quad_defconfig F: configs/Mele_M3_defconfig F: configs/Mini-X_defconfig F: configs/mk802_defconfig @@ -40,6 +41,8 @@ F: include/configs/sun8i.h F: configs/ga10h_v1_1_defconfig F: configs/Ippo_q8h_v1_2_defconfig F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig +F: include/configs/sun9i.h +F: configs/Merrii_A80_Optimus_defconfig A20-OLINUXINO-LIME BOARD M: FUKAUMI Naoki <naobsd@gmail.com> @@ -61,11 +64,6 @@ M: Paul Kocialkowski <contact@paulk.fr> S: Maintained F: configs/Ampe_A76_defconfig -Astar MID756 BOARD -M: VishnuPatekar <vishnupatekar0510@gmail.com> -S: Maintained -F: configs/Astar_MID756_defconfig - COLOMBUS BOARD M: Maxime Ripard <maxime.ripard@free-electrons.com> S: Maintained @@ -79,6 +77,11 @@ F: include/configs/sun7i.h F: configs/Cubieboard2_defconfig F: configs/Cubietruck_defconfig +ET Q8 V1.6 Tablet BOARD +M: VishnuPatekar <vishnupatekar0510@gmail.com> +S: Maintained +F: configs/Et_q8_v1_6_defconfig + FORFUN-Q88DB TABLET M: Jens Lucius <info@jenslucius.com> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 5f79cc1bb8..f27967bbf4 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -22,6 +22,9 @@ #ifdef CONFIG_AXP221_POWER #include <axp221.h> #endif +#ifdef CONFIG_NAND_SUNXI +#include <nand.h> +#endif #include <asm/arch/clock.h> #include <asm/arch/cpu.h> #include <asm/arch/display.h> @@ -315,6 +318,21 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_NAND +void board_nand_init(void) +{ + unsigned int pin; + static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS; + + /* Configure AHB muxes to connect output pins with NAND controller */ + for (pin = 0; pin < 16; pin++) + sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND); + + for (pin = 0; pin < ARRAY_SIZE(ports); pin++) + sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND); +} +#endif + void i2c_init_board(void) { #ifdef CONFIG_I2C0_ENABLE @@ -530,10 +548,11 @@ int misc_init_r(void) } } +#ifndef CONFIG_MACH_SUN9I ret = sunxi_usb_phy_probe(); if (ret) return ret; - +#endif #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE); #endif diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index 6dd2ffe558..86bd6e9136 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -375,7 +375,7 @@ const omap3_sysinfo sysinfo = { #define MUX_BEAGLE_XM() \ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\ - MUX_VAL(CP(GPMC_WAIT0), (IDIS | PTU | EN | M4)) /*GPIO_63*/\ + MUX_VAL(CP(GPMC_WAIT1), (IDIS | PTU | EN | M4)) /*GPIO_63*/\ MUX_VAL(CP(MMC1_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_129*/\ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h index 2294abec71..df658c5211 100644 --- a/board/ti/beagle_x15/mux_data.h +++ b/board/ti/beagle_x15/mux_data.h @@ -31,8 +31,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ - {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ - {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ + {UART2_CTSN, (FSC | IEN | PTU | PDIS | M2)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (FSC | IEN | PTU | PDIS | M1)}, /* uart2_rtsn.uart3_txd */ {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ |