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-rw-r--r--board/gdsys/405ep/405ep.c114
-rw-r--r--board/gdsys/405ep/405ep.h10
-rw-r--r--board/gdsys/405ep/Kconfig51
-rw-r--r--board/gdsys/405ep/MAINTAINERS12
-rw-r--r--board/gdsys/405ep/Makefile12
-rw-r--r--board/gdsys/405ep/dlvision-10g.c317
-rw-r--r--board/gdsys/405ep/io.c227
-rw-r--r--board/gdsys/405ep/iocon.c673
-rw-r--r--board/gdsys/405ep/neo.c154
9 files changed, 0 insertions, 1570 deletions
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
deleted file mode 100644
index 35fa06a2ee..0000000000
--- a/board/gdsys/405ep/405ep.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/global_data.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#define REFLECTION_TESTPATTERN 0xdede
-#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
-
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-#define REFLECTION_TESTREG reflection_low
-#else
-#define REFLECTION_TESTREG reflection_high
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int get_fpga_state(unsigned dev)
-{
- return gd->arch.fpga_state[dev];
-}
-
-int board_early_init_f(void)
-{
- unsigned k;
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->arch.fpga_state[k] = 0;
-
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks
- * -> ca. 15 us
- */
- mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
- return 0;
-}
-
-int board_early_init_r(void)
-{
- unsigned k;
- unsigned ctr;
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->arch.fpga_state[k] = 0;
-
- /*
- * reset FPGA
- */
- gd405ep_init();
-
- gd405ep_set_fpga_reset(1);
-
- gd405ep_setup_hw();
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
- ctr = 0;
- while (!gd405ep_get_fpga_done(k)) {
- udelay(100000);
- if (ctr++ > 5) {
- gd->arch.fpga_state[k] |=
- FPGA_STATE_DONE_FAILED;
- break;
- }
- }
- }
-
- udelay(10);
-
- gd405ep_set_fpga_reset(0);
-
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
- /*
- * wait for fpga out of reset
- */
- ctr = 0;
- while (1) {
- u16 val;
-
- FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
-
- FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
- if (val == REFLECTION_TESTPATTERN_INV)
- break;
-
- udelay(100000);
- if (ctr++ > 5) {
- gd->arch.fpga_state[k] |=
- FPGA_STATE_REFLECTION_FAILED;
- break;
- }
- }
- }
-
- return 0;
-}
diff --git a/board/gdsys/405ep/405ep.h b/board/gdsys/405ep/405ep.h
deleted file mode 100644
index 5647dbc62b..0000000000
--- a/board/gdsys/405ep/405ep.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __405EP_H_
-#define __405EP_H_
-
-/* functions to be provided by board implementation */
-void gd405ep_init(void);
-void gd405ep_set_fpga_reset(unsigned state);
-void gd405ep_setup_hw(void);
-int gd405ep_get_fpga_done(unsigned fpga);
-
-#endif /* __405EP_H_ */
diff --git a/board/gdsys/405ep/Kconfig b/board/gdsys/405ep/Kconfig
deleted file mode 100644
index 20cb80fc2e..0000000000
--- a/board/gdsys/405ep/Kconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-if TARGET_DLVISION_10G
-
-config SYS_BOARD
- default "405ep"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "dlvision-10g"
-
-endif
-
-if TARGET_IO
-
-config SYS_BOARD
- default "405ep"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "io"
-
-endif
-
-if TARGET_IOCON
-
-config SYS_BOARD
- default "405ep"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "iocon"
-
-endif
-
-if TARGET_NEO
-
-config SYS_BOARD
- default "405ep"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_CONFIG_NAME
- default "neo"
-
-endif
diff --git a/board/gdsys/405ep/MAINTAINERS b/board/gdsys/405ep/MAINTAINERS
deleted file mode 100644
index 14038804b8..0000000000
--- a/board/gdsys/405ep/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-405EP BOARD
-M: Dirk Eibach <eibach@gdsys.de>
-S: Maintained
-F: board/gdsys/405ep/
-F: include/configs/dlvision-10g.h
-F: configs/dlvision-10g_defconfig
-F: include/configs/io.h
-F: configs/io_defconfig
-F: include/configs/iocon.h
-F: configs/iocon_defconfig
-F: include/configs/neo.h
-F: configs/neo_defconfig
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
deleted file mode 100644
index 857ec04fa8..0000000000
--- a/board/gdsys/405ep/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := 405ep.o
-obj-$(CONFIG_NEO) += neo.o
-obj-$(CONFIG_IO) += io.o
-obj-$(CONFIG_IOCON) += iocon.o
-obj-$(CONFIG_DLVISION_10G) += dlvision-10g.o
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
deleted file mode 100644
index b531786653..0000000000
--- a/board/gdsys/405ep/dlvision-10g.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#include "../common/osd.h"
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
-
-#define LATCH2_MC2_PRESENT_N 0x0080
-
-enum {
- UNITTYPE_MAIN = 1<<0,
- UNITTYPE_SERVER = 1<<1,
- UNITTYPE_DISPLAYPORT = 1<<2,
-};
-
-enum {
- HWVER_101 = 0,
- HWVER_110 = 1,
- HWVER_130 = 2,
- HWVER_140 = 3,
- HWVER_150 = 4,
- HWVER_160 = 5,
- HWVER_170 = 6,
-};
-
-enum {
- AUDIO_NONE = 0,
- AUDIO_TX = 1,
- AUDIO_RX = 2,
- AUDIO_RXTX = 3,
-};
-
-enum {
- SYSCLK_156250 = 2,
-};
-
-enum {
- RAM_NONE = 0,
- RAM_DDR2_32 = 1,
- RAM_DDR2_64 = 2,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int misc_init_r(void)
-{
- /*
- * Note: DTT has been removed. Please use UCLASS_THERMAL.
- *
- * startup fans
- *
- * dtt_init();
- */
-
- return 0;
-}
-
-static unsigned int get_hwver(void)
-{
- u16 latch3 = in_le16((void *)LATCH3_BASE);
-
- return latch3 & 0x0003;
-}
-
-static unsigned int get_mc2_present(void)
-{
- u16 latch2 = in_le16((void *)LATCH2_BASE);
-
- return !(latch2 & LATCH2_MC2_PRESENT_N);
-}
-
-static void print_fpga_info(unsigned dev)
-{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- unsigned unit_type;
- unsigned hardware_version;
- unsigned feature_rs232;
- unsigned feature_audio;
- unsigned feature_sysclock;
- unsigned feature_ramconfig;
- unsigned feature_carrier_speed;
- unsigned feature_carriers;
- unsigned feature_video_channels;
- int fpga_state = get_fpga_state(dev);
-
- printf("FPGA%d: ", dev);
-
- FPGA_GET_REG(dev, versions, &versions);
- FPGA_GET_REG(dev, fpga_version, &fpga_version);
- FPGA_GET_REG(dev, fpga_features, &fpga_features);
-
- hardware_version = versions & 0x000f;
-
- if (fpga_state
- && !((hardware_version == HWVER_101)
- && (fpga_state == FPGA_STATE_DONE_FAILED))) {
- puts("not available\n");
- if (fpga_state & FPGA_STATE_DONE_FAILED)
- puts(" Waiting for FPGA-DONE timed out.\n");
- if (fpga_state & FPGA_STATE_REFLECTION_FAILED)
- puts(" FPGA reflection test failed.\n");
- return;
- }
-
- unit_type = (versions >> 4) & 0x000f;
- hardware_version = versions & 0x000f;
- feature_rs232 = fpga_features & (1<<11);
- feature_audio = (fpga_features >> 9) & 0x0003;
- feature_sysclock = (fpga_features >> 7) & 0x0003;
- feature_ramconfig = (fpga_features >> 5) & 0x0003;
- feature_carrier_speed = fpga_features & (1<<4);
- feature_carriers = (fpga_features >> 2) & 0x0003;
- feature_video_channels = fpga_features & 0x0003;
-
- if (unit_type & UNITTYPE_MAIN)
- printf("Mainchannel ");
- else
- printf("Videochannel ");
-
- if (unit_type & UNITTYPE_SERVER)
- printf("Serverside ");
- else
- printf("Userside ");
-
- if (unit_type & UNITTYPE_DISPLAYPORT)
- printf("DisplayPort");
- else
- printf("DVI-DL");
-
- switch (hardware_version) {
- case HWVER_101:
- printf(" HW-Ver 1.01\n");
- break;
-
- case HWVER_110:
- printf(" HW-Ver 1.10-1.20\n");
- break;
-
- case HWVER_130:
- printf(" HW-Ver 1.30\n");
- break;
-
- case HWVER_140:
- printf(" HW-Ver 1.40-1.43\n");
- break;
-
- case HWVER_150:
- printf(" HW-Ver 1.50\n");
- break;
-
- case HWVER_160:
- printf(" HW-Ver 1.60-1.61\n");
- break;
-
- case HWVER_170:
- printf(" HW-Ver 1.70\n");
- break;
-
- default:
- printf(" HW-Ver %d(not supported)\n",
- hardware_version);
- break;
- }
-
- printf(" FPGA V %d.%02d, features:",
- fpga_version / 100, fpga_version % 100);
-
- printf(" %sRS232", feature_rs232 ? "" : "no ");
-
- switch (feature_audio) {
- case AUDIO_NONE:
- printf(", no audio");
- break;
-
- case AUDIO_TX:
- printf(", audio tx");
- break;
-
- case AUDIO_RX:
- printf(", audio rx");
- break;
-
- case AUDIO_RXTX:
- printf(", audio rx+tx");
- break;
-
- default:
- printf(", audio %d(not supported)", feature_audio);
- break;
- }
-
- switch (feature_sysclock) {
- case SYSCLK_156250:
- printf(", clock 156.25 MHz");
- break;
-
- default:
- printf(", clock %d(not supported)", feature_sysclock);
- break;
- }
-
- puts(",\n ");
-
- switch (feature_ramconfig) {
- case RAM_NONE:
- printf("no RAM");
- break;
-
- case RAM_DDR2_32:
- printf("RAM 32 bit DDR2");
- break;
-
- case RAM_DDR2_64:
- printf("RAM 64 bit DDR2");
- break;
-
- default:
- printf("RAM %d(not supported)", feature_ramconfig);
- break;
- }
-
- printf(", %d carrier(s) %s", feature_carriers,
- feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
-
- printf(", %d video channel(s)\n", feature_video_channels);
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- puts("Board: ");
-
- puts("DLVision 10G");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
-
- puts("\n");
-
- return 0;
-}
-
-int last_stage_init(void)
-{
- u16 versions;
-
- FPGA_GET_REG(0, versions, &versions);
-
- print_fpga_info(0);
- if (get_mc2_present())
- print_fpga_info(1);
-
- if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
- return 0;
-
- if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
- osd_probe(0);
-
- if (get_mc2_present() &&
- (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
- osd_probe(1);
-
- return 0;
-}
-
-void gd405ep_init(void)
-{
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
- if (state) {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
- } else {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- }
-}
-
-void gd405ep_setup_hw(void)
-{
- /*
- * set "startup-finished"-gpios
- */
- gpio_write_bit(21, 0);
- gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
- return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
-}
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
deleted file mode 100644
index 1484469bb0..0000000000
--- a/board/gdsys/405ep/io.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-#include <miiphy.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
-#define PHYREG_CONTROL 0
-#define PHYREG_PAGE_ADDRESS 22
-#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
-#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
-
-enum {
- UNITTYPE_CCD_SWITCH = 1,
-};
-
-enum {
- HWVER_100 = 0,
- HWVER_110 = 1,
- HWVER_121 = 2,
- HWVER_122 = 3,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int misc_init_r(void)
-{
- /*
- * Note: DTT has been removed. Please use UCLASS_THERMAL.
- *
- * startup fans
- *
- * dtt_init();
- */
-
- return 0;
-}
-
-int configure_gbit_phy(unsigned char addr)
-{
- unsigned short value;
-
- /* select page 2 */
- if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_PAGE_ADDRESS, 0x0002))
- goto err_out;
- /* disable SGMII autonegotiation */
- if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
- goto err_out;
- /* select page 0 */
- if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_PAGE_ADDRESS, 0x0000))
- goto err_out;
- /* switch from powerdown to normal operation */
- if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
- goto err_out;
- if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
- goto err_out;
- /* reset phy so settings take effect */
- if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
- PHYREG_CONTROL, 0x9140))
- goto err_out;
-
- return 0;
-
-err_out:
- printf("Error writing to the PHY addr=%02x\n", addr);
- return -1;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- puts("Board: CATCenter Io");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
-
- puts("\n");
-
- return 0;
-}
-
-static void print_fpga_info(void)
-{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- unsigned unit_type;
- unsigned hardware_version;
- unsigned feature_channels;
- unsigned feature_expansion;
-
- FPGA_GET_REG(0, versions, &versions);
- FPGA_GET_REG(0, fpga_version, &fpga_version);
- FPGA_GET_REG(0, fpga_features, &fpga_features);
-
- unit_type = (versions & 0xf000) >> 12;
- hardware_version = versions & 0x000f;
- feature_channels = fpga_features & 0x007f;
- feature_expansion = fpga_features & (1<<15);
-
- puts("FPGA: ");
-
- switch (unit_type) {
- case UNITTYPE_CCD_SWITCH:
- printf("CCD-Switch");
- break;
-
- default:
- printf("UnitType %d(not supported)", unit_type);
- break;
- }
-
- switch (hardware_version) {
- case HWVER_100:
- printf(" HW-Ver 1.00\n");
- break;
-
- case HWVER_110:
- printf(" HW-Ver 1.10\n");
- break;
-
- case HWVER_121:
- printf(" HW-Ver 1.21\n");
- break;
-
- case HWVER_122:
- printf(" HW-Ver 1.22\n");
- break;
-
- default:
- printf(" HW-Ver %d(not supported)\n",
- hardware_version);
- break;
- }
-
- printf(" FPGA V %d.%02d, features:",
- fpga_version / 100, fpga_version % 100);
-
- printf(" %d channel(s)", feature_channels);
-
- printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-}
-
-/*
- * setup Gbit PHYs
- */
-int last_stage_init(void)
-{
- unsigned int k;
-
- print_fpga_info();
-
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-
- for (k = 0; k < 32; ++k)
- configure_gbit_phy(k);
-
- /* take fpga serdes blocks out of reset */
- FPGA_SET_REG(0, quad_serdes_reset, 0);
-
- return 0;
-}
-
-void gd405ep_init(void)
-{
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
- if (state) {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
- } else {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- }
-}
-
-void gd405ep_setup_hw(void)
-{
- /*
- * set "startup-finished"-gpios
- */
- gpio_write_bit(21, 0);
- gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
- return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
-}
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
deleted file mode 100644
index 7db0e29ea6..0000000000
--- a/board/gdsys/405ep/iocon.c
+++ /dev/null
@@ -1,673 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#include "../common/osd.h"
-#include "../common/mclink.h"
-#include "../common/phy.h"
-
-#include <i2c.h>
-#include <pca953x.h>
-#include <pca9698.h>
-
-#include <miiphy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
-#define MAX_MUX_CHANNELS 2
-
-enum {
- UNITTYPE_MAIN_SERVER = 0,
- UNITTYPE_MAIN_USER = 1,
- UNITTYPE_VIDEO_SERVER = 2,
- UNITTYPE_VIDEO_USER = 3,
-};
-
-enum {
- HWVER_100 = 0,
- HWVER_104 = 1,
- HWVER_110 = 2,
- HWVER_120 = 3,
- HWVER_200 = 4,
- HWVER_210 = 5,
- HWVER_220 = 6,
- HWVER_230 = 7,
-};
-
-enum {
- FPGA_HWVER_200 = 0,
- FPGA_HWVER_210 = 1,
-};
-
-enum {
- COMPRESSION_NONE = 0,
- COMPRESSION_TYPE1_DELTA = 1,
- COMPRESSION_TYPE1_TYPE2_DELTA = 3,
-};
-
-enum {
- AUDIO_NONE = 0,
- AUDIO_TX = 1,
- AUDIO_RX = 2,
- AUDIO_RXTX = 3,
-};
-
-enum {
- SYSCLK_147456 = 0,
-};
-
-enum {
- RAM_DDR2_32 = 0,
- RAM_DDR3_32 = 1,
-};
-
-enum {
- CARRIER_SPEED_1G = 0,
- CARRIER_SPEED_2_5G = 1,
-};
-
-enum {
- MCFPGA_DONE = 1 << 0,
- MCFPGA_INIT_N = 1 << 1,
- MCFPGA_PROGRAM_N = 1 << 2,
- MCFPGA_UPDATE_ENABLE_N = 1 << 3,
- MCFPGA_RESET_N = 1 << 4,
-};
-
-enum {
- GPIO_MDC = 1 << 14,
- GPIO_MDIO = 1 << 15,
-};
-
-unsigned int mclink_fpgacount;
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
-{
- int res;
-
- switch (fpga) {
- case 0:
- out_le16(reg, data);
- break;
- default:
- res = mclink_send(fpga - 1, regoff, data);
- if (res < 0) {
- printf("mclink_send reg %02lx data %04x returned %d\n",
- regoff, data, res);
- return res;
- }
- break;
- }
-
- return 0;
-}
-
-int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
-{
- int res;
-
- switch (fpga) {
- case 0:
- *data = in_le16(reg);
- break;
- default:
- if (fpga > mclink_fpgacount)
- return -EINVAL;
- res = mclink_receive(fpga - 1, regoff, data);
- if (res < 0) {
- printf("mclink_receive reg %02lx returned %d\n",
- regoff, res);
- return res;
- }
- }
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- puts("Board: ");
-
- puts("IoCon");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
-
- puts("\n");
-
- return 0;
-}
-
-static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
-{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- unsigned unit_type;
- unsigned hardware_version;
- unsigned feature_compression;
- unsigned feature_osd;
- unsigned feature_audio;
- unsigned feature_sysclock;
- unsigned feature_ramconfig;
- unsigned feature_carrier_speed;
- unsigned feature_carriers;
- unsigned feature_video_channels;
-
- int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM;
-
- FPGA_GET_REG(fpga, versions, &versions);
- FPGA_GET_REG(fpga, fpga_version, &fpga_version);
- FPGA_GET_REG(fpga, fpga_features, &fpga_features);
-
- unit_type = (versions & 0xf000) >> 12;
- feature_compression = (fpga_features & 0xe000) >> 13;
- feature_osd = fpga_features & (1<<11);
- feature_audio = (fpga_features & 0x0600) >> 9;
- feature_sysclock = (fpga_features & 0x0180) >> 7;
- feature_ramconfig = (fpga_features & 0x0060) >> 5;
- feature_carrier_speed = fpga_features & (1<<4);
- feature_carriers = (fpga_features & 0x000c) >> 2;
- feature_video_channels = fpga_features & 0x0003;
-
- if (legacy)
- printf("legacy ");
-
- switch (unit_type) {
- case UNITTYPE_MAIN_USER:
- printf("Mainchannel");
- break;
-
- case UNITTYPE_VIDEO_USER:
- printf("Videochannel");
- break;
-
- default:
- printf("UnitType %d(not supported)", unit_type);
- break;
- }
-
- if (unit_type == UNITTYPE_MAIN_USER) {
- if (legacy)
- hardware_version =
- (in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
- else
- hardware_version =
- (!!pca9698_get_value(0x20, 24) << 0)
- | (!!pca9698_get_value(0x20, 25) << 1)
- | (!!pca9698_get_value(0x20, 26) << 2)
- | (!!pca9698_get_value(0x20, 27) << 3);
- switch (hardware_version) {
- case HWVER_100:
- printf(" HW-Ver 1.00,");
- break;
-
- case HWVER_104:
- printf(" HW-Ver 1.04,");
- break;
-
- case HWVER_110:
- printf(" HW-Ver 1.10,");
- break;
-
- case HWVER_120:
- printf(" HW-Ver 1.20-1.21,");
- break;
-
- case HWVER_200:
- printf(" HW-Ver 2.00,");
- break;
-
- case HWVER_210:
- printf(" HW-Ver 2.10,");
- break;
-
- case HWVER_220:
- printf(" HW-Ver 2.20,");
- break;
-
- case HWVER_230:
- printf(" HW-Ver 2.30,");
- break;
-
- default:
- printf(" HW-Ver %d(not supported),",
- hardware_version);
- break;
- }
- if (rgmii2_present)
- printf(" RGMII2,");
- }
-
- if (unit_type == UNITTYPE_VIDEO_USER) {
- hardware_version = versions & 0x000f;
- switch (hardware_version) {
- case FPGA_HWVER_200:
- printf(" HW-Ver 2.00,");
- break;
-
- case FPGA_HWVER_210:
- printf(" HW-Ver 2.10,");
- break;
-
- default:
- printf(" HW-Ver %d(not supported),",
- hardware_version);
- break;
- }
- }
-
- printf(" FPGA V %d.%02d\n features:",
- fpga_version / 100, fpga_version % 100);
-
-
- switch (feature_compression) {
- case COMPRESSION_NONE:
- printf(" no compression");
- break;
-
- case COMPRESSION_TYPE1_DELTA:
- printf(" type1-deltacompression");
- break;
-
- case COMPRESSION_TYPE1_TYPE2_DELTA:
- printf(" type1-deltacompression, type2-inlinecompression");
- break;
-
- default:
- printf(" compression %d(not supported)", feature_compression);
- break;
- }
-
- printf(", %sosd", feature_osd ? "" : "no ");
-
- switch (feature_audio) {
- case AUDIO_NONE:
- printf(", no audio");
- break;
-
- case AUDIO_TX:
- printf(", audio tx");
- break;
-
- case AUDIO_RX:
- printf(", audio rx");
- break;
-
- case AUDIO_RXTX:
- printf(", audio rx+tx");
- break;
-
- default:
- printf(", audio %d(not supported)", feature_audio);
- break;
- }
-
- puts(",\n ");
-
- switch (feature_sysclock) {
- case SYSCLK_147456:
- printf("clock 147.456 MHz");
- break;
-
- default:
- printf("clock %d(not supported)", feature_sysclock);
- break;
- }
-
- switch (feature_ramconfig) {
- case RAM_DDR2_32:
- printf(", RAM 32 bit DDR2");
- break;
-
- case RAM_DDR3_32:
- printf(", RAM 32 bit DDR3");
- break;
-
- default:
- printf(", RAM %d(not supported)", feature_ramconfig);
- break;
- }
-
- printf(", %d carrier(s) %s", feature_carriers,
- feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
-
- printf(", %d video channel(s)\n", feature_video_channels);
-}
-
-int last_stage_init(void)
-{
- int slaves;
- unsigned int k;
- unsigned int mux_ch;
- unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
- int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
- u16 fpga_features;
- int feature_carrier_speed;
- bool ch0_rgmii2_present = false;
-
- FPGA_GET_REG(0, fpga_features, &fpga_features);
- feature_carrier_speed = fpga_features & (1<<4);
-
- if (!legacy) {
- /* Turn on Parade DP501 */
- pca9698_direction_output(0x20, 9, 1);
-
- ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
- }
-
- /* wait for FPGA done; then reset FPGA */
- for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
- unsigned int ctr = 0;
-
- if (i2c_probe(mclink_controllers[k]))
- continue;
-
- while (!(pca953x_get_val(mclink_controllers[k])
- & MCFPGA_DONE)) {
- udelay(100000);
- if (ctr++ > 5) {
- printf("no done for mclink_controller %d\n", k);
- break;
- }
- }
-
- pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
- pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
- udelay(10);
- pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
- MCFPGA_RESET_N);
- }
-
- if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
- for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
- if ((mux_ch == 1) && !ch0_rgmii2_present)
- continue;
-
- setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
- }
- }
-
- /* give slave-PLLs and Parade DP501 some time to be up and running */
- udelay(500000);
-
- mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
- slaves = mclink_probe();
- mclink_fpgacount = 0;
-
- print_fpga_info(0, ch0_rgmii2_present);
- osd_probe(0);
-
- if (slaves <= 0)
- return 0;
-
- mclink_fpgacount = slaves;
-
- for (k = 1; k <= slaves; ++k) {
- FPGA_GET_REG(k, fpga_features, &fpga_features);
- feature_carrier_speed = fpga_features & (1<<4);
-
- print_fpga_info(k, false);
- osd_probe(k);
- if (feature_carrier_speed == CARRIER_SPEED_1G) {
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, bb_miiphy_buses[k].name,
- MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
- setup_88e1518(bb_miiphy_buses[k].name, 0);
- }
- }
-
- return 0;
-}
-
-/*
- * provide access to fpga gpios (for I2C bitbang)
- * (these may look all too simple but make iocon.h much more readable)
- */
-void fpga_gpio_set(unsigned int bus, int pin)
-{
- FPGA_SET_REG(bus, gpio.set, pin);
-}
-
-void fpga_gpio_clear(unsigned int bus, int pin)
-{
- FPGA_SET_REG(bus, gpio.clear, pin);
-}
-
-int fpga_gpio_get(unsigned int bus, int pin)
-{
- u16 val;
-
- FPGA_GET_REG(bus, gpio.read, &val);
-
- return val & pin;
-}
-
-void gd405ep_init(void)
-{
- unsigned int k;
-
- if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
- for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
- } else {
- pca9698_direction_output(0x20, 4, 1);
- }
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
- int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-
- if (legacy) {
- if (state) {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
- } else {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- }
- } else {
- pca9698_set_value(0x20, 4, state ? 0 : 1);
- }
-}
-
-void gd405ep_setup_hw(void)
-{
- /*
- * set "startup-finished"-gpios
- */
- gpio_write_bit(21, 0);
- gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
- int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-
- if (legacy)
- return in_le16((void *)LATCH2_BASE)
- & CONFIG_SYS_FPGA_DONE(fpga);
- else
- return pca9698_get_value(0x20, 20);
-}
-
-/*
- * FPGA MII bitbang implementation
- */
-
-struct fpga_mii {
- unsigned fpga;
- int mdio;
-} fpga_mii[] = {
- { 0, 1},
- { 1, 1},
- { 2, 1},
- { 3, 1},
-};
-
-static int mii_dummy_init(struct bb_miiphy_bus *bus)
-{
- return 0;
-}
-
-static int mii_mdio_active(struct bb_miiphy_bus *bus)
-{
- struct fpga_mii *fpga_mii = bus->priv;
-
- if (fpga_mii->mdio)
- FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
- else
- FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
-
- return 0;
-}
-
-static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
-{
- struct fpga_mii *fpga_mii = bus->priv;
-
- FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-
- return 0;
-}
-
-static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
- struct fpga_mii *fpga_mii = bus->priv;
-
- if (v)
- FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
- else
- FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
-
- fpga_mii->mdio = v;
-
- return 0;
-}
-
-static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
- u16 gpio;
- struct fpga_mii *fpga_mii = bus->priv;
-
- FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
-
- *v = ((gpio & GPIO_MDIO) != 0);
-
- return 0;
-}
-
-static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
- struct fpga_mii *fpga_mii = bus->priv;
-
- if (v)
- FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
- else
- FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
-
- return 0;
-}
-
-static int mii_delay(struct bb_miiphy_bus *bus)
-{
- udelay(1);
-
- return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- {
- .name = "board0",
- .init = mii_dummy_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &fpga_mii[0],
- },
- {
- .name = "board1",
- .init = mii_dummy_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &fpga_mii[1],
- },
- {
- .name = "board2",
- .init = mii_dummy_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &fpga_mii[2],
- },
- {
- .name = "board3",
- .init = mii_dummy_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &fpga_mii[3],
- },
-};
-
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
- sizeof(bb_miiphy_buses[0]);
diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c
deleted file mode 100644
index ad88af2d46..0000000000
--- a/board/gdsys/405ep/neo.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * (C) Copyright 2011
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
-enum {
- UNITTYPE_CCX16 = 1,
- UNITTYPE_CCIP216 = 2,
-};
-
-enum {
- HWVER_300 = 3,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int misc_init_r(void)
-{
- /*
- * Note: DTT has been removed. Please use UCLASS_THERMAL.
- *
- * startup fans
- *
- * dtt_init();
- */
-
- return 0;
-}
-
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- puts("Board: CATCenter Neo");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
-
- puts("\n");
-
- return 0;
-}
-
-static void print_fpga_info(void)
-{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- int fpga_state = get_fpga_state(0);
- unsigned unit_type;
- unsigned hardware_version;
- unsigned feature_channels;
-
- puts("FPGA: ");
- if (fpga_state & FPGA_STATE_DONE_FAILED) {
- printf(" done timed out\n");
- return;
- }
-
- if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
- printf(" refelectione test failed\n");
- return;
- }
-
- FPGA_GET_REG(0, versions, &versions);
- FPGA_GET_REG(0, fpga_version, &fpga_version);
- FPGA_GET_REG(0, fpga_features, &fpga_features);
-
- unit_type = (versions & 0xf000) >> 12;
- hardware_version = versions & 0x000f;
- feature_channels = fpga_features & 0x007f;
-
- switch (unit_type) {
- case UNITTYPE_CCX16:
- printf("CCX-Switch");
- break;
-
- default:
- printf("UnitType %d(not supported)", unit_type);
- break;
- }
-
- switch (hardware_version) {
- case HWVER_300:
- printf(" HW-Ver 3.00-3.12\n");
- break;
-
- default:
- printf(" HW-Ver %d(not supported)\n",
- hardware_version);
- break;
- }
-
- printf(" FPGA V %d.%02d, features:",
- fpga_version / 100, fpga_version % 100);
-
- printf(" %d channel(s)\n", feature_channels);
-}
-
-int last_stage_init(void)
-{
- print_fpga_info();
-
- return 0;
-}
-
-void gd405ep_init(void)
-{
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
- if (state) {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
- } else {
- out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
- out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- }
-}
-
-void gd405ep_setup_hw(void)
-{
- /*
- * set "startup-finished"-gpios
- */
- gpio_write_bit(21, 0);
- gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
- /*
- * Neo hardware has no FPGA-DONE GPIO
- */
- return 1;
-}
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