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-rw-r--r--board/esd/pmc440/Kconfig12
-rw-r--r--board/esd/pmc440/MAINTAINERS6
-rw-r--r--board/esd/pmc440/Makefile10
-rw-r--r--board/esd/pmc440/cmd_pmc440.c554
-rw-r--r--board/esd/pmc440/config.mk16
-rw-r--r--board/esd/pmc440/fpga.c446
-rw-r--r--board/esd/pmc440/fpga.h31
-rw-r--r--board/esd/pmc440/init.S69
-rw-r--r--board/esd/pmc440/pmc440.c906
-rw-r--r--board/esd/pmc440/pmc440.h135
-rw-r--r--board/esd/pmc440/sdram.c140
11 files changed, 0 insertions, 2325 deletions
diff --git a/board/esd/pmc440/Kconfig b/board/esd/pmc440/Kconfig
deleted file mode 100644
index df8bd65ab7..0000000000
--- a/board/esd/pmc440/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PMC440
-
-config SYS_BOARD
- default "pmc440"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "PMC440"
-
-endif
diff --git a/board/esd/pmc440/MAINTAINERS b/board/esd/pmc440/MAINTAINERS
deleted file mode 100644
index 32fb9baeef..0000000000
--- a/board/esd/pmc440/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PMC440 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/pmc440/
-F: include/configs/PMC440.h
-F: configs/PMC440_defconfig
diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile
deleted file mode 100644
index 708e9d138e..0000000000
--- a/board/esd/pmc440/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pmc440.o cmd_pmc440.o sdram.o fpga.o \
- ../common/cmd_loadpci.o
-extra-y += init.o
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
deleted file mode 100644
index b7cd595362..0000000000
--- a/board/esd/pmc440/cmd_pmc440.c
+++ /dev/null
@@ -1,554 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/processor.h>
-#if defined(CONFIG_LOGBUFFER)
-#include <logbuff.h>
-#endif
-
-#include "pmc440.h"
-
-int is_monarch(void);
-int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt);
-int eeprom_write_enable(unsigned dev_addr, int state);
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_BSP)
-
-static int got_fifoirq;
-static int got_hcirq;
-
-int fpga_interrupt(u32 arg)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
- int rc = -1; /* not for us */
- u32 status = FPGA_IN32(&fpga->status);
-
- /* check for interrupt from fifo module */
- if (status & STATUS_FIFO_ISF) {
- /* disable this int source */
- FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
- rc = 0;
- got_fifoirq = 1; /* trigger backend */
- }
-
- if (status & STATUS_HOST_ISF) {
- FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
- rc = 0;
- got_hcirq = 1;
- }
-
- return rc;
-}
-
-int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- got_hcirq = 0;
-
- FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
- FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
-
- irq_install_handler(IRQ0_FPGA,
- (interrupt_handler_t *)fpga_interrupt,
- fpga);
-
- FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
-
- while (!got_hcirq) {
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- break;
- }
- }
- if (got_hcirq)
- printf("Got interrupt!\n");
-
- FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
- irq_free_handler(IRQ0_FPGA);
- return 0;
-}
-U_BOOT_CMD(
- waithci, 1, 1, do_waithci,
- "Wait for host control interrupt",
- ""
-);
-
-void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
-{
- u32 ctrl;
-
- while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
- printf("%5d %d %3d %08x",
- (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
- FPGA_IN32(&fpga->fifo[f].data));
- if (ctrl & FIFO_OVERFLOW) {
- printf(" OVERFLOW\n");
- FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
- } else
- printf("\n");
- }
-}
-
-int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
- int i;
- int n = 0;
- u32 ctrl, data, f;
- char str[] = "\\|/-";
- int abort = 0;
- int count = 0;
- int count2 = 0;
-
- switch (argc) {
- case 1:
- /* print all fifos status information */
- printf("fifo level status\n");
- printf("______________________________\n");
- for (i=0; i<FIFO_COUNT; i++) {
- ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
- printf(" %d %3d %s%s%s %s\n",
- i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
- ctrl & FIFO_FULL ? "FULL " : "",
- ctrl & FIFO_EMPTY ? "EMPTY " : "",
- ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
- ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
- }
- break;
-
- case 2:
- /* completely read out fifo 'n' */
- if (!strcmp(argv[1],"read")) {
- printf(" # fifo level data\n");
- printf("______________________________\n");
-
- for (i=0; i<FIFO_COUNT; i++)
- dump_fifo(fpga, i, &n);
-
- } else if (!strcmp(argv[1],"wait")) {
- got_fifoirq = 0;
-
- irq_install_handler(IRQ0_FPGA,
- (interrupt_handler_t *)fpga_interrupt,
- fpga);
-
- printf(" # fifo level data\n");
- printf("______________________________\n");
-
- /* enable all fifo interrupts */
- FPGA_OUT32(&fpga->hostctrl,
- HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
- for (i=0; i<FIFO_COUNT; i++) {
- /* enable interrupts from all fifos */
- FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
- }
-
- while (1) {
- /* wait loop */
- while (!got_fifoirq) {
- count++;
- if (!(count % 100)) {
- count2++;
- putc(0x08); /* backspace */
- putc(str[count2 % 4]);
- }
-
- /* Abort if ctrl-c was pressed */
- if ((abort = ctrlc())) {
- puts("\nAbort\n");
- break;
- }
- udelay(1000);
- }
- if (abort)
- break;
-
- /* simple fifo backend */
- if (got_fifoirq) {
- for (i=0; i<FIFO_COUNT; i++)
- dump_fifo(fpga, i, &n);
-
- got_fifoirq = 0;
- /* unmask global fifo irq */
- FPGA_OUT32(&fpga->hostctrl,
- HOSTCTRL_FIFOIE_GATE |
- HOSTCTRL_FIFOIE_FLAG);
- }
- }
-
- /* disable all fifo interrupts */
- FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
- for (i=0; i<FIFO_COUNT; i++)
- FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
-
- irq_free_handler(IRQ0_FPGA);
-
- } else {
- printf("Usage:\nfifo %s\n", cmdtp->help);
- return 1;
- }
- break;
-
- case 4:
- case 5:
- if (!strcmp(argv[1],"write")) {
- /* get fifo number or fifo address */
- f = simple_strtoul(argv[2], NULL, 16);
-
- /* data paramter */
- data = simple_strtoul(argv[3], NULL, 16);
-
- /* get optional count parameter */
- n = 1;
- if (argc >= 5)
- n = (int)simple_strtoul(argv[4], NULL, 10);
-
- if (f < FIFO_COUNT) {
- printf("writing %d x %08x to fifo %d\n",
- n, data, f);
- for (i=0; i<n; i++)
- FPGA_OUT32(&fpga->fifo[f].data, data);
- } else {
- printf("writing %d x %08x to fifo port at "
- "address %08x\n",
- n, data, f);
- for (i=0; i<n; i++)
- out_be32((void *)f, data);
- }
- } else {
- printf("Usage:\nfifo %s\n", cmdtp->help);
- return 1;
- }
- break;
-
- default:
- printf("Usage:\nfifo %s\n", cmdtp->help);
- return 1;
- }
- return 0;
-}
-U_BOOT_CMD(
- fifo, 5, 1, do_fifo,
- "Fifo module operations",
- "wait\nfifo read\n"
- "fifo write fifo(0..3) data [cnt=1]\n"
- "fifo write address(>=4) data [cnt=1]\n"
- " - without arguments: print all fifo's status\n"
- " - with 'wait' argument: interrupt driven read from all fifos\n"
- " - with 'read' argument: read current contents from all fifos\n"
- " - with 'write' argument: write 'data' 'cnt' times to "
- "'fifo' or 'address'"
-);
-
-int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong sdsdp[5];
- ulong delay;
- int count=16;
-
- if (argc < 2) {
- printf("Usage:\nsbe %s\n", cmdtp->help);
- return -1;
- }
-
- if (argc > 1) {
- if (!strcmp(argv[1], "400")) {
- /* PLB=133MHz, PLB/PCI=3 */
- printf("Bootstrapping for 400MHz\n");
- sdsdp[0]=0x8678624e;
- sdsdp[1]=0x095fa030;
- sdsdp[2]=0x40082350;
- sdsdp[3]=0x0d050000;
- } else if (!strcmp(argv[1], "533")) {
- /* PLB=133MHz, PLB/PCI=3 */
- printf("Bootstrapping for 533MHz\n");
- sdsdp[0]=0x87788252;
- sdsdp[1]=0x095fa030;
- sdsdp[2]=0x40082350;
- sdsdp[3]=0x0d050000;
- } else if (!strcmp(argv[1], "667")) {
- /* PLB=133MHz, PLB/PCI=3 */
- printf("Bootstrapping for 667MHz\n");
- sdsdp[0]=0x8778a256;
- sdsdp[1]=0x095fa030;
- sdsdp[2]=0x40082350;
- sdsdp[3]=0x0d050000;
- } else {
- printf("Usage:\nsbe %s\n", cmdtp->help);
- return -1;
- }
- }
-
- if (argc > 2) {
- sdsdp[4] = 0;
- if (argv[2][0]=='1')
- sdsdp[4]=0x19750100;
- else if (argv[2][0]=='0')
- sdsdp[4]=0x19750000;
- if (sdsdp[4])
- count += 4;
- }
-
- if (argc > 3) {
- delay = simple_strtoul(argv[3], NULL, 10);
- if (delay > 20)
- delay = 20;
- sdsdp[4] |= delay;
- }
-
- printf("Writing boot EEPROM ...\n");
- if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
- 0, (uchar*)sdsdp, count) != 0)
- printf("bootstrap_eeprom_write failed\n");
- else
- printf("done (dump via 'i2c md 52 0.1 14')\n");
-
- return 0;
-}
-U_BOOT_CMD(
- sbe, 4, 0, do_setup_bootstrap_eeprom,
- "setup bootstrap eeprom",
- "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
-);
-
-#if defined(CONFIG_PRAM)
-#include <environment.h>
-#include <search.h>
-#include <errno.h>
-
-int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 pram, nextbase, base;
- char *v;
- u32 param;
- ulong *lptr;
-
- env_t *envp;
- char *res;
- int len;
-
- v = getenv("pram");
- if (v)
- pram = simple_strtoul(v, NULL, 10);
- else {
- printf("Error: pram undefined. Please define pram in KiB\n");
- return 1;
- }
-
- base = (u32)gd->ram_size;
-#if defined(CONFIG_LOGBUFFER)
- base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
-#endif
- /*
- * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
- */
- param = base - (pram << 10);
- printf("PARAM: @%08x\n", param);
- debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base);
-
- /* clear entire PA ram */
- memset((void*)param, 0, (pram << 10));
-
- /* reserve 4k for pointer field */
- nextbase = base - 4096;
- lptr = (ulong*)(base);
-
- /*
- * *(--lptr) = item_size;
- * *(--lptr) = base - item_base = distance from field top;
- */
-
- /* env is first (4k aligned) */
- nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
- envp = (env_t *)nextbase;
- res = (char *)envp->data;
- len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
- if (len < 0) {
- error("Cannot export environment: errno = %d\n", errno);
- return 1;
- }
- envp->crc = crc32(0, envp->data, ENV_SIZE);
-
- *(--lptr) = CONFIG_ENV_SIZE; /* size */
- *(--lptr) = base - nextbase; /* offset | type=0 */
-
- /* free section */
- *(--lptr) = nextbase - param; /* size */
- *(--lptr) = (base - param) | 126; /* offset | type=126 */
-
- /* terminate pointer field */
- *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
- *(--lptr) = 0; /* offset=0 -> terminator */
- return 0;
-}
-U_BOOT_CMD(
- painit, 1, 1, do_painit,
- "prepare PciAccess system",
- ""
-);
-#endif /* CONFIG_PRAM */
-
-int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- in_be32((void*)CONFIG_SYS_RESET_BASE);
- return 0;
-}
-U_BOOT_CMD(
- selfreset, 1, 1, do_selfreset,
- "assert self-reset# signal",
- ""
-);
-
-int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- /* requiers bootet FPGA and PLD_IOEN_N active */
- if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
- printf("Error: resetout requires a bootet FPGA\n");
- return -1;
- }
-
- if (argc > 1) {
- if (argv[1][0] == '0') {
- /* assert */
- printf("PMC-RESETOUT# asserted\n");
- FPGA_OUT32(&fpga->hostctrl,
- HOSTCTRL_PMCRSTOUT_GATE);
- } else {
- /* deassert */
- printf("PMC-RESETOUT# deasserted\n");
- FPGA_OUT32(&fpga->hostctrl,
- HOSTCTRL_PMCRSTOUT_GATE |
- HOSTCTRL_PMCRSTOUT_FLAG);
- }
- } else {
- printf("PMC-RESETOUT# is %s\n",
- FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
- "inactive" : "active");
- }
-
- return 0;
-}
-U_BOOT_CMD(
- resetout, 2, 1, do_resetout,
- "assert PMC-RESETOUT# signal",
- ""
-);
-
-int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (is_monarch()) {
- printf("This command is only supported in non-monarch mode\n");
- return -1;
- }
-
- if (argc > 1) {
- if (argv[1][0] == '0') {
- /* assert */
- printf("inta# asserted\n");
- out_be32((void*)GPIO1_TCR,
- in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
- } else {
- /* deassert */
- printf("inta# deasserted\n");
- out_be32((void*)GPIO1_TCR,
- in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
- }
- } else {
- printf("inta# is %s\n",
- in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
- "active" : "inactive");
- }
- return 0;
-}
-U_BOOT_CMD(
- inta, 2, 1, do_inta,
- "Assert/Deassert or query INTA# state in non-monarch mode",
- ""
-);
-
-/* test-only */
-int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong pciaddr;
-
- if (argc > 1) {
- pciaddr = simple_strtoul(argv[1], NULL, 16);
-
- pciaddr &= 0xf0000000;
-
- /* map PCI address at 0xc0000000 in PLB space */
-
- /* PMM1 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1MA, 0x00000000);
- /* PMM1 Local Address */
- out32r(PCIL0_PMM1LA, 0xc0000000);
- /* PMM1 PCI Low Address */
- out32r(PCIL0_PMM1PCILA, pciaddr);
- /* PMM1 PCI High Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000);
- /* 256MB + No prefetching, and enable region */
- out32r(PCIL0_PMM1MA, 0xf0000001);
- } else {
- printf("Usage:\npmm %s\n", cmdtp->help);
- }
- return 0;
-}
-U_BOOT_CMD(
- pmm, 2, 1, do_pmm,
- "Setup pmm[1] registers",
- "<pciaddr> (pciaddr will be aligned to 256MB)"
-);
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int query = argc == 1;
- int state = 0;
-
- if (query) {
- /* Query write access state. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
- if (state < 0) {
- puts("Query of write access state failed.\n");
- } else {
- printf("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
- state = 0;
- }
- } else {
- if ('0' == argv[1][0]) {
- /* Disable write access. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
- } else {
- /* Enable write access. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0) {
- puts("Setup of write access state failed.\n");
- }
- }
-
- return state;
-}
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- ""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-#endif /* CONFIG_CMD_BSP */
diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk
deleted file mode 100644
index 9cb071e45b..0000000000
--- a/board/esd/pmc440/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
deleted file mode 100644
index f876da855b..0000000000
--- a/board/esd/pmc440/fpga.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * (C) Copyright 2007
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <spartan2.h>
-#include <spartan3.h>
-#include <command.h>
-#include "fpga.h"
-#include "pmc440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_FPGA)
-
-#define USE_SP_CODE
-
-#ifdef USE_SP_CODE
-xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
- fpga_pre_config_fn,
- fpga_pgm_fn,
- fpga_init_fn,
- NULL, /* err */
- fpga_done_fn,
- fpga_clk_fn,
- fpga_cs_fn,
- fpga_wr_fn,
- NULL, /* rdata */
- fpga_wdata_fn,
- fpga_busy_fn,
- fpga_abort_fn,
- fpga_post_config_fn,
-};
-#else
-xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
- fpga_pre_config_fn,
- fpga_pgm_fn,
- fpga_clk_fn,
- fpga_init_fn,
- fpga_done_fn,
- fpga_wr_fn,
- fpga_post_config_fn,
-};
-#endif
-
-xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
- ngcc_fpga_pre_config_fn,
- ngcc_fpga_pgm_fn,
- ngcc_fpga_clk_fn,
- ngcc_fpga_init_fn,
- ngcc_fpga_done_fn,
- ngcc_fpga_wr_fn,
- ngcc_fpga_post_config_fn
-};
-
-xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- XILINX_XC3S1200E_DESC(
-#ifdef USE_SP_CODE
- slave_parallel,
-#else
- slave_serial,
-#endif
- (void *)&pmc440_fpga_fns,
- 0),
- XILINX_XC2S200_DESC(
- slave_serial,
- (void *)&ngcc_fpga_fns,
- 0)
-};
-
-
-/*
- * Set the active-low FPGA reset signal.
- */
-void fpga_reset(int assert)
-{
- debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
- if (assert) {
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
- debug("asserted\n");
- } else {
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
- debug("deasserted\n");
- }
-}
-
-
-/*
- * Initialize the SelectMap interface. We assume that the mode and the
- * initial state of all of the port pins have already been set!
- */
-void fpga_serialslave_init(void)
-{
- debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
- __LINE__);
- fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
-}
-
-
-/*
- * Set the FPGA's active-low SelectMap program line to the specified level
- */
-int fpga_pgm_fn(int assert, int flush, int cookie)
-{
- debug("%s:%d: FPGA PROGRAM ",
- __FUNCTION__, __LINE__);
-
- if (assert) {
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
- debug("asserted\n");
- } else {
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
- debug("deasserted\n");
- }
- return assert;
-}
-
-
-/*
- * Test the state of the active-low FPGA INIT line. Return 1 on INIT
- * asserted (low).
- */
-int fpga_init_fn(int cookie)
-{
- if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
- return 0;
- else
- return 1;
-}
-
-#ifdef USE_SP_CODE
-int fpga_abort_fn(int cookie)
-{
- return 0;
-}
-
-
-int fpga_cs_fn(int assert_cs, int flush, int cookie)
-{
- return assert_cs;
-}
-
-
-int fpga_busy_fn(int cookie)
-{
- return 1;
-}
-#endif
-
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-int fpga_done_fn(int cookie)
-{
- if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
- return 1;
- else
- return 0;
-}
-
-
-/*
- * FPGA pre-configuration function. Just make sure that
- * FPGA reset is asserted to keep the FPGA from starting up after
- * configuration.
- */
-int fpga_pre_config_fn(int cookie)
-{
- debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
- fpga_reset(true);
-
- /* release init# */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
- /* disable PLD IOs */
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
- return 0;
-}
-
-
-/*
- * FPGA post configuration function. Blip the FPGA reset line and then see if
- * the FPGA appears to be running.
- */
-int fpga_post_config_fn(int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
- int rc=0;
- char *s;
-
- debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
-
- /* enable PLD0..7 pins */
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
-
- fpga_reset(true);
- udelay (100);
- fpga_reset(false);
- udelay (100);
-
- FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
-
- /* NGCC/CANDES only: enable ledlink */
- if ((s = getenv("bd_type")) &&
- ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes"))))
- FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
-
- return rc;
-}
-
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- if (assert_clk)
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
- else
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
-
- return assert_clk;
-}
-
-
-int fpga_wr_fn(int assert_write, int flush, int cookie)
-{
- if (assert_write)
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
- else
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
-
- return assert_write;
-}
-
-#ifdef USE_SP_CODE
-int fpga_wdata_fn(uchar data, int flush, int cookie)
-{
- uchar val = data;
- ulong or = in_be32((void*)GPIO1_OR);
- int i = 7;
- do {
- /* Write data */
- if (val & 0x80)
- or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
- else
- or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
-
- out_be32((void*)GPIO1_OR, or);
-
- /* Assert the clock */
- or |= GPIO1_FPGA_CLK;
- out_be32((void*)GPIO1_OR, or);
- val <<= 1;
- i --;
- } while (i > 0);
-
- /* Write last data bit (the 8th clock comes from the sp_load() code */
- if (val & 0x80)
- or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
- else
- or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
-
- out_be32((void*)GPIO1_OR, or);
-
- return 0;
-}
-#endif
-
-#define NGCC_FPGA_PRG CLOCK_EN
-#define NGCC_FPGA_DATA RESET_OUT
-#define NGCC_FPGA_DONE CLOCK_IN
-#define NGCC_FPGA_INIT IRIGB_R_IN
-#define NGCC_FPGA_CLK CLOCK_OUT
-
-void ngcc_fpga_serialslave_init(void)
-{
- debug("%s:%d: Initialize serial slave interface\n",
- __FUNCTION__, __LINE__);
-
- /* make sure program pin is inactive */
- ngcc_fpga_pgm_fn(false, false, 0);
-}
-
-/*
- * Set the active-low FPGA reset signal.
- */
-void ngcc_fpga_reset(int assert)
-{
- debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
-
- if (assert) {
- FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
- debug("asserted\n");
- } else {
- FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
- debug("deasserted\n");
- }
-}
-
-
-/*
- * Set the FPGA's active-low SelectMap program line to the specified level
- */
-int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
-
- if (assert) {
- FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
- debug("asserted\n");
- } else {
- FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
- debug("deasserted\n");
- }
-
- return assert;
-}
-
-
-/*
- * Test the state of the active-low FPGA INIT line. Return 1 on INIT
- * asserted (low).
- */
-int ngcc_fpga_init_fn(int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
- if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
- debug("high\n");
- return 0;
- } else {
- debug("low\n");
- return 1;
- }
-}
-
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-int ngcc_fpga_done_fn(int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
- if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
- debug("DONE high\n");
- return 1;
- } else {
- debug("low\n");
- return 0;
- }
-}
-
-
-/*
- * FPGA pre-configuration function.
- */
-int ngcc_fpga_pre_config_fn(int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
- debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
-
- ngcc_fpga_reset(true);
- FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
-
- ngcc_fpga_reset(true);
- return 0;
-}
-
-
-/*
- * FPGA post configuration function. Blip the FPGA reset line and then see if
- * the FPGA appears to be running.
- */
-int ngcc_fpga_post_config_fn(int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
-
- udelay (100);
- ngcc_fpga_reset(false);
-
- FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
-
- return 0;
-}
-
-
-int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- if (assert_clk)
- FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
- else
- FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
-
- return assert_clk;
-}
-
-
-int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
-{
- pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
- if (assert_write)
- FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
- else
- FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
-
- return assert_write;
-}
-
-
-/*
- * Initialize the fpga. Return 1 on success, 0 on failure.
- */
-int pmc440_init_fpga(void)
-{
- char *s;
-
- debug("%s:%d: Initialize FPGA interface\n",
- __FUNCTION__, __LINE__);
- fpga_init();
-
- fpga_serialslave_init ();
- debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
- fpga_add (fpga_xilinx, &fpga[0]);
-
- /* NGCC only */
- if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
- ngcc_fpga_serialslave_init ();
- debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
- fpga_add (fpga_xilinx, &fpga[1]);
- }
-
- return 0;
-}
-#endif /* CONFIG_FPGA */
diff --git a/board/esd/pmc440/fpga.h b/board/esd/pmc440/fpga.h
deleted file mode 100644
index 3810788a92..0000000000
--- a/board/esd/pmc440/fpga.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2007
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern int pmc440_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_init_fn(int cookie);
-extern int fpga_err_fn(int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
-extern int fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int fpga_wdata_fn (uchar data, int flush, int cookie);
-extern int fpga_read_data_fn(unsigned char *data, int cookie);
-extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
-extern int fpga_busy_fn(int cookie);
-extern int fpga_abort_fn(int cookie );
-extern int fpga_pre_config_fn(int cookie );
-extern int fpga_post_config_fn(int cookie );
-
-extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int ngcc_fpga_init_fn(int cookie);
-extern int ngcc_fpga_done_fn(int cookie);
-extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int ngcc_fpga_pre_config_fn(int cookie );
-extern int ngcc_fpga_post_config_fn(int cookie );
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
deleted file mode 100644
index 1f26fad147..0000000000
--- a/board/esd/pmc440/init.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- */
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-
- /* TLB entries for DDR2 SDRAM are generated dynamically */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
-#endif
-
- /* TLB-entry for PCI Memory */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
-
- /* TLB-entries for EBC */
- /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
- * tlb entry.
- * This dummy entry is only for convinience in order not to modify the
- * amount of entries. Currently OS/9 relies on this :-)
- */
- tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for NAND */
- tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for Internal Registers & OCM */
- tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
-
- /*TLB-entry PCI registers*/
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
- /* TLB-entry PCI IO space */
- tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
-
- /* TODO: what about high IO space */
- tlbtab_end
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
deleted file mode 100644
index 0d43505e35..0000000000
--- a/board/esd/pmc440/pmc440.c
+++ /dev/null
@@ -1,906 +0,0 @@
-/*
- * (Cg) Copyright 2007-2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- * Based on board/amcc/sequoia/sequoia.c
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <console.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/ppc440.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <i2c.h>
-#ifdef CONFIG_RESET_PHY_R
-#include <miiphy.h>
-#endif
-#include <serial.h>
-#include <asm/4xx_pci.h>
-#include <usb.h>
-
-#include "fpga.h"
-#include "pmc440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-extern void __ft_board_setup(void *blob, bd_t *bd);
-
-ulong flash_get_size(ulong base, int banknum);
-static int pci_is_66mhz(void);
-int is_monarch(void);
-static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt);
-
-struct serial_device *default_serial_console(void)
-{
- uchar buf[4];
- ulong delay;
- int i;
- ulong val;
-
- /*
- * Use default console on P4 when strapping jumper
- * is installed (bootstrap option != 'H').
- */
- mfsdr(SDR0_PINSTP, val);
- if (((val & 0xf0000000) >> 29) != 7)
- return &eserial2_device;
-
- ulong scratchreg = in_be32((void *)GPIO0_ISR3L);
- if (!(scratchreg & 0x80)) {
- /* mark scratchreg valid */
- scratchreg = (scratchreg & 0xffffff00) | 0x80;
-
- i2c_init_all();
-
- i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
- 0x10, buf, 4);
- if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
- scratchreg |= buf[2];
-
- /* bringup delay for console */
- for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++)
- udelay(1000);
- } else
- scratchreg |= 0x01;
- out_be32((void *)GPIO0_ISR3L, scratchreg);
- }
-
- if (scratchreg & 0x01)
- return &eserial2_device;
- else
- return &eserial1_device;
-}
-
-int board_early_init_f(void)
-{
- u32 sdr0_cust0;
- u32 sdr0_pfc1, sdr0_pfc2;
- u32 reg;
-
- /* general EBC configuration (disable EBC timeouts) */
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, 0xf8400000);
-
- /* Setup the GPIO pins */
- out_be32((void *)GPIO0_OR, 0x40000102);
- out_be32((void *)GPIO0_TCR, 0x4c90011f);
- out_be32((void *)GPIO0_OSRL, 0x28051400);
- out_be32((void *)GPIO0_OSRH, 0x55005000);
- out_be32((void *)GPIO0_TSRL, 0x08051400);
- out_be32((void *)GPIO0_TSRH, 0x55005000);
- out_be32((void *)GPIO0_ISR1L, 0x54000000);
- out_be32((void *)GPIO0_ISR1H, 0x00000000);
- out_be32((void *)GPIO0_ISR2L, 0x44000000);
- out_be32((void *)GPIO0_ISR2H, 0x00000100);
- out_be32((void *)GPIO0_ISR3L, 0x00000000);
- out_be32((void *)GPIO0_ISR3H, 0x00000000);
-
- out_be32((void *)GPIO1_OR, 0x80002408);
- out_be32((void *)GPIO1_TCR, 0xd6003c08);
- out_be32((void *)GPIO1_OSRL, 0x0a5a0000);
- out_be32((void *)GPIO1_OSRH, 0x00000000);
- out_be32((void *)GPIO1_TSRL, 0x00000000);
- out_be32((void *)GPIO1_TSRH, 0x00000000);
- out_be32((void *)GPIO1_ISR1L, 0x00005555);
- out_be32((void *)GPIO1_ISR1H, 0x40000000);
- out_be32((void *)GPIO1_ISR2L, 0x04010000);
- out_be32((void *)GPIO1_ISR2H, 0x00000000);
- out_be32((void *)GPIO1_ISR3L, 0x01400000);
- out_be32((void *)GPIO1_ISR3H, 0x00000000);
-
- /* patch PLB:PCI divider for 66MHz PCI */
- mfcpr(CPR0_SPCID, reg);
- if (pci_is_66mhz() && (reg != 0x02000000)) {
- mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
-
- mfcpr(CPR0_ICFG, reg);
- reg |= CPR0_ICFG_RLI_MASK;
- mtcpr(CPR0_ICFG, reg);
-
- mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
- }
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffff7ef);
- mtdcr(UIC0TR, 0x00000000);
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffc7f5);
- mtdcr(UIC1TR, 0x00000000);
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0x27ffffff);
- mtdcr(UIC2TR, 0x00000000);
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- /* select Ethernet pins */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_4;
- mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_4;
-
- /* enable 2nd IIC */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
-
- mtsdr(SDR0_PFC2, sdr0_pfc2);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* setup NAND FLASH */
- mfsdr(SDR0_CUST0, sdr0_cust0);
- sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
- mtsdr(SDR0_CUST0, sdr0_cust0);
-
- return 0;
-}
-
-#if defined(CONFIG_MISC_INIT_F)
-int misc_init_f(void)
-{
- struct pci_controller hose;
- hose.first_busno = 0;
- hose.last_busno = 0;
- hose.region_count = 0;
-
- if (getenv("pciearly") && (!is_monarch())) {
- printf("PCI: early target init\n");
- pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
- pci_target_init(&hose);
- }
- return 0;
-}
-#endif
-
-/*
- * misc_init_r.
- */
-int misc_init_r(void)
-{
- uint pbcr;
- int size_val = 0;
- u32 reg;
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1;
- unsigned long sdr0_srst0, sdr0_srst1;
- char *act = getenv("usbact");
-
- /*
- * FLASH stuff...
- */
-
- /* Re-do sizing to get full correct info */
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- size_val = ffs(gd->bd->bi_flashsize) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- /* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- /*
- * USB suff...
- */
- if ((act == NULL || strcmp(act, "host") == 0) &&
- !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-
- /*
- * An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
-
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /*
- * Take USB out of reset:
- * -Initial status = all cores are in reset
- * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
- * -wait 1 ms
- * -deassert reset to PHY
- * -wait 1 ms
- * -deassert reset to HOST
- * -wait 4 ms
- * -deassert all other resets
- */
- mfsdr(SDR0_SRST1, sdr0_srst1);
- sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
- SDR0_SRST1_P4OPB0 | \
- SDR0_SRST1_OPBA2 | \
- SDR0_SRST1_PLB42OPB1 | \
- SDR0_SRST1_OPB2PLB40);
- mtsdr(SDR0_SRST1, sdr0_srst1);
- udelay(1000);
-
- mfsdr(SDR0_SRST1, sdr0_srst1);
- sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
- mtsdr(SDR0_SRST1, sdr0_srst1);
- udelay(1000);
-
- mfsdr(SDR0_SRST0, sdr0_srst0);
- sdr0_srst0 &= ~SDR0_SRST0_USB2H;
- mtsdr(SDR0_SRST0, sdr0_srst0);
- udelay(4000);
-
- /* finally all the other resets */
- mtsdr(SDR0_SRST1, 0x00000000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
- /* enable power on USB socket */
- out_be32((void *)GPIO1_OR,
- in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
- }
-
- printf("USB: Host\n");
-
- } else if ((strcmp(act, "dev") == 0) ||
- (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x672c6000);
-
- udelay (1000);
- mtsdr(SDR0_SRST0, 0x00000080);
-
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x60206000);
-
- *(unsigned int *)(0xe0000350) = 0x00000001;
-
- udelay (1000);
- mtsdr(SDR0_SRST1, 0x60306000);
-
- /* SDR Setting */
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_PFC1, sdr0_pfc1);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
-
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
-
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
-
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /*clear resets*/
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Device\n");
- }
-
- /*
- * Clear PLB4A0_ACR[WRP]
- * This fix will make the MAL burst disabling patch for the Linux
- * EMAC driver obsolete.
- */
- reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
- mtdcr(PLB4A0_ACR, reg);
-
-#ifdef CONFIG_FPGA
- pmc440_init_fpga();
-#endif
-
- /* turn off POST LED */
- out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N);
- /* turn on RUN LED */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N);
- return 0;
-}
-
-int is_monarch(void)
-{
- if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH)
- return 0;
-
- return 1;
-}
-
-static int pci_is_66mhz(void)
-{
- if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN)
- return 1;
- return 0;
-}
-
-static int board_revision(void)
-{
- return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
-}
-
-int checkboard(void)
-{
- puts("Board: esd GmbH - PMC440");
-
- gd->board_type = board_revision();
- printf(", Rev 1.%ld, ", gd->board_type);
-
- if (!is_monarch()) {
- puts("non-");
- }
-
- printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
- return (0);
-}
-
-
-#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
-/*
- * Assign interrupts to PCI devices. Some OSs rely on this.
- */
-void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
-
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
- int_line[PCI_DEV(dev) & 0x03]);
-}
-#endif
-
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- char *ptmla_str, *ptmms_str;
-
- /*
- * Set up Direct MMIO registers
- */
- /*
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0x80000000-0xBFFFFFFF
- * ==> PCI address 0x80000000-0xBFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
- /* and enable region */
-
- if (!is_monarch()) {
- ptmla_str = getenv("ptm1la");
- ptmms_str = getenv("ptm1ms");
- if(NULL != ptmla_str && NULL != ptmms_str ) {
- out32r(PCIL0_PTM1MS,
- simple_strtoul(ptmms_str, NULL, 16));
- out32r(PCIL0_PTM1LA,
- simple_strtoul(ptmla_str, NULL, 16));
- } else {
- /* BAR1: default top 64MB of RAM */
- out32r(PCIL0_PTM1MS, 0xfc000001);
- out32r(PCIL0_PTM1LA, 0x0c000000);
- }
- } else {
- /* BAR1: default: complete 256MB RAM */
- out32r(PCIL0_PTM1MS, 0xf0000001);
- out32r(PCIL0_PTM1LA, 0x00000000);
- }
-
- ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
- ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
- if(NULL != ptmla_str && NULL != ptmms_str ) {
- out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
- out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
- } else {
- /* BAR2: default: 4MB FPGA */
- out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
- }
-
- if (is_monarch()) {
- /* BAR2: map FPGA registers behind system memory at 1GB */
- pci_hose_write_config_dword(hose, 0,
- PCI_BASE_ADDRESS_2, 0x40000008);
- }
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's vendor id */
- pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
-
- /* disabled for PMC405 backward compatibility */
- /* Configure command register as bus master */
- /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
-
-
- /* 240nS PCI clock */
- pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
-
- if (!is_monarch()) {
- /* Program the board's subsystem id/classcode */
- pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
- CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
- pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
- CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
-
- /* PCI configuration done: release ERREADY */
- out_be32((void *)GPIO1_OR,
- in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY);
- out_be32((void *)GPIO1_TCR,
- in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY);
- } else {
- /* Program the board's subsystem id/classcode */
- pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
- CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
- pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
- CONFIG_SYS_PCI_CLASSCODE_MONARCH);
- }
-
- /* enable host configuration */
- pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*
- * Override weak default pci_master_init()
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
- /*
- * Only configure the master in monach mode
- */
- if (is_monarch())
- __pci_master_init(hose);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-static void wait_for_pci_ready(void)
-{
- if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) {
- printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
- while (1) {
- if (ctrlc()) {
- puts("abort\n");
- break;
- }
- if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) {
- printf("done\n");
- break;
- }
- }
- }
-}
-
-/*
- * Override weak is_pci_host()
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- char *s = getenv("pciscan");
- if (s == NULL)
- if (is_monarch()) {
- wait_for_pci_ready();
- return 1;
- } else
- return 0;
- else if (!strcmp(s, "yes"))
- return 1;
-
- return 0;
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_RESET_PHY_R
-static int pmc440_setup_vsc8601(char *devname, int phy_addr,
- unsigned short behavior, unsigned short method)
-{
- /* adjust LED behavior */
- if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) {
- printf("Phy%d: register write access failed\n", phy_addr);
- return -1;
- }
-
- miiphy_write(devname, phy_addr, 0x11, 0x0010);
- miiphy_write(devname, phy_addr, 0x11, behavior);
- miiphy_write(devname, phy_addr, 0x10, method);
- miiphy_write(devname, phy_addr, 0x1f, 0x0000);
-
- return 0;
-}
-
-static int pmc440_setup_ksz9031(char *devname, int phy_addr)
-{
- unsigned short id1, id2;
-
- if (miiphy_read(devname, phy_addr, 2, &id1) ||
- miiphy_read(devname, phy_addr, 3, &id2)) {
- printf("Phy%d: cannot read id\n", phy_addr);
- return -1;
- }
-
- if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) {
- printf("Phy%d: unexpected id\n", phy_addr);
- return -1;
- }
-
- /* MMD 2.08: adjust tx_clk pad skew */
- miiphy_write(devname, phy_addr, 0x0d, 2);
- miiphy_write(devname, phy_addr, 0x0e, 8);
- miiphy_write(devname, phy_addr, 0x0d, 0x4002);
- miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5));
-
- return 0;
-}
-
-void reset_phy(void)
-{
- char *s;
- unsigned short val_method, val_behavior;
-
- if (gd->board_type < 4) {
- /* special LED setup for NGCC/CANDES */
- s = getenv("bd_type");
- if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
- val_method = 0x0e0a;
- val_behavior = 0x0cf2;
- } else {
- /* PMC440 standard type */
- val_method = 0x0e10;
- val_behavior = 0x0cf0;
- }
-
- /* boards up to rev. 1.3 use Vitesse VSC8601 phys */
- pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR,
- val_method, val_behavior);
- pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR,
- val_method, val_behavior);
- } else {
- /* rev. 1.4 uses a Micrel KSZ9031 */
- pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR);
- pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR);
- }
-}
-#endif
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/*
- * Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
- */
-int eeprom_write_enable(unsigned dev_addr, int state)
-{
- if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
- (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
- return -1;
- } else {
- switch (state) {
- case 1:
- /* Enable write access, clear bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
- state = 0;
- break;
- case 0:
- /* Disable write access, set bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
- state = 0;
- break;
- default:
- /* Read current status back. */
- state = (0 == (in_be32((void *)GPIO0_OR)
- & GPIO0_EP_EEP));
- break;
- }
- }
- return state;
-}
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
-int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt)
-{
- unsigned end = offset + cnt;
- unsigned blk_off;
- int rcode = 0;
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
- eeprom_write_enable(dev_addr, 1);
-#endif
- /*
- * Write data until done or would cross a write page boundary.
- * We must write the address again when changing pages
- * because the address counter only increments within a page.
- */
- while (offset < end) {
- unsigned alen, len;
- unsigned maxlen;
- uchar addr[2];
-
- blk_off = offset & 0xFF; /* block offset */
-
- addr[0] = offset >> 8; /* block number */
- addr[1] = blk_off; /* block offset */
- alen = 2;
- addr[0] |= dev_addr; /* insert device address */
-
- len = end - offset;
-
-#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
-#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
-
- maxlen = BOOT_EEPROM_PAGE_SIZE -
- BOOT_EEPROM_PAGE_OFFSET(blk_off);
- if (maxlen > I2C_RXTX_LEN)
- maxlen = I2C_RXTX_LEN;
-
- if (len > maxlen)
- len = maxlen;
-
- if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
- rcode = 1;
-
- buffer += len;
- offset += len;
-
-#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
- udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-#endif
- }
-#if defined(CONFIG_SYS_EEPROM_WREN)
- eeprom_write_enable(dev_addr, 0);
-#endif
- return rcode;
-}
-
-static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt)
-{
- unsigned end = offset + cnt;
- unsigned blk_off;
- int rcode = 0;
-
- /*
- * Read data until done or would cross a page boundary.
- * We must write the address again when changing pages
- * because the next page may be in a different device.
- */
- while (offset < end) {
- unsigned alen, len;
- unsigned maxlen;
- uchar addr[2];
-
- blk_off = offset & 0xFF; /* block offset */
-
- addr[0] = offset >> 8; /* block number */
- addr[1] = blk_off; /* block offset */
- alen = 2;
-
- addr[0] |= dev_addr; /* insert device address */
-
- len = end - offset;
-
- maxlen = 0x100 - blk_off;
- if (maxlen > I2C_RXTX_LEN)
- maxlen = I2C_RXTX_LEN;
- if (len > maxlen)
- len = maxlen;
-
- if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
- rcode = 1;
- buffer += len;
- offset += len;
- }
-
- return rcode;
-}
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int board_usb_init(int index, enum usb_init_type init)
-{
- char *act = getenv("usbact");
- int i;
-
- if ((act == NULL || strcmp(act, "host") == 0) &&
- !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT))
- /* enable power on USB socket */
- out_be32((void *)GPIO1_OR,
- in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
-
- for (i=0; i<1000; i++)
- udelay(1000);
-
- return 0;
-}
-
-int usb_board_stop(void)
-{
- /* disable power on USB socket */
- out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N);
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return usb_board_stop();
-}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- int rc;
-
- __ft_board_setup(blob, bd);
-
- /*
- * Disable PCI in non-monarch mode.
- */
- if (!is_monarch()) {
- rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
- "disabled", sizeof("disabled"), 1);
- if (rc) {
- printf("Unable to update property status in PCI node, ");
- printf("err=%s\n", fdt_strerror(rc));
- }
- }
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h
deleted file mode 100644
index 84e0b1f46c..0000000000
--- a/board/esd/pmc440/pmc440.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PMC440_H__
-#define __PMC440_H__
-
-/*
- * GPIOs
- */
-#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */
-#define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */
-#define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */
-#define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */
-#define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */
-#define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */
-#define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */
-
-#define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */
-#define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */
-#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */
-#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */
-#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */
-
-/*
- * FPGA programming pin configuration
- */
-#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
-#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */
-#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */
-#define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */
-#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */
-#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */
-
-/*
- * FPGA interface
- */
-#define FPGA_BA CONFIG_SYS_FPGA_BASE0
-#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
-#define FPGA_IN32(p) in_be32((void*)(p))
-#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
-#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
-
-struct pmc440_fifo_s {
- u32 data;
- u32 ctrl;
-};
-
-/* fifo ctrl register */
-#define FIFO_IE (1 << 15)
-#define FIFO_OVERFLOW (1 << 10)
-#define FIFO_EMPTY (1 << 9)
-#define FIFO_FULL (1 << 8)
-#define FIFO_LEVEL_MASK 0x000000ff
-
-#define FIFO_COUNT 4
-
-struct pmc440_fpga_s {
- u32 ctrla;
- u32 status;
- u32 ctrlb;
- u32 pad1[0x40 / sizeof(u32) - 3];
- u32 irig_time; /* offset: 0x0040 */
- u32 irig_tod;
- u32 irig_cf;
- u32 pad2;
- u32 irig_rx_time; /* offset: 0x0050 */
- u32 pad3[3];
- u32 hostctrl; /* offset: 0x0060 */
- u32 pad4[0x20 / sizeof(u32) - 1];
- struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
-};
-
-typedef struct pmc440_fpga_s pmc440_fpga_t;
-
-/* ctrl register */
-#define CTRL_HOST_IE (1 << 8)
-
-/* outputs */
-#define RESET_EN (1 << 31)
-#define CLOCK_EN (1 << 30)
-#define RESET_OUT (1 << 19)
-#define CLOCK_OUT (1 << 22)
-#define RESET_OUT (1 << 19)
-#define IRIGB_R_OUT (1 << 14)
-
-/* status register */
-#define STATUS_VERSION_SHIFT 24
-#define STATUS_VERSION_MASK 0xff000000
-#define STATUS_HWREV_SHIFT 20
-#define STATUS_HWREV_MASK 0x00f00000
-
-#define STATUS_CAN_ISF (1 << 11)
-#define STATUS_CSTM_ISF (1 << 10)
-#define STATUS_FIFO_ISF (1 << 9)
-#define STATUS_HOST_ISF (1 << 8)
-
-/* inputs */
-#define RESET_IN (1 << 0)
-#define CLOCK_IN (1 << 1)
-#define IRIGB_R_IN (1 << 5)
-
-/* hostctrl register */
-#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17)
-#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16)
-#define HOSTCTRL_CSTM1IE_GATE (1 << 7)
-#define HOSTCTRL_CSTM1IW_FLAG (1 << 6)
-#define HOSTCTRL_CSTM0IE_GATE (1 << 5)
-#define HOSTCTRL_CSTM0IW_FLAG (1 << 4)
-#define HOSTCTRL_FIFOIE_GATE (1 << 3)
-#define HOSTCTRL_FIFOIE_FLAG (1 << 2)
-#define HOSTCTRL_HCINT_GATE (1 << 1)
-#define HOSTCTRL_HCINT_FLAG (1 << 0)
-
-#define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000)
-#define NGCC_CTRL_FPGARST_N (1 << 2)
-
-/*
- * FPGA to PPC interrupt
- */
-#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */
-#define IRQ1_FPGA (32+30) /* UIC1 - custom module */
-#define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */
-#define IRQ_ETH0 (64+ 4) /* UIC2 */
-#define IRQ_ETH1 ( 27) /* UIC0 */
-#define IRQ_RTC (64+ 0) /* UIC2 */
-#define IRQ_PCIA (64+ 1) /* UIC2 */
-#define IRQ_PCIB (32+18) /* UIC1 */
-#define IRQ_PCIC (32+19) /* UIC1 */
-#define IRQ_PCID (32+20) /* UIC1 */
-
-#endif /* __PMC440_H__ */
diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c
deleted file mode 100644
index c379e7723d..0000000000
--- a/board/esd/pmc440/sdram.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2009
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
- *
- * (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debug output */
-#undef DEBUG
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/ppc440.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-
-struct sdram_conf_s {
- ulong size;
- int rows;
- int banks;
-};
-
-struct sdram_conf_s sdram_conf[] = {
- {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
- {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
- {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
-};
-
-/*
- * dram_init -- 440EPx's DDR controller is a DENALI Core
- */
-int initdram_by_rb(int rows, int banks)
-{
- ulong speed = get_bus_freq(0);
-
- mtsdram(DDR0_02, 0x00000000);
-
- mtsdram(DDR0_00, 0x0000190A);
- mtsdram(DDR0_01, 0x01000000);
- mtsdram(DDR0_03, 0x02030602);
- mtsdram(DDR0_04, 0x0A020200);
- mtsdram(DDR0_05, 0x02020308);
- mtsdram(DDR0_06, 0x0102C812);
- mtsdram(DDR0_07, 0x000D0100);
- mtsdram(DDR0_08, 0x02430001);
- mtsdram(DDR0_09, 0x00011D5F);
- mtsdram(DDR0_10, 0x00000100);
- mtsdram(DDR0_11, 0x0027C800);
- mtsdram(DDR0_12, 0x00000003);
- mtsdram(DDR0_14, 0x00000000);
- mtsdram(DDR0_17, 0x19000000);
- mtsdram(DDR0_18, 0x19191919);
- mtsdram(DDR0_19, 0x19191919);
- mtsdram(DDR0_20, 0x0B0B0B0B);
- mtsdram(DDR0_21, 0x0B0B0B0B);
- mtsdram(DDR0_22, 0x00267F0B);
- mtsdram(DDR0_23, 0x00000000);
- mtsdram(DDR0_24, 0x01010002);
- if (speed > 133333334)
- mtsdram(DDR0_26, 0x5B26050C);
- else
- mtsdram(DDR0_26, 0x5B260408);
- mtsdram(DDR0_27, 0x0000682B);
- mtsdram(DDR0_28, 0x00000000);
- mtsdram(DDR0_31, 0x00000000);
-
- mtsdram(DDR0_42,
- DDR0_42_ADDR_PINS_DECODE(14 - rows) |
- 0x00000006);
- mtsdram(DDR0_43,
- DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
- 0x030A0200);
-
- mtsdram(DDR0_44, 0x00000003);
- mtsdram(DDR0_02, 0x00000001);
-
- denali_wait_for_dlllock();
-
-#ifdef CONFIG_DDR_DATA_EYE
- /*
- * Perform data eye search if requested.
- */
- denali_core_search_data_eye();
-#endif
- /*
- * Clear possible errors resulting from data-eye-search.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- return 0;
-}
-
-int dram_init(void)
-{
- phys_size_t size;
- int n;
-
- /* go through supported memory configurations */
- for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
- size = sdram_conf[n].size;
-
- /* program TLB entries */
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
- TLB_WORD2_I_ENABLE);
-
- /*
- * setup denali core
- */
- initdram_by_rb(sdram_conf[n].rows,
- sdram_conf[n].banks);
-
- /* check for suitable configuration */
- if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) {
- gd->ram_size = size;
- return 0;
- }
-
- /* delete TLB entries */
- remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
- }
-
- return -ENXIO;
-}
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