diff options
Diffstat (limited to 'board/amcc/sequoia')
| -rw-r--r-- | board/amcc/sequoia/Kconfig | 12 | ||||
| -rw-r--r-- | board/amcc/sequoia/MAINTAINERS | 9 | ||||
| -rw-r--r-- | board/amcc/sequoia/Makefile | 10 | ||||
| -rw-r--r-- | board/amcc/sequoia/chip_config.c | 105 | ||||
| -rw-r--r-- | board/amcc/sequoia/config.mk | 19 | ||||
| -rw-r--r-- | board/amcc/sequoia/init.S | 79 | ||||
| -rw-r--r-- | board/amcc/sequoia/sdram.c | 96 | ||||
| -rw-r--r-- | board/amcc/sequoia/sequoia.c | 413 | ||||
| -rw-r--r-- | board/amcc/sequoia/u-boot-ram.lds | 79 |
9 files changed, 0 insertions, 822 deletions
diff --git a/board/amcc/sequoia/Kconfig b/board/amcc/sequoia/Kconfig deleted file mode 100644 index 67ee3ca2eb..0000000000 --- a/board/amcc/sequoia/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SEQUOIA - -config SYS_BOARD - default "sequoia" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "sequoia" - -endif diff --git a/board/amcc/sequoia/MAINTAINERS b/board/amcc/sequoia/MAINTAINERS deleted file mode 100644 index 6c28a3717c..0000000000 --- a/board/amcc/sequoia/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -SEQUOIA BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/sequoia/ -F: include/configs/sequoia.h -F: configs/rainier_defconfig -F: configs/rainier_ramboot_defconfig -F: configs/sequoia_defconfig -F: configs/sequoia_ramboot_defconfig diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile deleted file mode 100644 index b4ab5daa85..0000000000 --- a/board/amcc/sequoia/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = sequoia.o sdram.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/board/amcc/sequoia/chip_config.c b/board/amcc/sequoia/chip_config.c deleted file mode 100644 index eef93165b0..0000000000 --- a/board/amcc/sequoia/chip_config.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "333-133-nor", "NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66", - { - 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "333-166-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "333-166-nand", "NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { - 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "400-160-nor", "NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53", - { - 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "416-166-nor", "NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55", - { - 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "416-166-nand", "NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55", - { - 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "500-166-nor", "NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "500-166-nand", "NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "533-133-nor", "NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66", - { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "667-133-nor", "NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66", - { - 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "667-166-nor", "NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55", - { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "667-166-nand", "NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55", - { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk deleted file mode 100644 index 824e78f75d..0000000000 --- a/board/amcc/sequoia/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2002-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 440EPx Reference Platform (Sequoia) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S deleted file mode 100644 index f876639d35..0000000000 --- a/board/amcc/sequoia/init.S +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> - -/* - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - */ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* vxWorks needs this as first entry for the Machine Check interrupt */ - tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG ) - - /* - * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This - * entry is already configured for SDRAM via the JTAG debugger and mustn't - * be re-initialized by this RAM-booting U-Boot version. - */ -#ifndef CONFIG_SYS_RAMBOOT - /* TLB-entry for DDR SDRAM (Up to 2GB) */ -#ifdef CONFIG_4xx_DCACHE - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G) -#else - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG ) -#endif -#endif /* CONFIG_SYS_RAMBOOT */ - - /* TLB-entry for EBC */ - tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG ) - - /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) -#endif - - /* TLB-entry for PCI Memory */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) - - /* TLB-entry for NAND */ - tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG ) - - /* TLB-entry for Internal Registers & OCM */ - tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) - - /*TLB-entry PCI registers*/ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) - - /* TLB-entry for peripherals */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) - - /* TLB-entry PCI IO Space - from sr@denx.de */ - tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) - - tlbtab_end diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c deleted file mode 100644 index ea987179e7..0000000000 --- a/board/amcc/sequoia/sdram.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debug output */ -#undef DEBUG - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc440.h> - -DECLARE_GLOBAL_DATA_PTR; - -/*-----------------------------------------------------------------------------+ - * Prototypes - *-----------------------------------------------------------------------------*/ -extern int denali_wait_for_dlllock(void); -extern void denali_core_search_data_eye(void); - -/************************************************************************* - * - * dram_init -- 440EPx's DDR controller is a DENALI Core - * - ************************************************************************/ -int dram_init(void) -{ -#if !defined(CONFIG_SYS_RAMBOOT) - ulong speed = get_bus_freq(0); - - mtsdram(DDR0_02, 0x00000000); - - mtsdram(DDR0_00, 0x0000190A); - mtsdram(DDR0_01, 0x01000000); - mtsdram(DDR0_03, 0x02030602); - mtsdram(DDR0_04, 0x0A020200); - mtsdram(DDR0_05, 0x02020308); - mtsdram(DDR0_06, 0x0102C812); - mtsdram(DDR0_07, 0x000D0100); - mtsdram(DDR0_08, 0x02430001); - mtsdram(DDR0_09, 0x00011D5F); - mtsdram(DDR0_10, 0x00000100); - mtsdram(DDR0_11, 0x0027C800); - mtsdram(DDR0_12, 0x00000003); - mtsdram(DDR0_14, 0x00000000); - mtsdram(DDR0_17, 0x19000000); - mtsdram(DDR0_18, 0x19191919); - mtsdram(DDR0_19, 0x19191919); - mtsdram(DDR0_20, 0x0B0B0B0B); - mtsdram(DDR0_21, 0x0B0B0B0B); - mtsdram(DDR0_22, 0x00267F0B); - mtsdram(DDR0_23, 0x00000000); - mtsdram(DDR0_24, 0x01010002); - if (speed > 133333334) - mtsdram(DDR0_26, 0x5B26050C); - else - mtsdram(DDR0_26, 0x5B260408); - mtsdram(DDR0_27, 0x0000682B); - mtsdram(DDR0_28, 0x00000000); - mtsdram(DDR0_31, 0x00000000); - mtsdram(DDR0_42, 0x01000006); - mtsdram(DDR0_43, 0x030A0200); - mtsdram(DDR0_44, 0x00000003); - mtsdram(DDR0_02, 0x00000001); - - denali_wait_for_dlllock(); -#endif /* #ifndef CONFIG_SYS_RAMBOOT */ - -#ifdef CONFIG_DDR_DATA_EYE - /* -----------------------------------------------------------+ - * Perform data eye search if requested. - * ----------------------------------------------------------*/ - denali_core_search_data_eye(); -#endif - - /* - * Clear possible errors resulting from data-eye-search. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20; - - return 0; -} diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c deleted file mode 100644 index 1e45774ce4..0000000000 --- a/board/amcc/sequoia/sequoia.c +++ /dev/null @@ -1,413 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <errno.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/ppc4xx.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/bitops.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_MTD_NOR_FLASH) -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#endif - -extern void __ft_board_setup(void *blob, bd_t *bd); -ulong flash_get_size(ulong base, int banknum); - -static inline u32 get_async_pci_freq(void) -{ - if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & - CONFIG_SYS_BCSR5_PCI66EN) - return 66666666; - else - return 33333333; -} - -int board_early_init_f(void) -{ - u32 sdr0_cust0; - u32 sdr0_pfc1, sdr0_pfc2; - u32 reg; - - mtdcr(EBC0_CFGADDR, EBC0_CFG); - mtdcr(EBC0_CFGDATA, 0xb8400000); - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - /* Check and reconfigure the PCI sync clock if necessary */ - ppc4xx_pci_sync_clock_config(get_async_pci_freq()); - - /* 50MHz tmrclk */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); - - /* clear write protects */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00); - - /* enable Ethernet */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00); - - /* enable USB device */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20); - - /* select Ethernet (and optionally IIC1) pins */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | - SDR0_PFC1_SELECT_CONFIG_4; -#ifdef CONFIG_I2C_MULTI_BUS - sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); -#endif - /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS; - - mfsdr(SDR0_PFC2, sdr0_pfc2); - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | - SDR0_PFC2_SELECT_CONFIG_4; - mtsdr(SDR0_PFC2, sdr0_pfc2); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* PCI arbiter enabled */ - mfsdr(SDR0_PCI0, reg); - mtsdr(SDR0_PCI0, 0x80000000 | reg); - - /* setup NAND FLASH */ - mfsdr(SDR0_CUST0, sdr0_cust0); - sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); - mtsdr(SDR0_CUST0, sdr0_cust0); - - return 0; -} - -int misc_init_r(void) -{ -#if defined(CONFIG_MTD_NOR_FLASH) - uint pbcr; - int size_val = 0; -#endif -#ifdef CONFIG_440EPX - unsigned long usb2d0cr = 0; - unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; - char *act = getenv("usbact"); -#endif - u32 reg; - -#if defined(CONFIG_MTD_NOR_FLASH) - /* Re-do flash sizing to get full correct info */ - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - -#if defined(CONFIG_SYS_RAMBOOT) - mtdcr(EBC0_CFGADDR, PB3CR); -#else - mtdcr(EBC0_CFGADDR, PB0CR); -#endif - pbcr = mfdcr(EBC0_CFGDATA); - size_val = ffs(gd->bd->bi_flashsize) - 21; - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); -#if defined(CONFIG_SYS_RAMBOOT) - mtdcr(EBC0_CFGADDR, PB3CR); -#else - mtdcr(EBC0_CFGADDR, PB0CR); -#endif - mtdcr(EBC0_CFGDATA, pbcr); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, 0); - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif -#endif /* CONFIG_MTD_NOR_FLASH */ - - /* - * USB suff... - */ -#ifdef CONFIG_440EPX - if (act == NULL || strcmp(act, "hostdev") == 0) { - /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - - /* - * An 8-bit/60MHz interface is the only possible alternative - * when connecting the Device to the PHY - */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; - - /* - * To enable the USB 2.0 Device function - * through the UTMI interface - */ - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; - - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); - - /*clear resets*/ - udelay (1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Host(int phy) Device(ext phy)\n"); - - } else if (strcmp(act, "dev") == 0) { - /*-------------------PATCH-------------------------------*/ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - udelay (1000); - mtsdr(SDR0_SRST1, 0x672c6000); - - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000080); - - udelay (1000); - mtsdr(SDR0_SRST1, 0x60206000); - - *(unsigned int *)(0xe0000350) = 0x00000001; - - udelay (1000); - mtsdr(SDR0_SRST1, 0x60306000); - /*-------------------PATCH-------------------------------*/ - - /* SDR Setting */ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_PFC1, sdr0_pfc1); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; - - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; - - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; - - mtsdr(SDR0_USB2H0CR, usb2h0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* clear resets */ - udelay (1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Device(int phy)\n"); - } -#endif /* CONFIG_440EPX */ - - mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ - reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); - mtsdr(SDR0_SRST1, reg); - - /* - * Clear PLB4A0_ACR[WRP] - * This fix will make the MAL burst disabling patch for the Linux - * EMAC driver obsolete. - */ - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; - mtdcr(PLB4A0_ACR, reg); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u8 rev; - u32 clock = get_async_pci_freq(); - -#ifdef CONFIG_440EPX - printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); -#else - printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); -#endif - - rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); - printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - /* - * Reconfiguration of the PCI sync clock is already done, - * now check again if everything is in range: - */ - if (ppc4xx_pci_sync_clock_config(clock)) { - printf("ERROR: PCI clocking incorrect (async=%d " - "sync=%ld)!\n", clock, get_PCI_freq()); - } - - return (0); -} - -#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) -/* - * Assign interrupts to PCI devices. - */ -void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); -} -#endif - -#if defined(CONFIG_SYS_RAMBOOT) -/* - * On NAND-booting sequoia, we need to patch the chips select numbers - * in the dtb (CS0 - NAND, CS3 - NOR) - */ -int ft_board_setup(void *blob, bd_t *bd) -{ - int rc; - int len; - int nodeoffset; - struct fdt_property *prop; - u32 *reg; - char path[32]; - - /* First do common fdt setup */ - __ft_board_setup(blob, bd); - - /* And now configure NOR chip select to 3 instead of 0 */ - strcpy(path, "/plb/opb/ebc/nor_flash@0,0"); - nodeoffset = fdt_path_offset(blob, path); - prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); - if (prop == NULL) { - printf("Unable to update NOR chip select for NAND booting\n"); - return -FDT_ERR_NOTFOUND; - } - reg = (u32 *)&prop->data[0]; - reg[0] = 3; - rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); - if (rc) { - printf("Unable to update property NOR mappings\n"); - return rc; - } - - /* And now configure NAND chip select to 0 instead of 3 */ - strcpy(path, "/plb/opb/ebc/ndfc@3,0"); - nodeoffset = fdt_path_offset(blob, path); - prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); - if (prop == NULL) { - printf("Unable to update NDFC chip select for NAND booting\n"); - return len; - } - reg = (u32 *)&prop->data[0]; - reg[0] = 0; - rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); - if (rc) { - printf("Unable to update property NDFC mapping\n"); - return rc; - } - - return 0; -} -#endif /* CONFIG_SYS_RAMBOOT */ diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds deleted file mode 100644 index ef08be8d53..0000000000 --- a/board/amcc/sequoia/u-boot-ram.lds +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/ppc4xx/start.o (.text*) - board/amcc/sequoia/init.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} |