diff options
Diffstat (limited to 'arch')
94 files changed, 5113 insertions, 476 deletions
diff --git a/arch/arm/cpu/arm920t/at91rm9200/ether.c b/arch/arm/cpu/arm920t/at91rm9200/ether.c index 91eab95eed..e1cdebab9d 100644 --- a/arch/arm/cpu/arm920t/at91rm9200/ether.c +++ b/arch/arm/cpu/arm920t/at91rm9200/ether.c @@ -283,7 +283,7 @@ void eth_halt (void) }; #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -int at91rm9200_miiphy_read(char *devname, unsigned char addr, +int at91rm9200_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short * value) { at91rm9200_EmacEnableMDIO (p_mac); @@ -292,7 +292,7 @@ int at91rm9200_miiphy_read(char *devname, unsigned char addr, return 0; } -int at91rm9200_miiphy_write(char *devname, unsigned char addr, +int at91rm9200_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) { at91rm9200_EmacEnableMDIO (p_mac); diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index c63e8641f2..82c978bd93 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -81,7 +81,7 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval) unsigned int j = 0; u32 val = sizeval >> 1; - for (i = 0; val > 0x10000; i++) { + for (i = 0; val >= 0x10000; i++) { j |= (1 << i); val = val >> 1; } diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile new file mode 100644 index 0000000000..ce3e5a5a5a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = clock.o reset.o timer.o +SOBJS = + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c new file mode 100644 index 0000000000..70c8c8b04a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* + * Get the peripheral bus frequency depending on pll pin settings + */ +ulong get_bus_freq(ulong dummy) +{ + struct mb86r0x_crg * crg = (struct mb86r0x_crg *) + MB86R0x_CRG_BASE; + uint32_t pllmode; + + pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE; + + if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20) + return 40000000; + + return 41164767; +} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c new file mode 100644 index 0000000000..e7f0f6788b --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* + * Reset the cpu by setting software reset request bit + */ +void reset_cpu(ulong ignored) +{ + struct mb86r0x_crg * crg = (struct mb86r0x_crg *) + MB86R0x_CRG_BASE; + + writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr); + while (1) + /* NOP */; + /* Never reached */ +} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c new file mode 100644 index 0000000000..9175b71d16 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2010 + * Matthias Weisser, Graf-Syteco <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <div64.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256) + +static unsigned long long timestamp; +static ulong lastdec; + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, TIMER_FREQ); + + return tick; +} + +static inline unsigned long long usec_to_tick(unsigned long long usec) +{ + usec *= TIMER_FREQ; + do_div(usec, 1000000); + + return usec; +} + +/* nothing really to do with interrupts, just starts up a counter. */ +int timer_init(void) +{ + struct mb86r0x_timer * timer = (struct mb86r0x_timer *) + MB86R0x_TIMER_BASE; + ulong ctrl = readl(&timer->control); + + writel(TIMER_LOAD_VAL, &timer->load); + + ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S | + MB86R0x_TIMER_SIZE_32; + + writel(ctrl, &timer->control); + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ +unsigned long long get_ticks(void) +{ + struct mb86r0x_timer * timer = (struct mb86r0x_timer *) + MB86R0x_TIMER_BASE; + ulong now = readl(&timer->value); + + if (now <= lastdec) { + /* normal mode (non roll) */ + /* move stamp forward with absolut diff ticks */ + timestamp += lastdec - now; + } else { + /* we have rollover of incrementer */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + return timestamp; +} + +void reset_timer_masked(void) +{ + struct mb86r0x_timer * timer = (struct mb86r0x_timer *) + MB86R0x_TIMER_BASE; + + /* capture current value time */ + lastdec = readl(&timer->value); + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +void __udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = usec_to_tick(usec); + tmp = get_ticks(); /* get current timestamp */ + + while ((get_ticks() - tmp) < tmo) /* loop till event */ + /*NOP*/; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = TIMER_FREQ; + return tbclk; +} diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index f3c1e2192e..260f88b46e 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -61,7 +61,7 @@ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) unsigned int j = 0; u32 val = sizeval >> 1; - for (i = 0; val > 0x10000; i++) { + for (i = 0; val >= 0x10000; i++) { j |= (1 << i); val = val >> 1; } @@ -87,56 +87,56 @@ int orion5x_config_adr_windows(void) (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE; /* Window 0: PCIE MEM address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM, ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM, ORION5X_WIN_ENABLE), &winregs[0].ctrl); - writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base); - writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); - writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); + writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base); + writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); + writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); /* Window 1: PCIE IO address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO, ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO, ORION5X_WIN_ENABLE), &winregs[1].ctrl); - writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base); - writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); - writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); + writel(ORION5X_ADR_PCIE_IO, &winregs[1].base); + writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); + writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); /* Window 2: PCI MEM address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM, ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM, ORION5X_WIN_ENABLE), &winregs[2].ctrl); - writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base); + writel(ORION5X_ADR_PCI_MEM, &winregs[2].base); /* Window 3: PCI IO address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO, ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO, ORION5X_WIN_ENABLE), &winregs[3].ctrl); - writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base); + writel(ORION5X_ADR_PCI_IO, &winregs[3].base); /* Window 4: DEV_CS0 address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0, ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0, ORION5X_WIN_ENABLE), &winregs[4].ctrl); - writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base); + writel(ORION5X_ADR_DEV_CS0, &winregs[4].base); /* Window 5: DEV_CS1 address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1, ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1, ORION5X_WIN_ENABLE), &winregs[5].ctrl); - writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base); + writel(ORION5X_ADR_DEV_CS1, &winregs[5].base); /* Window 6: DEV_CS2 address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2, ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2, ORION5X_WIN_ENABLE), &winregs[6].ctrl); - writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base); + writel(ORION5X_ADR_DEV_CS2, &winregs[6].base); /* Window 7: BOOT Memory address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM, ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, ORION5X_WIN_ENABLE), &winregs[7].ctrl); - writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base); + writel(ORION5X_ADR_BOOTROM, &winregs[7].base); return 0; } diff --git a/arch/arm/cpu/armv7/mx51/timer.c b/arch/arm/cpu/armv7/mx51/timer.c index 81c4a06143..110edbfa85 100644 --- a/arch/arm/cpu/armv7/mx51/timer.c +++ b/arch/arm/cpu/armv7/mx51/timer.c @@ -89,7 +89,7 @@ ulong get_timer_masked(void) timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ)) - lastinc) + val; lastinc = val; - return val; + return timestamp; } ulong get_timer(ulong base) diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 69e285ff1d..6b8cf7ba2d 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -41,12 +41,8 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; /* * Nothing really to do with interrupts, just starts up a counter. - * We run the counter with 13MHz, divided by 8, resulting in timer - * frequency of 1.625MHz. With 32bit counter register, counter - * overflows in ~44min */ -/* 13MHz / 8 = 1.625MHz */ #define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) #define TIMER_LOAD_VAL 0xffffffff @@ -84,11 +80,6 @@ void set_timer(ulong t) /* delay x useconds */ void __udelay(unsigned long usec) { -#if defined(CONFIG_OMAP44XX) - /* TODO temporary hack until OMAP4 clock setup routines are present */ - if (usec > 1000) - usec = usec/1000; -#endif long tmo = usec * (TIMER_CLOCK / 1000) / 1000; unsigned long now, last = readl(&timer_base->tcrr); diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 5bf717303d..2e80d1fbf7 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -88,3 +88,14 @@ int checkboard(void) return 0; } +/* +* This function is called by start_armboot. You can reliably use static +* data. Any boot-time function that require static data should be +* called from here +*/ +int arch_cpu_init(void) +{ + set_muxconf_regs(); + return 0; +} + diff --git a/arch/arm/cpu/ixp/npe/include/npe.h b/arch/arm/cpu/ixp/npe/include/npe.h index 3d6f727476..b5eef8633f 100644 --- a/arch/arm/cpu/ixp/npe/include/npe.h +++ b/arch/arm/cpu/ixp/npe/include/npe.h @@ -82,9 +82,9 @@ struct npe { /* * prototypes... */ -extern int npe_miiphy_read (char *devname, unsigned char addr, +extern int npe_miiphy_read (const char *devname, unsigned char addr, unsigned char reg, unsigned short *value); -extern int npe_miiphy_write (char *devname, unsigned char addr, +extern int npe_miiphy_write (const char *devname, unsigned char addr, unsigned char reg, unsigned short value); #endif /* ifndef NPE_H */ diff --git a/arch/arm/cpu/ixp/npe/miiphy.c b/arch/arm/cpu/ixp/npe/miiphy.c index b208c51eae..4b0201a357 100644 --- a/arch/arm/cpu/ixp/npe/miiphy.c +++ b/arch/arm/cpu/ixp/npe/miiphy.c @@ -100,7 +100,7 @@ int phy_setup_aneg (char *devname, unsigned char addr) } -int npe_miiphy_read (char *devname, unsigned char addr, +int npe_miiphy_read (const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) { u16 val; @@ -112,7 +112,7 @@ int npe_miiphy_read (char *devname, unsigned char addr, } /* phy_read */ -int npe_miiphy_write (char *devname, unsigned char addr, +int npe_miiphy_write (const char *devname, unsigned char addr, unsigned char reg, unsigned short value) { ixEthAccMiiWriteRtn(addr, reg, value); diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h index 9edb0be5f5..0104418b43 100644 --- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h +++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h @@ -59,6 +59,11 @@ #define KW_USB20_BASE (KW_REGISTER(0x50000)) #define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) #define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) +#define KW_SATA_BASE (KW_REGISTER(0x80000)) + +/* Kirkwood Sata controller has two ports */ +#define KW_SATA_PORT0_OFFSET 0x2000 +#define KW_SATA_PORT1_OFFSET 0x4000 /* Kirkwood GbE controller has two ports */ #define MAX_MVGBE_DEVS 2 diff --git a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h new file mode 100644 index 0000000000..0bc5279137 --- /dev/null +++ b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef ASM_OFFSETS_H +#define ASM_OFFSETS_H + +/* + * Offset definitions for DDR controller + */ +#define DDR2_DRIC 0x00 +#define DDR2_DRIC1 0x02 +#define DDR2_DRIC2 0x04 +#define DDR2_DRCA 0x06 +#define DDR2_DRCM 0x08 +#define DDR2_DRCST1 0x0a +#define DDR2_DRCST2 0x0c +#define DDR2_DRCR 0x0e +#define DDR2_DRCF 0x20 +#define DDR2_DRASR 0x30 +#define DDR2_DRIMS 0x50 +#define DDR2_DROS 0x60 +#define DDR2_DRIBSODT1 0x64 +#define DDR2_DROABA 0x70 +#define DDR2_DROBS 0x84 + +/* + * Offset definitions Chip Control Module + */ +#define CCNT_CDCRC 0xec + +/* + * Offset definitions clock reset generator + */ +#define CRG_CRPR 0x00 +#define CRG_CRHA 0x18 +#define CRG_CRPA 0x1c +#define CRG_CRPB 0x20 +#define CRG_CRHB 0x24 +#define CRG_CRAM 0x28 + +/* + * Offset definitions External bus interface + */ +#define MEMC_MCFMODE0 0x00 +#define MEMC_MCFMODE2 0x08 +#define MEMC_MCFMODE4 0x10 +#define MEMC_MCFTIM0 0x20 +#define MEMC_MCFTIM2 0x28 +#define MEMC_MCFTIM4 0x30 +#define MEMC_MCFAREA0 0x40 +#define MEMC_MCFAREA2 0x48 +#define MEMC_MCFAREA4 0x50 + +#endif /* ASM_OFFSETS_H */ diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h new file mode 100644 index 0000000000..d1e57c0349 --- /dev/null +++ b/arch/arm/include/asm/arch-mb86r0x/hardware.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * + * Author : Carsten Schneider, mycable GmbH + * <cs@mycable.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> +#include <asm/arch/mb86r0x.h> + +#endif diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h new file mode 100644 index 0000000000..36a28b7af3 --- /dev/null +++ b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h @@ -0,0 +1,573 @@ +/* + * (C) Copyright 2007 + * + * mb86r0x definitions + * + * Author : Carsten Schneider, mycable GmbH + * <cs@mycable.de> + * + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MB86R0X_H +#define MB86R0X_H + +#ifndef __ASSEMBLY__ + +/* GPIO registers */ +struct mb86r0x_gpio { + uint32_t gpdr0; + uint32_t gpdr1; + uint32_t gpdr2; + uint32_t res; + uint32_t gpddr0; + uint32_t gpddr1; + uint32_t gpddr2; +}; + +/* PWM registers */ +struct mb86r0x_pwm { + uint32_t bcr; + uint32_t tpr; + uint32_t pr; + uint32_t dr; + uint32_t cr; + uint32_t sr; + uint32_t ccr; + uint32_t ir; +}; + +/* The mb86r0x chip control (CCNT) register set. */ +struct mb86r0x_ccnt { + uint32_t ccid; + uint32_t csrst; + uint32_t pad0[2]; + uint32_t cist; + uint32_t cistm; + uint32_t cgpio_ist; + uint32_t cgpio_istm; + uint32_t cgpio_ip; + uint32_t cgpio_im; + uint32_t caxi_bw; + uint32_t caxi_ps; + uint32_t cmux_md; + uint32_t cex_pin_st; + uint32_t cmlb; + uint32_t pad1[1]; + uint32_t cusb; + uint32_t pad2[41]; + uint32_t cbsc; + uint32_t cdcrc; + uint32_t cmsr0; + uint32_t cmsr1; + uint32_t pad3[2]; +}; + +/* The mb86r0x clock reset generator */ +struct mb86r0x_crg { + uint32_t crpr; + uint32_t pad0; + uint32_t crwr; + uint32_t crsr; + uint32_t crda; + uint32_t crdb; + uint32_t crha; + uint32_t crpa; + uint32_t crpb; + uint32_t crhb; + uint32_t cram; +}; + +/* The mb86r0x timer */ +struct mb86r0x_timer { + uint32_t load; + uint32_t value; + uint32_t control; + uint32_t intclr; + uint32_t ris; + uint32_t mis; + uint32_t bgload; +}; + +/* mb86r0x gdc display controller */ +struct mb86r0x_gdc_dsp { + /* Display settings */ + uint32_t dcm0; + uint16_t pad00; + uint16_t htp; + uint16_t hdp; + uint16_t hdb; + uint16_t hsp; + uint8_t hsw; + uint8_t vsw; + uint16_t pad01; + uint16_t vtr; + uint16_t vsp; + uint16_t vdp; + uint16_t wx; + uint16_t wy; + uint16_t ww; + uint16_t wh; + + /* Layer 0 */ + uint32_t l0m; + uint32_t l0oa; + uint32_t l0da; + uint16_t l0dx; + uint16_t l0dy; + + /* Layer 1 */ + uint32_t l1m; + uint32_t cbda0; + uint32_t cbda1; + uint32_t pad02; + + /* Layer 2 */ + uint32_t l2m; + uint32_t l2oa0; + uint32_t l2da0; + uint32_t l2oa1; + uint32_t l2da1; + uint16_t l2dx; + uint16_t l2dy; + + /* Layer 3 */ + uint32_t l3m; + uint32_t l3oa0; + uint32_t l3da0; + uint32_t l3oa1; + uint32_t l3da1; + uint16_t l3dx; + uint16_t l3dy; + + /* Layer 4 */ + uint32_t l4m; + uint32_t l4oa0; + uint32_t l4da0; + uint32_t l4oa1; + uint32_t l4da1; + uint16_t l4dx; + uint16_t l4dy; + + /* Layer 5 */ + uint32_t l5m; + uint32_t l5oa0; + uint32_t l5da0; + uint32_t l5oa1; + uint32_t l5da1; + uint16_t l5dx; + uint16_t l5dy; + + /* Cursor */ + uint16_t cutc; + uint8_t cpm; + uint8_t csize; + uint32_t cuoa0; + uint16_t cux0; + uint16_t cuy0; + uint32_t cuoa1; + uint16_t cux1; + uint16_t cuy1; + + /* Layer blending */ + uint32_t l0bld; + uint32_t pad03; + uint32_t l0tc; + uint16_t l3tc; + uint16_t l2tc; + uint32_t pad04[15]; + + /* Display settings */ + uint32_t dcm1; + uint32_t dcm2; + uint32_t dcm3; + uint32_t pad05; + + /* Layer 0 extended */ + uint32_t l0em; + uint16_t l0wx; + uint16_t l0wy; + uint16_t l0ww; + uint16_t l0wh; + uint32_t pad06; + + /* Layer 1 extended */ + uint32_t l1em; + uint16_t l1wx; + uint16_t l1wy; + uint16_t l1ww; + uint16_t l1wh; + uint32_t pad07; + + /* Layer 2 extended */ + uint32_t l2em; + uint16_t l2wx; + uint16_t l2wy; + uint16_t l2ww; + uint16_t l2wh; + uint32_t pad08; + + /* Layer 3 extended */ + uint32_t l3em; + uint16_t l3wx; + uint16_t l3wy; + uint16_t l3ww; + uint16_t l3wh; + uint32_t pad09; + + /* Layer 4 extended */ + uint32_t l4em; + uint16_t l4wx; + uint16_t l4wy; + uint16_t l4ww; + uint16_t l4wh; + uint32_t pad10; + + /* Layer 5 extended */ + uint32_t l5em; + uint16_t l5wx; + uint16_t l5wy; + uint16_t l5ww; + uint16_t l5wh; + uint32_t pad11; + + /* Multi screen control */ + uint32_t msc; + uint32_t pad12[3]; + uint32_t dls; + uint32_t dbgc; + + /* Layer blending */ + uint32_t l1bld; + uint32_t l2bld; + uint32_t l3bld; + uint32_t l4bld; + uint32_t l5bld; + uint32_t pad13; + + /* Extended transparency control */ + uint32_t l0etc; + uint32_t l1etc; + uint32_t l2etc; + uint32_t l3etc; + uint32_t l4etc; + uint32_t l5etc; + uint32_t pad14[10]; + + /* YUV coefficients */ + uint32_t l1ycr0; + uint32_t l1ycr1; + uint32_t l1ycg0; + uint32_t l1ycg1; + uint32_t l1ycb0; + uint32_t l1ycb1; + uint32_t pad15[130]; + + /* Layer palletes */ + uint32_t l0pal[256]; + uint32_t l1pal[256]; + uint32_t pad16[256]; + uint32_t l2pal[256]; + uint32_t l3pal[256]; + uint32_t pad17[256]; + + /* PWM settings */ + uint32_t vpwmm; + uint16_t vpwms; + uint16_t vpwme; + uint32_t vpwmc; + uint32_t pad18[253]; +}; + +/* mb86r0x gdc capture controller */ +struct mb86r0x_gdc_cap { + uint32_t vcm; + uint32_t csc; + uint32_t vcs; + uint32_t pad01; + + uint32_t cbm; + uint32_t cboa; + uint32_t cbla; + uint16_t cihstr; + uint16_t civstr; + uint16_t cihend; + uint16_t civend; + uint32_t pad02; + + uint32_t chp; + uint32_t cvp; + uint32_t pad03[4]; + + uint32_t clpf; + uint32_t pad04; + uint32_t cmss; + uint32_t cmds; + uint32_t pad05[12]; + + uint32_t rgbhc; + uint32_t rgbhen; + uint32_t rgbven; + uint32_t pad06; + uint32_t rgbs; + uint32_t pad07[11]; + + uint32_t rgbcmy; + uint32_t rgbcmcb; + uint32_t rgbcmcr; + uint32_t rgbcmb; + uint32_t pad08[12 + 1984]; +}; + +/* mb86r0x gdc draw */ +struct mb86r0x_gdc_draw { + uint32_t ys; + uint32_t xs; + uint32_t dxdy; + uint32_t xus; + uint32_t dxudy; + uint32_t xls; + uint32_t dxldy; + uint32_t usn; + uint32_t lsn; + uint32_t pad01[7]; + uint32_t rs; + uint32_t drdx; + uint32_t drdy; + uint32_t gs; + uint32_t dgdx; + uint32_t dgdy; + uint32_t bs; + uint32_t dbdx; + uint32_t dbdy; + uint32_t pad02[7]; + uint32_t zs; + uint32_t dzdx; + uint32_t dzdy; + uint32_t pad03[13]; + uint32_t ss; + uint32_t dsdx; + uint32_t dsdy; + uint32_t ts; + uint32_t dtdx; + uint32_t dtdy; + uint32_t qs; + uint32_t dqdx; + uint32_t dqdy; + uint32_t pad04[23]; + uint32_t lpn; + uint32_t lxs; + uint32_t lxde; + uint32_t lys; + uint32_t lyde; + uint32_t lzs; + uint32_t lzde; + uint32_t pad05[13]; + uint32_t pxdc; + uint32_t pydc; + uint32_t pzdc; + uint32_t pad06[25]; + uint32_t rxs; + uint32_t rys; + uint32_t rsizex; + uint32_t rsizey; + uint32_t pad07[12]; + uint32_t saddr; + uint32_t sstride; + uint32_t srx; + uint32_t sry; + uint32_t daddr; + uint32_t dstride; + uint32_t drx; + uint32_t dry; + uint32_t brsizex; + uint32_t brsizey; + uint32_t tcolor; + uint32_t pad08[93]; + uint32_t blpo; + uint32_t pad09[7]; + uint32_t ctr; + uint32_t ifsr; + uint32_t ifcnt; + uint32_t sst; + uint32_t ds; + uint32_t pst; + uint32_t est; + uint32_t pad10; + uint32_t mdr0; + uint32_t mdr1; + uint32_t mdr2; + uint32_t mdr3; + uint32_t mdr4; + uint32_t pad14[2]; + uint32_t mdr7; + uint32_t fbr; + uint32_t xres; + uint32_t zbr; + uint32_t tbr; + uint32_t pfbr; + uint32_t cxmin; + uint32_t cxmax; + uint32_t cymin; + uint32_t cymax; + uint32_t txs; + uint32_t tis; + uint32_t toa; + uint32_t sho; + uint32_t abr; + uint32_t pad15[2]; + uint32_t fc; + uint32_t bc; + uint32_t alf; + uint32_t blp; + uint32_t pad16; + uint32_t tbc; + uint32_t pad11[42]; + uint32_t lx0dc; + uint32_t ly0dc; + uint32_t lx1dc; + uint32_t ly1dc; + uint32_t pad12[12]; + uint32_t x0dc; + uint32_t y0dc; + uint32_t x1dc; + uint32_t y1dc; + uint32_t x2dc; + uint32_t y2dc; + uint32_t pad13[666]; +}; + +/* mb86r0x gdc geometry engine */ +struct mb86r0x_gdc_geom { + uint32_t gctr; + uint32_t pad00[15]; + uint32_t gmdr0; + uint32_t gmdr1; + uint32_t gmdr2; + uint32_t pad01[237]; + uint32_t dfifog; + uint32_t pad02[767]; +}; + +/* mb86r0x gdc */ +struct mb86r0x_gdc { + uint32_t pad00[2]; + uint32_t lts; + uint32_t pad01; + uint32_t lsta; + uint32_t pad02[3]; + uint32_t ist; + uint32_t imask; + uint32_t pad03[6]; + uint32_t lsa; + uint32_t lco; + uint32_t lreq; + + uint32_t pad04[16*1024 - 19]; + struct mb86r0x_gdc_dsp dsp0; + struct mb86r0x_gdc_dsp dsp1; + uint32_t pad05[4*1024 - 2]; + uint32_t vccc; + uint32_t vcsr; + struct mb86r0x_gdc_cap cap0; + struct mb86r0x_gdc_cap cap1; + uint32_t pad06[4*1024]; + uint32_t texture_base[16*1024]; + struct mb86r0x_gdc_draw draw; + uint32_t pad07[7*1024]; + struct mb86r0x_gdc_geom geom; + uint32_t pad08[7*1024]; +}; + +#endif /* __ASSEMBLY__ */ + +/* + * Physical Address Defines + */ +#define MB86R0x_DDR2_BASE 0xf3000000 +#define MB86R0x_GDC_BASE 0xf1fc0000 +#define MB86R0x_CCNT_BASE 0xfff42000 +#define MB86R0x_CAN0_BASE 0xfff54000 +#define MB86R0x_CAN1_BASE 0xfff55000 +#define MB86R0x_I2C0_BASE 0xfff56000 +#define MB86R0x_I2C1_BASE 0xfff57000 +#define MB86R0x_EHCI_BASE 0xfff80000 +#define MB86R0x_OHCI_BASE 0xfff81000 +#define MB86R0x_IRC1_BASE 0xfffb0000 +#define MB86R0x_MEMC_BASE 0xfffc0000 +#define MB86R0x_TIMER_BASE 0xfffe0000 +#define MB86R0x_UART0_BASE 0xfffe1000 +#define MB86R0x_UART1_BASE 0xfffe2000 +#define MB86R0x_IRCE_BASE 0xfffe4000 +#define MB86R0x_CRG_BASE 0xfffe7000 +#define MB86R0x_IRC0_BASE 0xfffe8000 +#define MB86R0x_GPIO_BASE 0xfffe9000 +#define MB86R0x_PWM0_BASE 0xfff41000 +#define MB86R0x_PWM1_BASE 0xfff41100 + +#define MB86R0x_CRSR_SWRSTREQ (1 << 1) + +/* + * Timer register bits + */ +#define MB86R0x_TIMER_ENABLE (1 << 7) +#define MB86R0x_TIMER_MODE_MSK (1 << 6) +#define MB86R0x_TIMER_MODE_FR (0 << 6) +#define MB86R0x_TIMER_MODE_PD (1 << 6) + +#define MB86R0x_TIMER_INT_EN (1 << 5) +#define MB86R0x_TIMER_PRS_MSK (3 << 2) +#define MB86R0x_TIMER_PRS_4S (1 << 2) +#define MB86R0x_TIMER_PRS_8S (1 << 3) +#define MB86R0x_TIMER_SIZE_32 (1 << 1) +#define MB86R0x_TIMER_ONE_SHT (1 << 0) + +/* + * Clock reset generator bits + */ +#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8) +#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0) +/* + * DDR2 controller bits + */ +#define MB86R0x_DDR2_DRCI_DRINI (1 << 15) +#define MB86R0x_DDR2_DRCI_CKEN (1 << 14) +#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0) +#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \ + MB86R0x_DDR2_DRCI_CKEN | \ + MB86R0x_DDR2_DRCI_DRCMD) +#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \ + MB86R0x_DDR2_DRCI_CKEN) +#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN +#endif /* MB86R0X_H */ diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h index 19046aaab4..6f645192a7 100644 --- a/arch/arm/include/asm/arch-omap24xx/i2c.h +++ b/arch/arm/include/asm/arch-omap24xx/i2c.h @@ -36,7 +36,9 @@ struct i2c { unsigned short stat; /* 0x08 */ unsigned short res3; unsigned short iv; /* 0x0C */ - unsigned short res4[3]; + unsigned short res4; + unsigned short syss; /* 0x10 */ + unsigned short res4p1; unsigned short buf; /* 0x14 */ unsigned short res5; unsigned short cnt; /* 0x18 */ @@ -63,110 +65,4 @@ struct i2c { #define I2C_BUS_MAX 2 -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */ -#define OMAP_I2C_STANDARD 100000 -#define OMAP_I2C_FAST_MODE 400000 -#define OMAP_I2C_HIGH_SPEED 3400000 - -#define SYSTEM_CLOCK_12 12000000 -#define SYSTEM_CLOCK_13 13000000 -#define SYSTEM_CLOCK_192 19200000 -#define SYSTEM_CLOCK_96 96000000 - -#ifndef I2C_IP_CLK -#define I2C_IP_CLK SYSTEM_CLOCK_96 -#endif - -#ifndef I2C_INTERNAL_SAMPLING_CLK -#define I2C_INTERNAL_SAMPLING_CLK 19200000 -#endif - -/* These are the trim values for standard and fast speed */ -#ifndef I2C_FASTSPEED_SCLL_TRIM -#define I2C_FASTSPEED_SCLL_TRIM 6 -#endif -#ifndef I2C_FASTSPEED_SCLH_TRIM -#define I2C_FASTSPEED_SCLH_TRIM 6 -#endif - -/* These are the trim values for high speed */ -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif - -#define I2C_PSC_MAX 0x0f -#define I2C_PSC_MIN 0x00 - - #endif diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h new file mode 100644 index 0000000000..81942a8063 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/am35x_def.h @@ -0,0 +1,52 @@ +/* + * am35x_def.h - TI's AM35x specific definitions. + * + * Based on arch/arm/include/asm/arch-omap3/cpu.h + * + * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> + * + * Copyright (c) 2010 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AM35X_DEF_H_ +#define _AM35X_DEF_H_ + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ + +/* General register mappings of system control module */ +#define AM35X_SCM_GEN_BASE 0x48002270 +struct am35x_scm_general { + u32 res1[0xC4]; /* 0x000 - 0x30C */ + u32 devconf2; /* 0x310 */ + u32 devconf3; /* 0x314 */ + u32 res2[0x2]; /* 0x318 - 0x31C */ + u32 cba_priority; /* 0x320 */ + u32 lvl_intr_clr; /* 0x324 */ + u32 ip_sw_reset; /* 0x328 */ + u32 ipss_clk_ctrl; /* 0x32C */ +}; +#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE) + +#endif /*__ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#endif /* _AM35X_DEF_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index c072c27bbf..390b007945 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -483,4 +483,7 @@ struct pm { #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) +/* MUSB base */ +#define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap3/i2c.h b/arch/arm/include/asm/arch-omap3/i2c.h index 7a4a73aa91..d2e7488fd1 100644 --- a/arch/arm/include/asm/arch-omap3/i2c.h +++ b/arch/arm/include/asm/arch-omap3/i2c.h @@ -34,7 +34,9 @@ struct i2c { unsigned short stat; /* 0x08 */ unsigned short res3; unsigned short iv; /* 0x0C */ - unsigned short res4[3]; + unsigned short res4; + unsigned short syss; /* 0x10 */ + unsigned short res4a; unsigned short buf; /* 0x14 */ unsigned short res5; unsigned short cnt; /* 0x18 */ diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index c056b9501b..7d5748acd4 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -139,4 +139,7 @@ struct watchdog { #define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) #define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) +/* MUSB base */ +#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h new file mode 100644 index 0000000000..019574b09f --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/mux_omap4.h @@ -0,0 +1,344 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated + * Richard Woodruff <r-woodruff2@ti.com> + * Aneesh V <aneesh@ti.com> + * Balaji Krishnamoorthy <balajitk@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_OMAP4_H_ +#define _MUX_OMAP4_H_ + +#include <asm/types.h> + +struct pad_conf_entry { + + u16 offset; + + u16 val; + +} __attribute__ ((packed)); + +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif + +#define IEN (1 << 8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD (1 << 3) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#define SAFE_MODE M7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif + +#define CORE_REVISION 0x0000 +#define CORE_HWINFO 0x0004 +#define CORE_SYSCONFIG 0x0010 +#define GPMC_AD0 0x0040 +#define GPMC_AD1 0x0042 +#define GPMC_AD2 0x0044 +#define GPMC_AD3 0x0046 +#define GPMC_AD4 0x0048 +#define GPMC_AD5 0x004A +#define GPMC_AD6 0x004C +#define GPMC_AD7 0x004E +#define GPMC_AD8 0x0050 +#define GPMC_AD9 0x0052 +#define GPMC_AD10 0x0054 +#define GPMC_AD11 0x0056 +#define GPMC_AD12 0x0058 +#define GPMC_AD13 0x005A +#define GPMC_AD14 0x005C +#define GPMC_AD15 0x005E +#define GPMC_A16 0x0060 +#define GPMC_A17 0x0062 +#define GPMC_A18 0x0064 +#define GPMC_A19 0x0066 +#define GPMC_A20 0x0068 +#define GPMC_A21 0x006A +#define GPMC_A22 0x006C +#define GPMC_A23 0x006E +#define GPMC_A24 0x0070 +#define GPMC_A25 0x0072 +#define GPMC_NCS0 0x0074 +#define GPMC_NCS1 0x0076 +#define GPMC_NCS2 0x0078 +#define GPMC_NCS3 0x007A +#define GPMC_NWP 0x007C +#define GPMC_CLK 0x007E +#define GPMC_NADV_ALE 0x0080 +#define GPMC_NOE 0x0082 +#define GPMC_NWE 0x0084 +#define GPMC_NBE0_CLE 0x0086 +#define GPMC_NBE1 0x0088 +#define GPMC_WAIT0 0x008A +#define GPMC_WAIT1 0x008C +#define C2C_DATA11 0x008E +#define C2C_DATA12 0x0090 +#define C2C_DATA13 0x0092 +#define C2C_DATA14 0x0094 +#define C2C_DATA15 0x0096 +#define HDMI_HPD 0x0098 +#define HDMI_CEC 0x009A +#define HDMI_DDC_SCL 0x009C +#define HDMI_DDC_SDA 0x009E +#define CSI21_DX0 0x00A0 +#define CSI21_DY0 0x00A2 +#define CSI21_DX1 0x00A4 +#define CSI21_DY1 0x00A6 +#define CSI21_DX2 0x00A8 +#define CSI21_DY2 0x00AA +#define CSI21_DX3 0x00AC +#define CSI21_DY3 0x00AE +#define CSI21_DX4 0x00B0 +#define CSI21_DY4 0x00B2 +#define CSI22_DX0 0x00B4 +#define CSI22_DY0 0x00B6 +#define CSI22_DX1 0x00B8 +#define CSI22_DY1 0x00BA +#define CAM_SHUTTER 0x00BC +#define CAM_STROBE 0x00BE +#define CAM_GLOBALRESET 0x00C0 +#define USBB1_ULPITLL_CLK 0x00C2 +#define USBB1_ULPITLL_STP 0x00C4 +#define USBB1_ULPITLL_DIR 0x00C6 +#define USBB1_ULPITLL_NXT 0x00C8 +#define USBB1_ULPITLL_DAT0 0x00CA +#define USBB1_ULPITLL_DAT1 0x00CC +#define USBB1_ULPITLL_DAT2 0x00CE +#define USBB1_ULPITLL_DAT3 0x00D0 +#define USBB1_ULPITLL_DAT4 0x00D2 +#define USBB1_ULPITLL_DAT5 0x00D4 +#define USBB1_ULPITLL_DAT6 0x00D6 +#define USBB1_ULPITLL_DAT7 0x00D8 +#define USBB1_HSIC_DATA 0x00DA +#define USBB1_HSIC_STROBE 0x00DC +#define USBC1_ICUSB_DP 0x00DE +#define USBC1_ICUSB_DM 0x00E0 +#define SDMMC1_CLK 0x00E2 +#define SDMMC1_CMD 0x00E4 +#define SDMMC1_DAT0 0x00E6 +#define SDMMC1_DAT1 0x00E8 +#define SDMMC1_DAT2 0x00EA +#define SDMMC1_DAT3 0x00EC +#define SDMMC1_DAT4 0x00EE +#define SDMMC1_DAT5 0x00F0 +#define SDMMC1_DAT6 0x00F2 +#define SDMMC1_DAT7 0x00F4 +#define ABE_MCBSP2_CLKX 0x00F6 +#define ABE_MCBSP2_DR 0x00F8 +#define ABE_MCBSP2_DX 0x00FA +#define ABE_MCBSP2_FSX 0x00FC +#define ABE_MCBSP1_CLKX 0x00FE +#define ABE_MCBSP1_DR 0x0100 +#define ABE_MCBSP1_DX 0x0102 +#define ABE_MCBSP1_FSX 0x0104 +#define ABE_PDM_UL_DATA 0x0106 +#define ABE_PDM_DL_DATA 0x0108 +#define ABE_PDM_FRAME 0x010A +#define ABE_PDM_LB_CLK 0x010C +#define ABE_CLKS 0x010E +#define ABE_DMIC_CLK1 0x0110 +#define ABE_DMIC_DIN1 0x0112 +#define ABE_DMIC_DIN2 0x0114 +#define ABE_DMIC_DIN3 0x0116 +#define UART2_CTS 0x0118 +#define UART2_RTS 0x011A +#define UART2_RX 0x011C +#define UART2_TX 0x011E +#define HDQ_SIO 0x0120 +#define I2C1_SCL 0x0122 +#define I2C1_SDA 0x0124 +#define I2C2_SCL 0x0126 +#define I2C2_SDA 0x0128 +#define I2C3_SCL 0x012A +#define I2C3_SDA 0x012C +#define I2C4_SCL 0x012E +#define I2C4_SDA 0x0130 +#define MCSPI1_CLK 0x0132 +#define MCSPI1_SOMI 0x0134 +#define MCSPI1_SIMO 0x0136 +#define MCSPI1_CS0 0x0138 +#define MCSPI1_CS1 0x013A +#define MCSPI1_CS2 0x013C +#define MCSPI1_CS3 0x013E +#define UART3_CTS_RCTX 0x0140 +#define UART3_RTS_SD 0x0142 +#define UART3_RX_IRRX 0x0144 +#define UART3_TX_IRTX 0x0146 +#define SDMMC5_CLK 0x0148 +#define SDMMC5_CMD 0x014A +#define SDMMC5_DAT0 0x014C +#define SDMMC5_DAT1 0x014E +#define SDMMC5_DAT2 0x0150 +#define SDMMC5_DAT3 0x0152 +#define MCSPI4_CLK 0x0154 +#define MCSPI4_SIMO 0x0156 +#define MCSPI4_SOMI 0x0158 +#define MCSPI4_CS0 0x015A +#define UART4_RX 0x015C +#define UART4_TX 0x015E +#define USBB2_ULPITLL_CLK 0x0160 +#define USBB2_ULPITLL_STP 0x0162 +#define USBB2_ULPITLL_DIR 0x0164 +#define USBB2_ULPITLL_NXT 0x0166 +#define USBB2_ULPITLL_DAT0 0x0168 +#define USBB2_ULPITLL_DAT1 0x016A +#define USBB2_ULPITLL_DAT2 0x016C +#define USBB2_ULPITLL_DAT3 0x016E +#define USBB2_ULPITLL_DAT4 0x0170 +#define USBB2_ULPITLL_DAT5 0x0172 +#define USBB2_ULPITLL_DAT6 0x0174 +#define USBB2_ULPITLL_DAT7 0x0176 +#define USBB2_HSIC_DATA 0x0178 +#define USBB2_HSIC_STROBE 0x017A +#define UNIPRO_TX0 0x017C +#define UNIPRO_TY0 0x017E +#define UNIPRO_TX1 0x0180 +#define UNIPRO_TY1 0x0182 +#define UNIPRO_TX2 0x0184 +#define UNIPRO_TY2 0x0186 +#define UNIPRO_RX0 0x0188 +#define UNIPRO_RY0 0x018A +#define UNIPRO_RX1 0x018C +#define UNIPRO_RY1 0x018E +#define UNIPRO_RX2 0x0190 +#define UNIPRO_RY2 0x0192 +#define USBA0_OTG_CE 0x0194 +#define USBA0_OTG_DP 0x0196 +#define USBA0_OTG_DM 0x0198 +#define FREF_CLK1_OUT 0x019A +#define FREF_CLK2_OUT 0x019C +#define SYS_NIRQ1 0x019E +#define SYS_NIRQ2 0x01A0 +#define SYS_BOOT0 0x01A2 +#define SYS_BOOT1 0x01A4 +#define SYS_BOOT2 0x01A6 +#define SYS_BOOT3 0x01A8 +#define SYS_BOOT4 0x01AA +#define SYS_BOOT5 0x01AC +#define DPM_EMU0 0x01AE +#define DPM_EMU1 0x01B0 +#define DPM_EMU2 0x01B2 +#define DPM_EMU3 0x01B4 +#define DPM_EMU4 0x01B6 +#define DPM_EMU5 0x01B8 +#define DPM_EMU6 0x01BA +#define DPM_EMU7 0x01BC +#define DPM_EMU8 0x01BE +#define DPM_EMU9 0x01C0 +#define DPM_EMU10 0x01C2 +#define DPM_EMU11 0x01C4 +#define DPM_EMU12 0x01C6 +#define DPM_EMU13 0x01C8 +#define DPM_EMU14 0x01CA +#define DPM_EMU15 0x01CC +#define DPM_EMU16 0x01CE +#define DPM_EMU17 0x01D0 +#define DPM_EMU18 0x01D2 +#define DPM_EMU19 0x01D4 +#define WAKEUPEVENT_0 0x01D8 +#define WAKEUPEVENT_1 0x01DC +#define WAKEUPEVENT_2 0x01E0 +#define WAKEUPEVENT_3 0x01E4 +#define WAKEUPEVENT_4 0x01E8 +#define WAKEUPEVENT_5 0x01EC +#define WAKEUPEVENT_6 0x01F0 + +#define WKUP_REVISION 0x0000 +#define WKUP_HWINFO 0x0004 +#define WKUP_SYSCONFIG 0x0010 +#define PAD0_SIM_IO 0x0040 +#define PAD1_SIM_CLK 0x0042 +#define PAD0_SIM_RESET 0x0044 +#define PAD1_SIM_CD 0x0046 +#define PAD0_SIM_PWRCTRL 0x0048 +#define PAD1_SR_SCL 0x004A +#define PAD0_SR_SDA 0x004C +#define PAD1_FREF_XTAL_IN 0x004E +#define PAD0_FREF_SLICER_IN 0x0050 +#define PAD1_FREF_CLK_IOREQ 0x0052 +#define PAD0_FREF_CLK0_OUT 0x0054 +#define PAD1_FREF_CLK3_REQ 0x0056 +#define PAD0_FREF_CLK3_OUT 0x0058 +#define PAD1_FREF_CLK4_REQ 0x005A +#define PAD0_FREF_CLK4_OUT 0x005C +#define PAD1_SYS_32K 0x005E +#define PAD0_SYS_NRESPWRON 0x0060 +#define PAD1_SYS_NRESWARM 0x0062 +#define PAD0_SYS_PWR_REQ 0x0064 +#define PAD1_SYS_PWRON_RESET 0x0066 +#define PAD0_SYS_BOOT6 0x0068 +#define PAD1_SYS_BOOT7 0x006A +#define PAD0_JTAG_NTRST 0x006C +#define PAD1_JTAG_TCK 0x006D +#define PAD0_JTAG_RTCK 0x0070 +#define PAD1_JTAG_TMS_TMSC 0x0072 +#define PAD0_JTAG_TDI 0x0074 +#define PAD1_JTAG_TDO 0x0076 +#define PADCONF_WAKEUPEVENT_0 0x007C +#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 +#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 +#define PADCONF_MODE 0x05A8 +#define CONTROL_XTAL_OSCILLATOR 0x05AC +#define CONTROL_CONTROL_I2C_2 0x0604 +#define CONTROL_CONTROL_JTAG 0x0608 +#define CONTROL_CONTROL_SYS 0x060C +#define CONTROL_SPARE_RW 0x0614 +#define CONTROL_SPARE_R 0x0618 +#define CONTROL_SPARE_R_C0 0x061C + +#endif /* _MUX_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index 5243ea8e7f..79ff22cf31 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -44,6 +44,8 @@ /* CONTROL */ #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000) +#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) +#define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000) /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index c6fab002fb..ad0c640dfd 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -32,6 +32,7 @@ void gpmc_init(void); void watchdog_init(void); u32 get_device_type(void); void invalidate_dcache(u32); +void set_muxconf_regs(void); extern const struct omap_sysinfo sysinfo; diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index 22e2dd3046..6ce02a9212 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -75,35 +75,91 @@ enum orion5x_cpu_attrib { }; /* - * Default Device Address MAP BAR values + * Device Address MAP BAR values + * + * All addresses and sizes not defined by board code + * will be given default values here. */ -#define ORION5X_DEFADR_PCIE_MEM 0x90000000 -#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000 -#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0 -#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024) -#define ORION5X_DEFADR_PCIE_IO 0xf0000000 -#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000 -#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0 -#define ORION5X_DEFSZ_PCIE_IO (64*1024) +#if !defined (ORION5X_ADR_PCIE_MEM) +#define ORION5X_ADR_PCIE_MEM 0x90000000 +#endif + +#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO) +#define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000 +#endif + +#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI) +#define ORION5X_ADR_PCIE_MEM_REMAP_HI 0 +#endif + +#if !defined (ORION5X_SZ_PCIE_MEM) +#define ORION5X_SZ_PCIE_MEM (128*1024*1024) +#endif + +#if !defined (ORION5X_ADR_PCIE_IO) +#define ORION5X_ADR_PCIE_IO 0xf0000000 +#endif + +#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO) +#define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000 +#endif + +#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI) +#define ORION5X_ADR_PCIE_IO_REMAP_HI 0 +#endif + +#if !defined (ORION5X_SZ_PCIE_IO) +#define ORION5X_SZ_PCIE_IO (64*1024) +#endif + +#if !defined (ORION5X_ADR_PCI_MEM) +#define ORION5X_ADR_PCI_MEM 0x98000000 +#endif + +#if !defined (ORION5X_SZ_PCI_MEM) +#define ORION5X_SZ_PCI_MEM (128*1024*1024) +#endif + +#if !defined (ORION5X_ADR_PCI_IO) +#define ORION5X_ADR_PCI_IO 0xf0100000 +#endif + +#if !defined (ORION5X_SZ_PCI_IO) +#define ORION5X_SZ_PCI_IO (64*1024) +#endif + +#if !defined (ORION5X_ADR_DEV_CS0) +#define ORION5X_ADR_DEV_CS0 0xfa000000 +#endif + +#if !defined (ORION5X_SZ_DEV_CS0) +#define ORION5X_SZ_DEV_CS0 (2*1024*1024) +#endif -#define ORION5X_DEFADR_PCI_MEM 0x98000000 -#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024) +#if !defined (ORION5X_ADR_DEV_CS1) +#define ORION5X_ADR_DEV_CS1 0xf8000000 +#endif -#define ORION5X_DEFADR_PCI_IO 0xf0100000 -#define ORION5X_DEFSZ_PCI_IO (64*1024) +#if !defined (ORION5X_SZ_DEV_CS1) +#define ORION5X_SZ_DEV_CS1 (32*1024*1024) +#endif -#define ORION5X_DEFADR_DEV_CS0 0xfa000000 -#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024) +#if !defined (ORION5X_ADR_DEV_CS2) +#define ORION5X_ADR_DEV_CS2 0xfa800000 +#endif -#define ORION5X_DEFADR_DEV_CS1 0xf8000000 -#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024) +#if !defined (ORION5X_SZ_DEV_CS2) +#define ORION5X_SZ_DEV_CS2 (1*1024*1024) +#endif -#define ORION5X_DEFADR_DEV_CS2 0xfa800000 -#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024) +#if !defined (ORION5X_ADR_BOOTROM) +#define ORION5X_ADR_BOOTROM 0xFFF80000 +#endif -#define ORION5X_DEFADR_BOOTROM 0xFFF80000 -#define ORION5X_DEFSZ_BOOTROM (512*1024) +#if !defined (ORION5X_SZ_BOOTROM) +#define ORION5X_SZ_BOOTROM (512*1024) +#endif /* * PCIE registers are used for SoC device ID and revision diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h index d257b66581..e3d3f76dbb 100644 --- a/arch/arm/include/asm/arch-orion5x/orion5x.h +++ b/arch/arm/include/asm/arch-orion5x/orion5x.h @@ -55,6 +55,9 @@ #define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000)) #define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000)) #define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000)) +#define ORION5X_SATA_BASE (ORION5X_REGISTER(0x80000)) +#define ORION5X_SATA_PORT0_OFFSET 0x2000 +#define ORION5X_SATA_PORT1_OFFSET 0x4000 /* Orion5x GbE controller has a single port */ #define MAX_MVGBE_DEVS 1 diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index e8f3eb13aa..ff1518eb0d 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -75,13 +75,47 @@ static inline phys_addr_t virt_to_phys(void * vaddr) #define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) #define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); +extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen) +{ + uint8_t *buf = (uint8_t *)data; + while(bytelen--) + __arch_putb(*buf++, addr); +} + +extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen) +{ + uint16_t *buf = (uint16_t *)data; + while(wordlen--) + __arch_putw(*buf++, addr); +} + +extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen) +{ + uint32_t *buf = (uint32_t *)data; + while(longlen--) + __arch_putl(*buf++, addr); +} -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); +extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen) +{ + uint8_t *buf = (uint8_t *)data; + while(bytelen--) + *buf++ = __arch_getb(addr); +} + +extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen) +{ + uint16_t *buf = (uint16_t *)data; + while(wordlen--) + *buf++ = __arch_getw(addr); +} + +extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) +{ + uint32_t *buf = (uint32_t *)data; + while(longlen--) + *buf++ = __arch_getl(addr); +} #define __raw_writeb(v,a) __arch_putb(v,a) #define __raw_writew(v,a) __arch_putw(v,a) diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 940d814f8e..fd28d2b39e 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1990,7 +1990,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_BENZINA 2003 #define MACH_TYPE_BLAZE 2004 #define MACH_TYPE_LINKSTATION_LS_HGL 2005 -#define MACH_TYPE_HTCVENUS 2006 +#define MACH_TYPE_HTCKOVSKY 2006 #define MACH_TYPE_SONY_PRS505 2007 #define MACH_TYPE_HANLIN_V3 2008 #define MACH_TYPE_SAPPHIRA 2009 @@ -2862,6 +2862,90 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_MATRIX518 2879 #define MACH_TYPE_TINY_GURNARD 2880 #define MACH_TYPE_SPEAR1310 2881 +#define MACH_TYPE_BV07 2882 +#define MACH_TYPE_MXT_TD61 2883 +#define MACH_TYPE_OPENRD_ULTIMATE 2884 +#define MACH_TYPE_DEVIXP 2885 +#define MACH_TYPE_MICCPT 2886 +#define MACH_TYPE_MIC256 2887 +#define MACH_TYPE_AS1167 2888 +#define MACH_TYPE_OMAP3_IBIZA 2889 +#define MACH_TYPE_U5500 2890 +#define MACH_TYPE_DAVINCI_PICTO 2891 +#define MACH_TYPE_MECHA 2892 +#define MACH_TYPE_BUBBA3 2893 +#define MACH_TYPE_PUPITRE 2894 +#define MACH_TYPE_TEGRA_HARMONY 2895 +#define MACH_TYPE_TEGRA_VOGUE 2896 +#define MACH_TYPE_TEGRA_E1165 2897 +#define MACH_TYPE_SIMPLENET 2898 +#define MACH_TYPE_EC4350TBM 2899 +#define MACH_TYPE_PEC_TC 2900 +#define MACH_TYPE_PEC_HC2 2901 +#define MACH_TYPE_ESL_MOBILIS_A 2902 +#define MACH_TYPE_ESL_MOBILIS_B 2903 +#define MACH_TYPE_ESL_WAVE_A 2904 +#define MACH_TYPE_ESL_WAVE_B 2905 +#define MACH_TYPE_UNISENSE_MMM 2906 +#define MACH_TYPE_BLUESHARK 2907 +#define MACH_TYPE_E10 2908 +#define MACH_TYPE_APP3K_ROBIN 2909 +#define MACH_TYPE_POV15HD 2910 +#define MACH_TYPE_STELLA 2911 +#define MACH_TYPE_LINKSTATION_LSCHL 2913 +#define MACH_TYPE_NETWALKER 2914 +#define MACH_TYPE_ACSX106 2915 +#define MACH_TYPE_ATLAS5_C1 2916 +#define MACH_TYPE_NSB3AST 2917 +#define MACH_TYPE_GNET_SLC 2918 +#define MACH_TYPE_AF4000 2919 +#define MACH_TYPE_ARK9431 2920 +#define MACH_TYPE_FS_S5PC100 2921 +#define MACH_TYPE_OMAP3505NOVA8 2922 +#define MACH_TYPE_OMAP3621_EDP1 2923 +#define MACH_TYPE_ORATISAES 2924 +#define MACH_TYPE_SMDKV310 2925 +#define MACH_TYPE_SIEMENS_L0 2926 +#define MACH_TYPE_VENTANA 2927 +#define MACH_TYPE_WM8505_7IN_NETBOOK 2928 +#define MACH_TYPE_EC4350SDB 2929 +#define MACH_TYPE_MIMAS 2930 +#define MACH_TYPE_TITAN 2931 +#define MACH_TYPE_CRANEBOARD 2932 +#define MACH_TYPE_ES2440 2933 +#define MACH_TYPE_NAJAY_A9263 2934 +#define MACH_TYPE_HTCTORNADO 2935 +#define MACH_TYPE_DIMM_MX257 2936 +#define MACH_TYPE_JIGEN 2937 +#define MACH_TYPE_SMDK6450 2938 +#define MACH_TYPE_MENO_QNG 2939 +#define MACH_TYPE_NS2416 2940 +#define MACH_TYPE_RPC353 2941 +#define MACH_TYPE_TQ6410 2942 +#define MACH_TYPE_SKY6410 2943 +#define MACH_TYPE_DYNASTY 2944 +#define MACH_TYPE_VIVO 2945 +#define MACH_TYPE_BURY_BL7582 2946 +#define MACH_TYPE_BURY_BPS5270 2947 +#define MACH_TYPE_BASI 2948 +#define MACH_TYPE_TN200 2949 +#define MACH_TYPE_C2MMI 2950 +#define MACH_TYPE_MESON_6236M 2951 +#define MACH_TYPE_MESON_8626M 2952 +#define MACH_TYPE_TUBE 2953 +#define MACH_TYPE_MESSINA 2954 +#define MACH_TYPE_MX50_ARM2 2955 +#define MACH_TYPE_CETUS9263 2956 +#define MACH_TYPE_BROWNSTONE 2957 +#define MACH_TYPE_VMX25 2958 +#define MACH_TYPE_VMX51 2959 +#define MACH_TYPE_ABACUS 2960 +#define MACH_TYPE_CM4745 2961 +#define MACH_TYPE_ORATISLINK 2962 +#define MACH_TYPE_DAVINCI_DM365_DVR 2963 +#define MACH_TYPE_NETVIZ 2964 +#define MACH_TYPE_FLEXIBITY 2965 +#define MACH_TYPE_WLAN_COMPUTER 2966 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -18506,9 +18590,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_HYNET_INE # endif -# define machine_is_argonst_foundation() (machine_arch_type == MACH_TYPE_HYNET_INE) +# define machine_is_hynet_ine() (machine_arch_type == MACH_TYPE_HYNET_INE) #else -# define machine_is_argonst_foundation() (0) +# define machine_is_hynet_ine() (0) #endif #ifdef CONFIG_MACH_HYNET_APP @@ -24002,9 +24086,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_MARVELL_NEWDB # endif -# define machine_is_dove_avng() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) +# define machine_is_marvell_newdb() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) #else -# define machine_is_dove_avng() (0) +# define machine_is_marvell_newdb() (0) #endif #ifdef CONFIG_MACH_VANDIHUD @@ -26599,14 +26683,14 @@ extern unsigned int __machine_arch_type; # define machine_is_linkstation_ls_hgl() (0) #endif -#ifdef CONFIG_MACH_HTCVENUS +#ifdef CONFIG_MACH_HTCKOVSKY # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_HTCVENUS +# define machine_arch_type MACH_TYPE_HTCKOVSKY # endif -# define machine_is_htckovsky() (machine_arch_type == MACH_TYPE_HTCVENUS) +# define machine_is_htckovsky() (machine_arch_type == MACH_TYPE_HTCKOVSKY) #else # define machine_is_htckovsky() (0) #endif @@ -30374,9 +30458,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_OREO # endif -# define machine_is_oreo_camera() (machine_arch_type == MACH_TYPE_OREO) +# define machine_is_oreo() (machine_arch_type == MACH_TYPE_OREO) #else -# define machine_is_oreo_camera() (0) +# define machine_is_oreo() (0) #endif #ifdef CONFIG_MACH_SMDK6442 @@ -31166,9 +31250,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_SIENNA # endif -# define machine_is_siena() (machine_arch_type == MACH_TYPE_SIENNA) +# define machine_is_sienna() (machine_arch_type == MACH_TYPE_SIENNA) #else -# define machine_is_siena() (0) +# define machine_is_sienna() (0) #endif #ifdef CONFIG_MACH_HTC_EXCALIBUR_S620 @@ -32654,9 +32738,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_WHITESTONE # endif -# define machine_is_htcwhitestone() (machine_arch_type == MACH_TYPE_WHITESTONE) +# define machine_is_whitestone() (machine_arch_type == MACH_TYPE_WHITESTONE) #else -# define machine_is_htcwhitestone() (0) +# define machine_is_whitestone() (0) #endif #ifdef CONFIG_MACH_AT91SAM9263NIT @@ -33662,9 +33746,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_DAVINCI_CIO # endif -# define machine_is_davinci_dm6467_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO) +# define machine_is_davinci_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO) #else -# define machine_is_davinci_dm6467_cio() (0) +# define machine_is_davinci_cio() (0) #endif #ifdef CONFIG_MACH_SMARTMETER_DL @@ -33986,9 +34070,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_SHEEVAD # endif -# define machine_is_sheevad() (machine_arch_type == MACH_TYPE_SHEEVAD) +# define machine_is_gplugd() (machine_arch_type == MACH_TYPE_SHEEVAD) #else -# define machine_is_sheevad() (0) +# define machine_is_gplugd() (0) #endif #ifdef CONFIG_MACH_QSD8X50A_ST1_1 @@ -35678,9 +35762,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_HTCSHIFT # endif -# define machine_is_htcclio() (machine_arch_type == MACH_TYPE_HTCSHIFT) +# define machine_is_htcshift() (machine_arch_type == MACH_TYPE_HTCSHIFT) #else -# define machine_is_htcclio() (0) +# define machine_is_htcshift() (0) #endif #ifdef CONFIG_MACH_DAVINCI_DM365_FC @@ -35810,9 +35894,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_LPC2 # endif -# define machine_is_lpc_evo() (machine_arch_type == MACH_TYPE_LPC2) +# define machine_is_lpc2() (machine_arch_type == MACH_TYPE_LPC2) #else -# define machine_is_lpc_evo() (0) +# define machine_is_lpc2() (0) #endif #ifdef CONFIG_MACH_OLYMPUS @@ -36134,9 +36218,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_SBC9261 # endif -# define machine_is_at91sam9261() (machine_arch_type == MACH_TYPE_SBC9261) +# define machine_is_sbc9261() (machine_arch_type == MACH_TYPE_SBC9261) #else -# define machine_is_at91sam9261() (0) +# define machine_is_sbc9261() (0) #endif #ifdef CONFIG_MACH_PCBFP0001 @@ -37063,6 +37147,1014 @@ extern unsigned int __machine_arch_type; # define machine_is_spear1310() (0) #endif +#ifdef CONFIG_MACH_BV07 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BV07 +# endif +# define machine_is_bv07() (machine_arch_type == MACH_TYPE_BV07) +#else +# define machine_is_bv07() (0) +#endif + +#ifdef CONFIG_MACH_MXT_TD61 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXT_TD61 +# endif +# define machine_is_mxt_td61() (machine_arch_type == MACH_TYPE_MXT_TD61) +#else +# define machine_is_mxt_td61() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_ULTIMATE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_ULTIMATE +# endif +# define machine_is_openrd_ultimate() (machine_arch_type == MACH_TYPE_OPENRD_ULTIMATE) +#else +# define machine_is_openrd_ultimate() (0) +#endif + +#ifdef CONFIG_MACH_DEVIXP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVIXP +# endif +# define machine_is_devixp() (machine_arch_type == MACH_TYPE_DEVIXP) +#else +# define machine_is_devixp() (0) +#endif + +#ifdef CONFIG_MACH_MICCPT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICCPT +# endif +# define machine_is_miccpt() (machine_arch_type == MACH_TYPE_MICCPT) +#else +# define machine_is_miccpt() (0) +#endif + +#ifdef CONFIG_MACH_MIC256 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIC256 +# endif +# define machine_is_mic256() (machine_arch_type == MACH_TYPE_MIC256) +#else +# define machine_is_mic256() (0) +#endif + +#ifdef CONFIG_MACH_AS1167 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS1167 +# endif +# define machine_is_as1167() (machine_arch_type == MACH_TYPE_AS1167) +#else +# define machine_is_as1167() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_IBIZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_IBIZA +# endif +# define machine_is_omap3_ibiza() (machine_arch_type == MACH_TYPE_OMAP3_IBIZA) +#else +# define machine_is_omap3_ibiza() (0) +#endif + +#ifdef CONFIG_MACH_U5500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U5500 +# endif +# define machine_is_u5500() (machine_arch_type == MACH_TYPE_U5500) +#else +# define machine_is_u5500() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_PICTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_PICTO +# endif +# define machine_is_davinci_picto() (machine_arch_type == MACH_TYPE_DAVINCI_PICTO) +#else +# define machine_is_davinci_picto() (0) +#endif + +#ifdef CONFIG_MACH_MECHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MECHA +# endif +# define machine_is_mecha() (machine_arch_type == MACH_TYPE_MECHA) +#else +# define machine_is_mecha() (0) +#endif + +#ifdef CONFIG_MACH_BUBBA3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUBBA3 +# endif +# define machine_is_bubba3() (machine_arch_type == MACH_TYPE_BUBBA3) +#else +# define machine_is_bubba3() (0) +#endif + +#ifdef CONFIG_MACH_PUPITRE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PUPITRE +# endif +# define machine_is_pupitre() (machine_arch_type == MACH_TYPE_PUPITRE) +#else +# define machine_is_pupitre() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_HARMONY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_HARMONY +# endif +# define machine_is_tegra_harmony() (machine_arch_type == MACH_TYPE_TEGRA_HARMONY) +#else +# define machine_is_tegra_harmony() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_VOGUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_VOGUE +# endif +# define machine_is_tegra_vogue() (machine_arch_type == MACH_TYPE_TEGRA_VOGUE) +#else +# define machine_is_tegra_vogue() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_E1165 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_E1165 +# endif +# define machine_is_tegra_e1165() (machine_arch_type == MACH_TYPE_TEGRA_E1165) +#else +# define machine_is_tegra_e1165() (0) +#endif + +#ifdef CONFIG_MACH_SIMPLENET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMPLENET +# endif +# define machine_is_simplenet() (machine_arch_type == MACH_TYPE_SIMPLENET) +#else +# define machine_is_simplenet() (0) +#endif + +#ifdef CONFIG_MACH_EC4350TBM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EC4350TBM +# endif +# define machine_is_ec4350tbm() (machine_arch_type == MACH_TYPE_EC4350TBM) +#else +# define machine_is_ec4350tbm() (0) +#endif + +#ifdef CONFIG_MACH_PEC_TC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEC_TC +# endif +# define machine_is_pec_tc() (machine_arch_type == MACH_TYPE_PEC_TC) +#else +# define machine_is_pec_tc() (0) +#endif + +#ifdef CONFIG_MACH_PEC_HC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEC_HC2 +# endif +# define machine_is_pec_hc2() (machine_arch_type == MACH_TYPE_PEC_HC2) +#else +# define machine_is_pec_hc2() (0) +#endif + +#ifdef CONFIG_MACH_ESL_MOBILIS_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_MOBILIS_A +# endif +# define machine_is_esl_mobilis_a() (machine_arch_type == MACH_TYPE_ESL_MOBILIS_A) +#else +# define machine_is_esl_mobilis_a() (0) +#endif + +#ifdef CONFIG_MACH_ESL_MOBILIS_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_MOBILIS_B +# endif +# define machine_is_esl_mobilis_b() (machine_arch_type == MACH_TYPE_ESL_MOBILIS_B) +#else +# define machine_is_esl_mobilis_b() (0) +#endif + +#ifdef CONFIG_MACH_ESL_WAVE_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_WAVE_A +# endif +# define machine_is_esl_wave_a() (machine_arch_type == MACH_TYPE_ESL_WAVE_A) +#else +# define machine_is_esl_wave_a() (0) +#endif + +#ifdef CONFIG_MACH_ESL_WAVE_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_WAVE_B +# endif +# define machine_is_esl_wave_b() (machine_arch_type == MACH_TYPE_ESL_WAVE_B) +#else +# define machine_is_esl_wave_b() (0) +#endif + +#ifdef CONFIG_MACH_UNISENSE_MMM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNISENSE_MMM +# endif +# define machine_is_unisense_mmm() (machine_arch_type == MACH_TYPE_UNISENSE_MMM) +#else +# define machine_is_unisense_mmm() (0) +#endif + +#ifdef CONFIG_MACH_BLUESHARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUESHARK +# endif +# define machine_is_blueshark() (machine_arch_type == MACH_TYPE_BLUESHARK) +#else +# define machine_is_blueshark() (0) +#endif + +#ifdef CONFIG_MACH_E10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E10 +# endif +# define machine_is_e10() (machine_arch_type == MACH_TYPE_E10) +#else +# define machine_is_e10() (0) +#endif + +#ifdef CONFIG_MACH_APP3K_ROBIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APP3K_ROBIN +# endif +# define machine_is_app3k_robin() (machine_arch_type == MACH_TYPE_APP3K_ROBIN) +#else +# define machine_is_app3k_robin() (0) +#endif + +#ifdef CONFIG_MACH_POV15HD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POV15HD +# endif +# define machine_is_pov15hd() (machine_arch_type == MACH_TYPE_POV15HD) +#else +# define machine_is_pov15hd() (0) +#endif + +#ifdef CONFIG_MACH_STELLA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STELLA +# endif +# define machine_is_stella() (machine_arch_type == MACH_TYPE_STELLA) +#else +# define machine_is_stella() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_LSCHL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_LSCHL +# endif +# define machine_is_linkstation_lschl() (machine_arch_type == MACH_TYPE_LINKSTATION_LSCHL) +#else +# define machine_is_linkstation_lschl() (0) +#endif + +#ifdef CONFIG_MACH_NETWALKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETWALKER +# endif +# define machine_is_netwalker() (machine_arch_type == MACH_TYPE_NETWALKER) +#else +# define machine_is_netwalker() (0) +#endif + +#ifdef CONFIG_MACH_ACSX106 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACSX106 +# endif +# define machine_is_acsx106() (machine_arch_type == MACH_TYPE_ACSX106) +#else +# define machine_is_acsx106() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS5_C1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS5_C1 +# endif +# define machine_is_atlas5_c1() (machine_arch_type == MACH_TYPE_ATLAS5_C1) +#else +# define machine_is_atlas5_c1() (0) +#endif + +#ifdef CONFIG_MACH_NSB3AST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB3AST +# endif +# define machine_is_nsb3ast() (machine_arch_type == MACH_TYPE_NSB3AST) +#else +# define machine_is_nsb3ast() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SLC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SLC +# endif +# define machine_is_gnet_slc() (machine_arch_type == MACH_TYPE_GNET_SLC) +#else +# define machine_is_gnet_slc() (0) +#endif + +#ifdef CONFIG_MACH_AF4000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AF4000 +# endif +# define machine_is_af4000() (machine_arch_type == MACH_TYPE_AF4000) +#else +# define machine_is_af4000() (0) +#endif + +#ifdef CONFIG_MACH_ARK9431 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARK9431 +# endif +# define machine_is_ark9431() (machine_arch_type == MACH_TYPE_ARK9431) +#else +# define machine_is_ark9431() (0) +#endif + +#ifdef CONFIG_MACH_FS_S5PC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FS_S5PC100 +# endif +# define machine_is_fs_s5pc100() (machine_arch_type == MACH_TYPE_FS_S5PC100) +#else +# define machine_is_fs_s5pc100() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3505NOVA8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3505NOVA8 +# endif +# define machine_is_omap3505nova8() (machine_arch_type == MACH_TYPE_OMAP3505NOVA8) +#else +# define machine_is_omap3505nova8() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3621_EDP1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3621_EDP1 +# endif +# define machine_is_omap3621_edp1() (machine_arch_type == MACH_TYPE_OMAP3621_EDP1) +#else +# define machine_is_omap3621_edp1() (0) +#endif + +#ifdef CONFIG_MACH_ORATISAES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISAES +# endif +# define machine_is_oratisaes() (machine_arch_type == MACH_TYPE_ORATISAES) +#else +# define machine_is_oratisaes() (0) +#endif + +#ifdef CONFIG_MACH_SMDKV310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKV310 +# endif +# define machine_is_smdkv310() (machine_arch_type == MACH_TYPE_SMDKV310) +#else +# define machine_is_smdkv310() (0) +#endif + +#ifdef CONFIG_MACH_SIEMENS_L0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIEMENS_L0 +# endif +# define machine_is_siemens_l0() (machine_arch_type == MACH_TYPE_SIEMENS_L0) +#else +# define machine_is_siemens_l0() (0) +#endif + +#ifdef CONFIG_MACH_VENTANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VENTANA +# endif +# define machine_is_ventana() (machine_arch_type == MACH_TYPE_VENTANA) +#else +# define machine_is_ventana() (0) +#endif + +#ifdef CONFIG_MACH_WM8505_7IN_NETBOOK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WM8505_7IN_NETBOOK +# endif +# define machine_is_wm8505_7in_netbook() (machine_arch_type == MACH_TYPE_WM8505_7IN_NETBOOK) +#else +# define machine_is_wm8505_7in_netbook() (0) +#endif + +#ifdef CONFIG_MACH_EC4350SDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EC4350SDB +# endif +# define machine_is_ec4350sdb() (machine_arch_type == MACH_TYPE_EC4350SDB) +#else +# define machine_is_ec4350sdb() (0) +#endif + +#ifdef CONFIG_MACH_MIMAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIMAS +# endif +# define machine_is_mimas() (machine_arch_type == MACH_TYPE_MIMAS) +#else +# define machine_is_mimas() (0) +#endif + +#ifdef CONFIG_MACH_TITAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TITAN +# endif +# define machine_is_titan() (machine_arch_type == MACH_TYPE_TITAN) +#else +# define machine_is_titan() (0) +#endif + +#ifdef CONFIG_MACH_CRANEBOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CRANEBOARD +# endif +# define machine_is_craneboard() (machine_arch_type == MACH_TYPE_CRANEBOARD) +#else +# define machine_is_craneboard() (0) +#endif + +#ifdef CONFIG_MACH_ES2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ES2440 +# endif +# define machine_is_es2440() (machine_arch_type == MACH_TYPE_ES2440) +#else +# define machine_is_es2440() (0) +#endif + +#ifdef CONFIG_MACH_NAJAY_A9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAJAY_A9263 +# endif +# define machine_is_najay_a9263() (machine_arch_type == MACH_TYPE_NAJAY_A9263) +#else +# define machine_is_najay_a9263() (0) +#endif + +#ifdef CONFIG_MACH_HTCTORNADO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCTORNADO +# endif +# define machine_is_htctornado() (machine_arch_type == MACH_TYPE_HTCTORNADO) +#else +# define machine_is_htctornado() (0) +#endif + +#ifdef CONFIG_MACH_DIMM_MX257 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DIMM_MX257 +# endif +# define machine_is_dimm_mx257() (machine_arch_type == MACH_TYPE_DIMM_MX257) +#else +# define machine_is_dimm_mx257() (0) +#endif + +#ifdef CONFIG_MACH_JIGEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JIGEN +# endif +# define machine_is_jigen301() (machine_arch_type == MACH_TYPE_JIGEN) +#else +# define machine_is_jigen301() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6450 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6450 +# endif +# define machine_is_smdk6450() (machine_arch_type == MACH_TYPE_SMDK6450) +#else +# define machine_is_smdk6450() (0) +#endif + +#ifdef CONFIG_MACH_MENO_QNG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MENO_QNG +# endif +# define machine_is_meno_qng() (machine_arch_type == MACH_TYPE_MENO_QNG) +#else +# define machine_is_meno_qng() (0) +#endif + +#ifdef CONFIG_MACH_NS2416 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NS2416 +# endif +# define machine_is_ns2416() (machine_arch_type == MACH_TYPE_NS2416) +#else +# define machine_is_ns2416() (0) +#endif + +#ifdef CONFIG_MACH_RPC353 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RPC353 +# endif +# define machine_is_rpc353() (machine_arch_type == MACH_TYPE_RPC353) +#else +# define machine_is_rpc353() (0) +#endif + +#ifdef CONFIG_MACH_TQ6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TQ6410 +# endif +# define machine_is_tq6410() (machine_arch_type == MACH_TYPE_TQ6410) +#else +# define machine_is_tq6410() (0) +#endif + +#ifdef CONFIG_MACH_SKY6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKY6410 +# endif +# define machine_is_sky6410() (machine_arch_type == MACH_TYPE_SKY6410) +#else +# define machine_is_sky6410() (0) +#endif + +#ifdef CONFIG_MACH_DYNASTY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DYNASTY +# endif +# define machine_is_dynasty() (machine_arch_type == MACH_TYPE_DYNASTY) +#else +# define machine_is_dynasty() (0) +#endif + +#ifdef CONFIG_MACH_VIVO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VIVO +# endif +# define machine_is_vivo() (machine_arch_type == MACH_TYPE_VIVO) +#else +# define machine_is_vivo() (0) +#endif + +#ifdef CONFIG_MACH_BURY_BL7582 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BURY_BL7582 +# endif +# define machine_is_bury_bl7582() (machine_arch_type == MACH_TYPE_BURY_BL7582) +#else +# define machine_is_bury_bl7582() (0) +#endif + +#ifdef CONFIG_MACH_BURY_BPS5270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BURY_BPS5270 +# endif +# define machine_is_bury_bps5270() (machine_arch_type == MACH_TYPE_BURY_BPS5270) +#else +# define machine_is_bury_bps5270() (0) +#endif + +#ifdef CONFIG_MACH_BASI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BASI +# endif +# define machine_is_basi() (machine_arch_type == MACH_TYPE_BASI) +#else +# define machine_is_basi() (0) +#endif + +#ifdef CONFIG_MACH_TN200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TN200 +# endif +# define machine_is_tn200() (machine_arch_type == MACH_TYPE_TN200) +#else +# define machine_is_tn200() (0) +#endif + +#ifdef CONFIG_MACH_C2MMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C2MMI +# endif +# define machine_is_c2mmi() (machine_arch_type == MACH_TYPE_C2MMI) +#else +# define machine_is_c2mmi() (0) +#endif + +#ifdef CONFIG_MACH_MESON_6236M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESON_6236M +# endif +# define machine_is_meson_6236m() (machine_arch_type == MACH_TYPE_MESON_6236M) +#else +# define machine_is_meson_6236m() (0) +#endif + +#ifdef CONFIG_MACH_MESON_8626M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESON_8626M +# endif +# define machine_is_meson_8626m() (machine_arch_type == MACH_TYPE_MESON_8626M) +#else +# define machine_is_meson_8626m() (0) +#endif + +#ifdef CONFIG_MACH_TUBE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TUBE +# endif +# define machine_is_tube() (machine_arch_type == MACH_TYPE_TUBE) +#else +# define machine_is_tube() (0) +#endif + +#ifdef CONFIG_MACH_MESSINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESSINA +# endif +# define machine_is_messina() (machine_arch_type == MACH_TYPE_MESSINA) +#else +# define machine_is_messina() (0) +#endif + +#ifdef CONFIG_MACH_MX50_ARM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX50_ARM2 +# endif +# define machine_is_mx50_arm2() (machine_arch_type == MACH_TYPE_MX50_ARM2) +#else +# define machine_is_mx50_arm2() (0) +#endif + +#ifdef CONFIG_MACH_CETUS9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CETUS9263 +# endif +# define machine_is_cetus9263() (machine_arch_type == MACH_TYPE_CETUS9263) +#else +# define machine_is_cetus9263() (0) +#endif + +#ifdef CONFIG_MACH_BROWNSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BROWNSTONE +# endif +# define machine_is_brownstone() (machine_arch_type == MACH_TYPE_BROWNSTONE) +#else +# define machine_is_brownstone() (0) +#endif + +#ifdef CONFIG_MACH_VMX25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMX25 +# endif +# define machine_is_vmx25() (machine_arch_type == MACH_TYPE_VMX25) +#else +# define machine_is_vmx25() (0) +#endif + +#ifdef CONFIG_MACH_VMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMX51 +# endif +# define machine_is_vmx51() (machine_arch_type == MACH_TYPE_VMX51) +#else +# define machine_is_vmx51() (0) +#endif + +#ifdef CONFIG_MACH_ABACUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ABACUS +# endif +# define machine_is_abacus() (machine_arch_type == MACH_TYPE_ABACUS) +#else +# define machine_is_abacus() (0) +#endif + +#ifdef CONFIG_MACH_CM4745 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM4745 +# endif +# define machine_is_cm4745() (machine_arch_type == MACH_TYPE_CM4745) +#else +# define machine_is_cm4745() (0) +#endif + +#ifdef CONFIG_MACH_ORATISLINK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISLINK +# endif +# define machine_is_oratislink() (machine_arch_type == MACH_TYPE_ORATISLINK) +#else +# define machine_is_oratislink() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM365_DVR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM365_DVR +# endif +# define machine_is_davinci_dm365_dvr() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_DVR) +#else +# define machine_is_davinci_dm365_dvr() (0) +#endif + +#ifdef CONFIG_MACH_NETVIZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETVIZ +# endif +# define machine_is_netviz() (machine_arch_type == MACH_TYPE_NETVIZ) +#else +# define machine_is_netviz() (0) +#endif + +#ifdef CONFIG_MACH_FLEXIBITY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLEXIBITY +# endif +# define machine_is_flexibity() (machine_arch_type == MACH_TYPE_FLEXIBITY) +#else +# define machine_is_flexibity() (0) +#endif + +#ifdef CONFIG_MACH_WLAN_COMPUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WLAN_COMPUTER +# endif +# define machine_is_wlan_computer() (machine_arch_type == MACH_TYPE_WLAN_COMPUTER) +#else +# define machine_is_wlan_computer() (0) +#endif + /* * These have not yet been registered */ diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index f5660a985b..54519b0e1d 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -125,7 +125,7 @@ void blue_LED_off(void) __attribute__((weak, alias("__blue_LED_off"))); static int init_baudrate (void) { char tmp[64]; /* long enough for environment variables */ - int i = getenv_r ("baudrate", tmp, sizeof (tmp)); + int i = getenv_f("baudrate", tmp, sizeof (tmp)); gd->bd->bi_baudrate = gd->baudrate = (i > 0) ? (int) simple_strtoul (tmp, NULL, 10) : CONFIG_BAUDRATE; diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 254aecff51..9e741d22e2 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -102,7 +102,7 @@ static int init_baudrate(void) char tmp[64]; int i; - i = getenv_r("baudrate", tmp, sizeof(tmp)); + i = getenv_f("baudrate", tmp, sizeof(tmp)); if (i > 0) { gd->baudrate = simple_strtoul(tmp, NULL, 10); } else { diff --git a/arch/blackfin/cpu/cmd_gpio.c b/arch/blackfin/cpu/cmd_gpio.c index 9e505b6617..4430c90d4d 100644 --- a/arch/blackfin/cpu/cmd_gpio.c +++ b/arch/blackfin/cpu/cmd_gpio.c @@ -26,11 +26,9 @@ int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } - if (argc != 3) { + if (argc != 3) show_usage: - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } + return cmd_usage(cmdtp); /* parse the behavior */ ulong sub_cmd; diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c index 1cd619f10b..e0f2975603 100644 --- a/arch/blackfin/cpu/jtag-console.c +++ b/arch/blackfin/cpu/jtag-console.c @@ -1,49 +1,116 @@ /* * jtag-console.c - console driver over Blackfin JTAG * - * Copyright (c) 2008 Analog Devices Inc. + * Copyright (c) 2008-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ #include <common.h> +#include <malloc.h> #include <stdio_dev.h> #include <asm/blackfin.h> +#ifdef DEBUG +# define dprintf(...) serial_printf(__VA_ARGS__) +#else +# define dprintf(...) do { if (0) printf(__VA_ARGS__); } while (0) +#endif + +static inline void dprintf_decode(const char *s, uint32_t len) +{ + uint32_t i; + for (i = 0; i < len; ++i) + if (s[i] < 0x20 || s[i] >= 0x7f) + dprintf("\\%o", s[i]); + else + dprintf("%c", s[i]); +} + +static inline uint32_t bfin_write_emudat(uint32_t emudat) +{ + __asm__ __volatile__("emudat = %0;" : : "d"(emudat)); + return emudat; +} + +static inline uint32_t bfin_read_emudat(void) +{ + uint32_t emudat; + __asm__ __volatile__("%0 = emudat;" : "=d"(emudat)); + return emudat; +} + #ifndef CONFIG_JTAG_CONSOLE_TIMEOUT # define CONFIG_JTAG_CONSOLE_TIMEOUT 500 #endif /* The Blackfin tends to be much much faster than the JTAG hardware. */ -static void jtag_write_emudat(uint32_t emudat) +static bool jtag_write_emudat(uint32_t emudat) { static bool overflowed = false; ulong timeout = get_timer(0) + CONFIG_JTAG_CONSOLE_TIMEOUT; while (bfin_read_DBGSTAT() & 0x1) { if (overflowed) - return; + return overflowed; if (timeout < get_timer(0)) overflowed = true; } overflowed = false; - __asm__ __volatile__("emudat = %0;" : : "d"(emudat)); + bfin_write_emudat(emudat); + return overflowed; } /* Transmit a buffer. The format is: * [32bit length][actual data] */ -static void jtag_send(const char *c, uint32_t len) +static void jtag_send(const char *raw_str, uint32_t len) { - uint32_t i; + const char *cooked_str; + uint32_t i, ex; if (len == 0) return; + /* Ugh, need to output \r after \n */ + ex = 0; + for (i = 0; i < len; ++i) + if (raw_str[i] == '\n') + ++ex; + if (ex) { + char *c = malloc(len + ex); + cooked_str = c; + for (i = 0; i < len; ++i) { + *c++ = raw_str[i]; + if (raw_str[i] == '\n') + *c++ = '\r'; + } + len += ex; + } else + cooked_str = raw_str; + + dprintf("%s(\"", __func__); + dprintf_decode(cooked_str, len); + dprintf("\", %i)\n", len); + /* First send the length */ - jtag_write_emudat(len); + if (jtag_write_emudat(len)) + goto done; /* Then send the data */ - for (i = 0; i < len; i += 4) - jtag_write_emudat((c[i] << 0) | (c[i+1] << 8) | (c[i+2] << 16) | (c[i+3] << 24)); + for (i = 0; i < len; i += 4) { + uint32_t emudat = + (cooked_str[i + 0] << 0) | + (cooked_str[i + 1] << 8) | + (cooked_str[i + 2] << 16) | + (cooked_str[i + 3] << 24); + if (jtag_write_emudat(emudat)) { + bfin_write_emudat(0); + goto done; + } + } + + done: + if (cooked_str != raw_str) + free((char *)cooked_str); } static void jtag_putc(const char c) { @@ -59,7 +126,10 @@ static size_t inbound_len, leftovers_len; /* Lower layers want to know when jtag has data */ static int jtag_tstc_dbg(void) { - return (bfin_read_DBGSTAT() & 0x2); + int ret = (bfin_read_DBGSTAT() & 0x2); + if (ret) + dprintf("%s: ret:%i\n", __func__, ret); + return ret; } /* Higher layers want to know when any data is available */ @@ -77,6 +147,9 @@ static int jtag_getc(void) int ret; uint32_t emudat; + dprintf("%s: inlen:%zu leftlen:%zu left:%x\n", __func__, + inbound_len, leftovers_len, leftovers); + /* see if any data is left over */ if (leftovers_len) { --leftovers_len; @@ -88,7 +161,7 @@ static int jtag_getc(void) /* wait for new data ! */ while (!jtag_tstc_dbg()) continue; - __asm__("%0 = emudat;" : "=d"(emudat)); + emudat = bfin_read_emudat(); if (inbound_len == 0) { /* grab the length */ diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 4e9bb19226..46e36c8904 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -53,9 +53,10 @@ static inline void serial_early_puts(const char *s) static int display_banner(void) { printf("\n\n%s\n\n", version_string); - printf("CPU: ADSP " MK_STR(CONFIG_BFIN_CPU) " " + printf("CPU: ADSP %s " "(Detected Rev: 0.%d) " "(%s boot)\n", + gd->bd->bi_cpu, bfin_revid(), get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE)); return 0; @@ -64,7 +65,7 @@ static int display_banner(void) static int init_baudrate(void) { char baudrate[15]; - int i = getenv_r("baudrate", baudrate, sizeof(baudrate)); + int i = getenv_f("baudrate", baudrate, sizeof(baudrate)); gd->bd->bi_baudrate = gd->baudrate = (i > 0) ? simple_strtoul(baudrate, NULL, 10) : CONFIG_BAUDRATE; diff --git a/arch/blackfin/lib/boot.c b/arch/blackfin/lib/boot.c index 37aa82a055..768a8826b5 100644 --- a/arch/blackfin/lib/boot.c +++ b/arch/blackfin/lib/boot.c @@ -18,6 +18,10 @@ extern void swap_to(int device_id); #endif +#ifdef CONFIG_VIDEO +extern void video_stop(void); +#endif + static char *make_command_line(void) { char *dest = (char *)CONFIG_LINUX_CMDLINE_ADDR; @@ -45,6 +49,11 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima swap_to(FLASH); #endif +#ifdef CONFIG_VIDEO + /* maybe this should be standardized and moved to bootm ... */ + video_stop(); +#endif + appl = (int (*)(char *))images->ep; printf("Starting Kernel at = %p\n", appl); diff --git a/arch/blackfin/lib/post.c b/arch/blackfin/lib/post.c index faf6b96ba2..bd6aaf5d4d 100644 --- a/arch/blackfin/lib/post.c +++ b/arch/blackfin/lib/post.c @@ -168,7 +168,7 @@ static void post_get_flags(int *test_flags) } for (i = 0; i < varnum; i++) { - if (getenv_r(var[i], list, sizeof(list)) <= 0) + if (getenv_f(var[i], list, sizeof(list)) <= 0) continue; for (j = 0; j < post_list_size; j++) { diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 0adc66455a..684cdb84a3 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -69,7 +69,7 @@ const char version_string[] = static int init_baudrate (void) { char tmp[64]; /* long enough for environment variables */ - int i = getenv_r("baudrate", tmp, 64); + int i = getenv_f("baudrate", tmp, 64); gd->baudrate = (i != 0) ? (int) simple_strtoul (tmp, NULL, 10) diff --git a/arch/m68k/include/asm/fec.h b/arch/m68k/include/asm/fec.h index 49311e596f..cecec59ff6 100644 --- a/arch/m68k/include/asm/fec.h +++ b/arch/m68k/include/asm/fec.h @@ -357,9 +357,9 @@ int fecpin_setclear(struct eth_device *dev, int setclear); void __mii_init(void); uint mii_send(uint mii_cmd); int mii_discover_phy(struct eth_device *dev); -int mcffec_miiphy_read(char *devname, unsigned char addr, +int mcffec_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value); -int mcffec_miiphy_write(char *devname, unsigned char addr, +int mcffec_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value); #endif diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index 732023d67c..b254079ae7 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -134,7 +134,7 @@ typedef int (init_fnc_t) (void); static int init_baudrate (void) { char tmp[64]; /* long enough for environment variables */ - int i = getenv_r ("baudrate", tmp, sizeof (tmp)); + int i = getenv_f("baudrate", tmp, sizeof (tmp)); gd->baudrate = (i > 0) ? (int) simple_strtoul (tmp, NULL, 10) @@ -278,7 +278,7 @@ board_init_f (ulong bootflag) /* * reserve protected RAM */ - i = getenv_r ("pram", tmp, sizeof (tmp)); + i = getenv_f("pram", tmp, sizeof (tmp)); reg = (i > 0) ? simple_strtoul (tmp, NULL, 10) : CONFIG_PRAM; addr -= (reg << 10); /* size is in kB */ debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); @@ -549,7 +549,7 @@ void board_init_r (gd_t *id, ulong dest_addr) * Fill in missing fields of bd_info. * We do this here, where we have "normal" access to the * environment; we used to do this still running from ROM, - * where had to use getenv_r(), which can be pretty slow when + * where had to use getenv_f(), which can be pretty slow when * the environment is in EEPROM. */ bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); diff --git a/arch/mips/cpu/au1x00_eth.c b/arch/mips/cpu/au1x00_eth.c index 5074997a29..c51079961c 100644 --- a/arch/mips/cpu/au1x00_eth.c +++ b/arch/mips/cpu/au1x00_eth.c @@ -89,7 +89,7 @@ mac_fifo_t mac_fifo[NO_OF_FIFOS]; #define MAX_WAIT 1000 #if defined(CONFIG_CMD_MII) -int au1x00_miiphy_read(char *devname, unsigned char addr, +int au1x00_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short * value) { volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); @@ -122,7 +122,7 @@ int au1x00_miiphy_read(char *devname, unsigned char addr, return 0; } -int au1x00_miiphy_write(char *devname, unsigned char addr, +int au1x00_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) { volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); diff --git a/arch/mips/cpu/incaip_clock.c b/arch/mips/cpu/incaip_clock.c index fc2c62180b..b65dfe0e1a 100644 --- a/arch/mips/cpu/incaip_clock.c +++ b/arch/mips/cpu/incaip_clock.c @@ -105,7 +105,7 @@ int incaip_set_cpuclk (void) char tmp[64]; ulong cpuclk; - if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) { + if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) { cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; cgu_init (cpuclk); ebu_init (cpuclk); diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index b2d113e870..ab4a17c943 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -114,7 +114,7 @@ static void display_flash_config(ulong size) static int init_baudrate (void) { char tmp[64]; /* long enough for environment variables */ - int i = getenv_r ("baudrate", tmp, sizeof (tmp)); + int i = getenv_f("baudrate", tmp, sizeof (tmp)); gd->baudrate = (i > 0) ? (int) simple_strtoul (tmp, NULL, 10) diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 6379534a0b..d9c654477d 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -40,11 +40,10 @@ int checkcpu (void) return (0); } - -int do_reset (void) +int do_reset(void) { - void (*rst)(void) = (void(*)(void))CONFIG_SYS_RESET_ADDR; - disable_interrupts (); - rst(); - return(0); + disable_interrupts(); + /* indirect call to go beyond 256MB limitation of toolchain */ + nios2_callr(CONFIG_SYS_RESET_ADDR); + return 0; } diff --git a/arch/nios2/include/asm/system.h b/arch/nios2/include/asm/system.h index bb03ca5316..086d92bb0c 100644 --- a/arch/nios2/include/asm/system.h +++ b/arch/nios2/include/asm/system.h @@ -56,4 +56,9 @@ ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ }) +/* indirect call to go beyond 256MB limitation of toolchain */ +#define nios2_callr(addr) __asm__ __volatile__ ( \ + "callr %0" \ + : : "r" (addr)) + #endif /* __ASM_NIOS2_SYSTEM_H */ diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index e25a1137f1..40a4d15027 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -42,7 +42,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima if (boot_get_fdt(flag, argc, argv, images, &of_flat_tree, &of_size)) return 1; #endif - if (!of_flat_tree) + if (!of_flat_tree && argc > 3) of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16); if (of_flat_tree) initrd_end = (ulong)of_flat_tree; diff --git a/arch/powerpc/cpu/mpc8220/fec.c b/arch/powerpc/cpu/mpc8220/fec.c index 5df9735332..00879dff5c 100644 --- a/arch/powerpc/cpu/mpc8220/fec.c +++ b/arch/powerpc/cpu/mpc8220/fec.c @@ -34,8 +34,8 @@ typedef struct { u8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ } NBUF; -int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal); -int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data); +int fec8220_miiphy_read (const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal); +int fec8220_miiphy_write (const char *devname, u8 phyAddr, u8 regAddr, u16 data); /********************************************************************/ #ifdef DEBUG @@ -840,7 +840,7 @@ int mpc8220_fec_initialize (bd_t * bis) dev->send = mpc8220_fec_send; dev->recv = mpc8220_fec_recv; - sprintf (dev->name, "FEC ETHERNET"); + sprintf (dev->name, "FEC"); eth_register (dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) @@ -881,7 +881,7 @@ int mpc8220_fec_initialize (bd_t * bis) /* MII-interface related functions */ /********************************************************************/ -int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal) +int fec8220_miiphy_read (const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal) { ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1; u32 reg; /* convenient holder for the PHY register */ @@ -925,7 +925,7 @@ int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal) } /********************************************************************/ -int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data) +int fec8220_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data) { ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1; u32 reg; /* convenient holder for the PHY register */ diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index 5ac02a09c0..c82958db1b 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -383,7 +383,7 @@ int fec_initialize(bd_t *bis) dev = (struct eth_device*) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); - sprintf(dev->name, "FCC%d ETHERNET", + sprintf(dev->name, "FCC%d", ether_fcc_info[i].ether_index + 1); dev->priv = ðer_fcc_info[i]; dev->init = fec_init; diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c index 432111df4c..2870a9cf94 100644 --- a/arch/powerpc/cpu/mpc8260/ether_scc.c +++ b/arch/powerpc/cpu/mpc8260/ether_scc.c @@ -375,7 +375,7 @@ int mpc82xx_scc_enet_initialize(bd_t *bis) dev = (struct eth_device *) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); - sprintf(dev->name, "SCC ETHERNET"); + sprintf(dev->name, "SCC"); dev->init = sec_init; dev->halt = sec_halt; dev->send = sec_send; diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index fe851f15db..b7c0272105 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -64,12 +64,20 @@ COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_FSL_CORENET) += liodn.o COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_FSL_CORENET) += portals.o + +# various SoC specific assignments +COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o + COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o +COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o +COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS = $(COBJS-y) COBJS += cpu.o diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index d7835c8d69..d73f3d7f14 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -41,6 +41,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) + puts("Work-around for Erratum SERDES8 enabled\n"); +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) + puts("Work-around for Erratum CPU22 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f15d43c38c..3f80700711 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -74,7 +74,7 @@ int checkcpu (void) puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 5d5b4c2963..27236a0bad 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -32,6 +32,7 @@ #include <ioports.h> #include <sata.h> #include <asm/io.h> +#include <asm/cache.h> #include <asm/mmu.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> @@ -127,6 +128,44 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) } #endif +#ifdef CONFIG_SYS_FSL_CPC +static void enable_cpc(void) +{ + int i; + u32 size = 0; + + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + u32 cpccfg0 = in_be32(&cpc->cpccfg0); + size += CPC_CFG0_SZ_K(cpccfg0); + + out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); + /* Read back to sync write */ + in_be32(&cpc->cpccsr0); + + } + + printf("Corenet Platform Cache: %d KB enabled\n", size); +} + +void invalidate_cpc(void) +{ + int i; + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + /* Flash invalidate the CPC and clear all the locks */ + out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); + while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) + ; + } +} +#else +#define enable_cpc() +#define invalidate_cpc() +#endif /* CONFIG_SYS_FSL_CPC */ + /* * Breathe some life into the CPU... * @@ -140,7 +179,7 @@ static void corenet_tb_init(void) volatile ccsr_rcpm_t *rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); volatile ccsr_pic_t *pic = - (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); u32 whoami = in_be32(&pic->whoami); /* Enable the timebase register for this core */ @@ -188,6 +227,9 @@ void cpu_init_f (void) corenet_tb_init(); #endif init_used_tlb_cams(); + + /* Invalidate the CPC before DDR gets enabled */ + invalidate_cpc(); } @@ -198,13 +240,18 @@ void cpu_init_f (void) * use the same bit-encoding as the older 8555, etc, parts. * */ - int cpu_init_r(void) { #ifdef CONFIG_SYS_LBC_LCRR volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; #endif +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); + sync(); +#endif + puts ("L2: "); #if defined(CONFIG_L2_CACHE) @@ -319,6 +366,9 @@ int cpu_init_r(void) #else puts("disabled\n"); #endif + + enable_cpc(); + #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ qe_init(qe_base); diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 0691ca455a..e46dcb7047 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -33,6 +33,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, return; } + out_be32(&ddr->eor, regs->ddr_eor); + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i == 0) { out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c index 5f1414d758..f69b2e649f 100644 --- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c +++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c @@ -446,7 +446,7 @@ int fec_initialize(bd_t *bis) dev = (struct eth_device*) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); - sprintf(dev->name, "FCC%d ETHERNET", + sprintf(dev->name, "FCC%d", ether_fcc_info[i].ether_index + 1); dev->priv = ðer_fcc_info[i]; dev->init = fec_init; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 932466e883..45403641cf 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -28,6 +28,8 @@ #include <fdt_support.h> #include <asm/processor.h> #include <linux/ctype.h> +#include <asm/io.h> +#include <asm/fsl_portals.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif @@ -52,18 +54,19 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) { + u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; + val = cpu_to_fdt32(val); if (*reg == id) { - fdt_setprop_string(blob, off, "status", "okay"); + fdt_setprop_string(blob, off, "status", + "okay"); } else { - u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; - val = cpu_to_fdt32(val); fdt_setprop_string(blob, off, "status", "disabled"); - fdt_setprop_string(blob, off, "enable-method", - "spin-table"); - fdt_setprop(blob, off, "cpu-release-addr", - &val, sizeof(val)); } + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); } else { printf ("cpu NULL\n"); } @@ -80,7 +83,30 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif +#ifdef CONFIG_SYS_FSL_CPC +static inline void ft_fixup_l3cache(void *blob, int off) +{ + u32 line_size, num_ways, size, num_sets; + cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; + u32 cfg0 = in_be32(&cpc->cpccfg0); + + size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; + num_ways = CPC_CFG0_NUM_WAYS(cfg0); + line_size = CPC_CFG0_LINE_SZ(cfg0); + num_sets = size / (line_size * num_ways); + + fdt_setprop(blob, off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, off, "cache-block-size", line_size); + fdt_setprop_cell(blob, off, "cache-size", size); + fdt_setprop_cell(blob, off, "cache-sets", num_sets); + fdt_setprop_cell(blob, off, "cache-level", 3); +#ifdef CONFIG_SYS_CACHE_STASHING + fdt_setprop_cell(blob, off, "cache-stash-id", 1); +#endif +} +#else #define ft_fixup_l3cache(x, y) +#endif #if defined(CONFIG_L2_CACHE) /* return size in kilobytes */ @@ -422,4 +448,18 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif ft_fixup_dpaa_clks(blob); + +#if defined(CONFIG_SYS_BMAN_MEM_PHYS) + fdt_portal(blob, "fsl,bman-portal", "bman-portals", + (u64)CONFIG_SYS_BMAN_MEM_PHYS, + CONFIG_SYS_BMAN_MEM_SIZE); +#endif + +#if defined(CONFIG_SYS_QMAN_MEM_PHYS) + fdt_portal(blob, "fsl,qman-portal", "qman-portals", + (u64)CONFIG_SYS_QMAN_MEM_PHYS, + CONFIG_SYS_QMAN_MEM_SIZE); + + fdt_fixup_qportals(blob); +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c new file mode 100644 index 0000000000..5bcf91abf2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -0,0 +1,495 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 +#include <hwconfig.h> +#endif +#include <asm/fsl_serdes.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/fsl_law.h> +#include "fsl_corenet_serdes.h" + +static u32 serdes_prtcl_map; + +#ifdef DEBUG +static const char *serdes_prtcl_str[] = { + [NONE] = "NA", + [PCIE1] = "PCIE1", + [PCIE2] = "PCIE2", + [PCIE3] = "PCIE3", + [PCIE4] = "PCIE4", + [SATA1] = "SATA1", + [SATA2] = "SATA2", + [SRIO1] = "SRIO1", + [SRIO2] = "SRIO2", + [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", + [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", + [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", + [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", + [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", + [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", + [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", + [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", + [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", + [XAUI_FM1] = "XAUI_FM1", + [XAUI_FM2] = "XAUI_FM2", + [AURORA] = "DEBUG", +}; +#endif + +static const struct { + int idx; + unsigned int lpd; /* RCW lane powerdown bit */ + int bank; +} lanes[SRDS_MAX_LANES] = { + { 0, 152, FSL_SRDS_BANK_1 }, + { 1, 153, FSL_SRDS_BANK_1 }, + { 2, 154, FSL_SRDS_BANK_1 }, + { 3, 155, FSL_SRDS_BANK_1 }, + { 4, 156, FSL_SRDS_BANK_1 }, + { 5, 157, FSL_SRDS_BANK_1 }, + { 6, 158, FSL_SRDS_BANK_1 }, + { 7, 159, FSL_SRDS_BANK_1 }, + { 8, 160, FSL_SRDS_BANK_1 }, + { 9, 161, FSL_SRDS_BANK_1 }, + { 16, 162, FSL_SRDS_BANK_2 }, + { 17, 163, FSL_SRDS_BANK_2 }, + { 18, 164, FSL_SRDS_BANK_2 }, + { 19, 165, FSL_SRDS_BANK_2 }, + { 20, 170, FSL_SRDS_BANK_3 }, + { 21, 171, FSL_SRDS_BANK_3 }, + { 22, 172, FSL_SRDS_BANK_3 }, + { 23, 173, FSL_SRDS_BANK_3 }, +}; + +int serdes_get_lane_idx(int lane) +{ + return lanes[lane].idx; +} + +int serdes_get_bank(int lane) +{ + return lanes[lane].bank; +} + +int serdes_lane_enabled(int lane) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + + int bank = lanes[lane].bank; + int word = lanes[lane].lpd / 32; + int bit = lanes[lane].lpd % 32; + + if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) + return 0; + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + if (!IS_SVR_REV(get_svr(), 1, 0)) + if (bank > 0) + return !(srds_lpd_b[bank] & + (8 >> (lane - (6 + 4 * bank)))); +#endif + + return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); +} + +int is_serdes_configured(enum srds_prtcl device) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* Is serdes enabled at all? */ + if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) + return 0; + + return (1 << device) & serdes_prtcl_map; +} + +#ifndef CONFIG_SYS_DCSRBAR_PHYS +#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ +#define CONFIG_SYS_DCSRBAR 0x80000000 +#define __DCSR_NOT_DEFINED_BY_CONFIG +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 +static void enable_bank(ccsr_gur_t *gur, int bank) +{ + u32 rcw5; + + /* + * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in + * CCSR, and read/write in DSCR. + */ + rcw5 = in_be32(gur->rcwsr + 5); + if (bank == FSL_SRDS_BANK_2) { + rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2; + rcw5 |= srds_lpd_b[bank] << 26; + } else if (bank == FSL_SRDS_BANK_3) { + rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3; + rcw5 |= srds_lpd_b[bank] << 18; + } else { + printf("SERDES: enable_bank: bad bank %d\n", bank + 1); + return; + } + + /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation + * of the DCSR mapping. + */ + { +#ifdef __DCSR_NOT_DEFINED_BY_CONFIG + struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); + int law_index; + if (law.index == -1) + law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_DCSR); + else + set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, + LAW_TRGT_IF_DCSR); +#endif + u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; + out_be32(p, rcw5); +#ifdef __DCSR_NOT_DEFINED_BY_CONFIG + if (law.index == -1) + disable_law(law_index); + else + set_law(law.index, law.addr, law.size, law.trgt_id); +#endif + } +} + +/* + * To avoid problems with clock jitter, rev 2 p4080 uses the pll from + * bank 3 to clock banks 2 and 3, as well as a limited selection of + * protocol configurations. This requires that banks 2 and 3's lanes be + * disabled in the RCW, and enabled with some fixup here to re-enable + * them, and to configure bank 2's clock parameters in bank 3's pll in + * cases where they differ. + */ +static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, + u32 devdisr, u32 devdisr2, int cfg) +{ + int srds_ratio_b2; + int rfck_sel; + + /* + * The disabled lanes of bank 2 will cause the associated + * logic blocks to be disabled in DEVDISR. We reverse that here. + * + * Note that normally it is not permitted to clear DEVDISR bits + * once the device has been disabled, but the hardware people + * say that this special case is OK. + */ + clrbits_be32(&gur->devdisr, devdisr); + clrbits_be32(&gur->devdisr2, devdisr2); + + /* + * Some protocols require special handling. There are a few + * additional protocol configurations that can be used, which are + * not listed here. See app note 4065 for supported protocol + * configurations. + */ + switch (cfg) { + case 0x19: + /* + * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL. + * SGMII on bank 3 should still be usable. + */ + setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + + enable_bank(gur, FSL_SRDS_BANK_3); + break; + + case 0x0f: + case 0x10: + /* + * Banks 2 (XAUI) and 3 (SGMII) have different clocking + * requirements in these configurations. Bank 3 cannot + * be used and should have its lanes (but not the bank + * itself) disabled in the RCW. We set up bank 3's pll + * for bank 2's needs here. + */ + srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7; + + /* Determine refclock from XAUI ratio */ + switch (srds_ratio_b2) { + case 1: /* 20:1 */ + rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + case 2: /* 25:1 */ + rfck_sel = SRDS_PLLCR0_RFCK_SEL_125; + break; + default: + printf("SERDES: bad SRDS_RATIO_B2 %d\n", + srds_ratio_b2); + return; + } + + clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, + SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel); + + clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, + SRDS_PLLCR0_FRATE_SEL_MASK, + SRDS_PLLCR0_FRATE_SEL_6_25); + break; + default: + enable_bank(gur, FSL_SRDS_BANK_3); + } + +} +#endif + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int cfg; + serdes_corenet_t *srds_regs; + int lane, bank, idx; + enum srds_prtcl lane_prtcl; + long long end_tick; + int have_bank[SRDS_MAX_BANK] = {}; +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + u32 serdes8_devdisr = 0; + u32 serdes8_devdisr2 = 0; + char srds_lpd_opt[16]; + const char *srds_lpd_arg; + size_t arglen; +#endif + + /* Is serdes enabled at all? */ + if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) + return; + + srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); + cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + debug("Using SERDES configuration 0x%x, lane settings:\n", cfg); + + if (!is_serdes_prtcl_valid(cfg)) { + printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg); + return; + } + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + if (!IS_SVR_REV(get_svr(), 1, 0)) + for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { + sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); + srds_lpd_arg = hwconfig_subarg("serdes", srds_lpd_opt, + &arglen); + if (srds_lpd_arg) + srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg, + NULL, 0); + } +#endif + + /* Look for banks with all lanes disabled, and power down the bank. */ + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); + if (serdes_lane_enabled(lane)) { + have_bank[serdes_get_bank(lane)] = 1; + serdes_prtcl_map |= (1 << lane_prtcl); + } + } + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + if (IS_SVR_REV(get_svr(), 1, 0)) { + /* At least one bank must be disabled due to SERDES8. If + * no bank is found to be disabled based on lane + * disables, disable bank 3 because we can't turn off its + * lanes in the RCW without disabling MDIO due to erratum + * GEN8. + * + * This means that if you are relying on bank 3 being + * disabled to avoid SERDES8, in some cases you cannot + * also disable all lanes of another bank, or else bank + * 3 won't be disabled, leaving you with a configuration + * that isn't valid according to SERDES8 (e.g. if banks + * 2 and 3 have the same clock, and bank 1 is disabled + * instead of 3). + */ + for (bank = 0; bank < SRDS_MAX_BANK; bank++) { + if (!have_bank[bank]) + break; + } + + if (bank == SRDS_MAX_BANK) + have_bank[FSL_SRDS_BANK_3] = 0; + } else { + if (have_bank[FSL_SRDS_BANK_2]) + have_bank[FSL_SRDS_BANK_3] = 1; + } +#endif + + for (bank = 0; bank < SRDS_MAX_BANK; bank++) { + if (!have_bank[bank]) { + printf("SERDES: bank %d disabled\n", bank + 1); + setbits_be32(&srds_regs->bank[bank].rstctl, + SRDS_RSTCTL_SDPD); + } + } + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + idx = serdes_get_lane_idx(lane); + lane_prtcl = serdes_get_prtcl(cfg, lane); + +#ifdef DEBUG + switch (lane) { + case 0: + puts("Bank1: "); + break; + case 10: + puts("\nBank2: "); + break; + case 14: + puts("\nBank3: "); + break; + default: + break; + } + + printf("%s ", serdes_prtcl_str[lane_prtcl]); +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + switch (lane_prtcl) { + case PCIE1: + case PCIE2: + case PCIE3: + serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >> + (lane_prtcl - PCIE1); + break; + case SRIO1: + case SRIO2: + serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >> + (lane_prtcl - SRIO1); + break; + case SGMII_FM1_DTSEC1: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_DTSEC1_1; + break; + case SGMII_FM1_DTSEC2: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_DTSEC1_2; + break; + case SGMII_FM1_DTSEC3: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_DTSEC1_3; + break; + case SGMII_FM1_DTSEC4: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_DTSEC1_4; + break; + case SGMII_FM2_DTSEC1: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_1; + break; + case SGMII_FM2_DTSEC2: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_2; + break; + case SGMII_FM2_DTSEC3: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_3; + break; + case SGMII_FM2_DTSEC4: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_4; + break; + case XAUI_FM1: + case XAUI_FM2: + if (lane_prtcl == XAUI_FM1) + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_10GEC1; + else + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_10GEC2; + break; + case AURORA: + break; + default: + break; + } + +#endif + } + +#ifdef DEBUG + puts("\n"); +#endif + + for (idx = 0; idx < SRDS_MAX_BANK; idx++) { + u32 rstctl; + + bank = idx; + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + if (!IS_SVR_REV(get_svr(), 1, 0)) { + /* + * Change bank init order to 0, 2, 1, so that the + * third bank's PLL is established before we + * start the second bank which shares the third + * bank's PLL. + */ + + if (idx == 1) + bank = FSL_SRDS_BANK_3; + else if (idx == 2) + bank = FSL_SRDS_BANK_2; + } +#endif + + /* Skip disabled banks */ + if (!have_bank[bank]) + continue; + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + if (!IS_SVR_REV(get_svr(), 1, 0)) { + if (idx == 1) { + p4080_erratum_serdes8(srds_regs, gur, + serdes8_devdisr, + serdes8_devdisr2, cfg); + } else if (idx == 2) { + enable_bank(gur, FSL_SRDS_BANK_2); + } + } +#endif + + /* reset banks for errata */ + setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST); + + /* wait for reset complete or 1-second timeout */ + end_tick = usec2ticks(1000000) + get_ticks(); + do { + rstctl = in_be32(&srds_regs->bank[bank].rstctl); + if (rstctl & SRDS_RSTCTL_RSTDONE) + break; + } while (end_tick > get_ticks()); + + if (!(rstctl & SRDS_RSTCTL_RSTDONE)) { + printf("SERDES: timeout resetting bank %d\n", + bank + 1); + continue; + } + } +} diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h new file mode 100644 index 0000000000..42d771e096 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h @@ -0,0 +1,44 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Author: Roy Zang <tie-fei.zang@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_CORENET_SERDES_H +#define __FSL_CORENET_SERDES_H + +#define SRDS_MAX_LANES 18 +#define SRDS_MAX_BANK 3 + +enum srds_bank { + FSL_SRDS_BANK_1 = 0, + FSL_SRDS_BANK_2 = 1, + FSL_SRDS_BANK_3 = 2, +}; + +int is_serdes_prtcl_valid(u32 prtcl); +int serdes_get_lane_idx(int lane); +int serdes_get_bank(int lane); +int serdes_lane_enabled(int lane); +enum srds_prtcl serdes_get_prtcl(int cfg, int lane); + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 +extern uint16_t srds_lpd_b[SRDS_MAX_BANK]; +#endif + +#endif /* __FSL_CORENET_SERDES_H */ diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index ac8c01ac15..a62b031774 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -35,7 +35,7 @@ int interrupt_init_cpu(unsigned int *decrementer_count) { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; out_be32(&pic->gcr, MPC85xx_PICGCR_RST); while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c new file mode 100644 index 0000000000..bd1909471c --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -0,0 +1,187 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset) +{ + liodns[0] = liodn_bases[dpaa_dev].id[0] + liodn_offset; + + if (liodn_bases[dpaa_dev].num_ids == 2) + liodns[1] = liodn_bases[dpaa_dev].id[1] + liodn_offset; + + return liodn_bases[dpaa_dev].num_ids; +} + +static void set_liodn(struct liodn_id_table *tbl, int size) +{ + int i; + + for (i = 0; i < size; i++) { + u32 liodn; + if (tbl[i].num_ids == 2) { + liodn = (tbl[i].id[0] << 16) | tbl[i].id[1]; + } else { + liodn = tbl[i].id[0]; + } + + out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); + } +} + +static void setup_sec_liodn_base(void) +{ + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + u32 base; + + if (!IS_E_PROCESSOR(get_svr())) + return; + + /* QILCR[QSLOM] */ + out_be32(&sec->qilcr_ms, 0x3ff<<16); + + base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) | + liodn_bases[FSL_HW_PORTAL_SEC].id[1]; + + out_be32(&sec->qilcr_ls, base); +} + +#ifdef CONFIG_SYS_DPAA_FMAN +static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, + struct liodn_id_table *tbl, int size) +{ + int i; + ccsr_fman_t *fm; + u32 base; + + switch(dev) { + case FSL_HW_PORTAL_FMAN1: + fm = (void *)CONFIG_SYS_FSL_FM1_ADDR; + break; + +#if (CONFIG_SYS_NUM_FMAN == 2) + case FSL_HW_PORTAL_FMAN2: + fm = (void *)CONFIG_SYS_FSL_FM2_ADDR; + break; +#endif + default: + printf("Error: Invalid device type to %s\n", __FUNCTION__); + return ; + } + + base = (liodn_bases[dev].id[0] << 16) | liodn_bases[dev].id[0]; + + /* setup all bases the same */ + for (i = 0; i < 32; i++) { + out_be32(&fm->fm_dma.fmdmplr[i], base); + } + + /* update tbl to ... */ + for (i = 0; i < size; i++) + tbl[i].id[0] += liodn_bases[dev].id[0]; +} +#endif + +static void setup_pme_liodn_base(void) +{ +#ifdef CONFIG_SYS_DPAA_PME + ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR; + u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) | + liodn_bases[FSL_HW_PORTAL_PME].id[1]; + + out_be32(&pme->liodnbr, base); +#endif +} + +void set_liodns(void) +{ + /* setup general liodn offsets */ + set_liodn(liodn_tbl, liodn_tbl_sz); + + /* setup SEC block liodn bases & offsets if we have one */ + if (IS_E_PROCESSOR(get_svr())) { + set_liodn(sec_liodn_tbl, sec_liodn_tbl_sz); + setup_sec_liodn_base(); + } + + /* setup FMAN block(s) liodn bases & offsets if we have one */ +#ifdef CONFIG_SYS_DPAA_FMAN + set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz); + setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, + fman1_liodn_tbl_sz); + +#if (CONFIG_SYS_NUM_FMAN == 2) + set_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); + setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, + fman2_liodn_tbl_sz); +#endif +#endif + /* setup PME liodn base */ + setup_pme_liodn_base(); +} + +static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) +{ + int i; + + for (i = 0; i < sz; i++) { + int off; + + if (tbl[i].compat == NULL) + continue; + + off = fdt_node_offset_by_compat_reg(blob, + tbl[i].compat, tbl[i].compat_offset); + if (off >= 0) { + off = fdt_setprop(blob, off, "fsl,liodn", + &tbl[i].id[0], + sizeof(u32) * tbl[i].num_ids); + if (off > 0) + printf("WARNING unable to set fsl,liodn for " + "%s: %s\n", + tbl[i].compat, fdt_strerror(off)); + } else { + debug("WARNING: could not set fsl,liodn for %s: %s.\n", + tbl[i].compat, fdt_strerror(off)); + } + } +} + +void fdt_fixup_liodn(void *blob) +{ + fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_liodn_tbl(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); +#if (CONFIG_SYS_NUM_FMAN == 2) + fdt_fixup_liodn_tbl(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); +#endif +#endif + fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz); +} diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index e05257cf04..603baef1bd 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -38,7 +38,7 @@ u32 get_my_id() int cpu_reset(int nr) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); /* the dummy read works around an errata on early 85xx MP PICs */ (void)in_be32(&pic->pir); @@ -207,7 +207,7 @@ static void plat_mp_up(unsigned long bootpg) gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); - pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; @@ -272,7 +272,7 @@ static void plat_mp_up(unsigned long bootpg) volatile u32 bpcr; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); u32 devdisr; int timeout = 10; diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c new file mode 100644 index 0000000000..a6cfaa5971 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -0,0 +1,115 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO(11, 12, 6, 5), + SET_QP_INFO(13, 14, 7, 6), + SET_QP_INFO(15, 16, 8, 7), + SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ + SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ +}; + +struct liodn_id_table liodn_tbl[] = { + SET_USB_LIODN(1, "fsl-usb2-mph", 127), + SET_USB_LIODN(2, "fsl-usb2-dr", 157), + + SET_SDHC_LIODN(1, 156), + + SET_PCI_LIODN(1, 193), + SET_PCI_LIODN(2, 194), + SET_PCI_LIODN(3, 195), + + SET_DMA_LIODN(1, 196), + SET_DMA_LIODN(2, 197), + + SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0), + + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), + SET_PME_LIODN(128), +}; + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 11), + SET_FMAN_RX_1G_LIODN(1, 1, 12), + SET_FMAN_RX_1G_LIODN(1, 2, 13), + SET_FMAN_RX_1G_LIODN(1, 3, 14), + SET_FMAN_RX_10G_LIODN(1, 0, 15), +}; + +#if (CONFIG_SYS_NUM_FMAN == 2) +struct liodn_id_table fman2_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(2, 0, 16), + SET_FMAN_RX_1G_LIODN(2, 1, 17), + SET_FMAN_RX_1G_LIODN(2, 2, 18), + SET_FMAN_RX_1G_LIODN(2, 3, 19), + SET_FMAN_RX_10G_LIODN(2, 0, 20), +}; +#endif +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 146, 154), + SET_SEC_JR_LIODN_ENTRY(1, 147, 155), + SET_SEC_JR_LIODN_ENTRY(2, 178, 186), + SET_SEC_JR_LIODN_ENTRY(3, 179, 187), + SET_SEC_RTIC_LIODN_ENTRY(a, 144), + SET_SEC_RTIC_LIODN_ENTRY(b, 145), + SET_SEC_RTIC_LIODN_ENTRY(c, 176), + SET_SEC_RTIC_LIODN_ENTRY(d, 177), + SET_SEC_DECO_LIODN_ENTRY(0, 129, 161), + SET_SEC_DECO_LIODN_ENTRY(1, 130, 162), + SET_SEC_DECO_LIODN_ENTRY(2, 131, 163), + SET_SEC_DECO_LIODN_ENTRY(3, 132, 164), + SET_SEC_DECO_LIODN_ENTRY(4, 133, 165), +}; + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#if (CONFIG_SYS_NUM_FMAN == 2) + [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64), +#endif +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133), +#endif +}; + +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c new file mode 100644 index 0000000000..87bd795293 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c @@ -0,0 +1,98 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3, + SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3, + SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, + XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE}, + [0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1, + SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + NONE, NONE, NONE, NONE}, + [0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}, + [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}, + [0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, +}; + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 +uint16_t srds_lpd_b[SRDS_MAX_BANK]; +#endif + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) { + int i; + + if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c new file mode 100644 index 0000000000..01aec6e794 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -0,0 +1,238 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +#include <asm/processor.h> +#include <asm/io.h> + +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR; + +void setup_portals(void) +{ + int i; + + /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ +#ifdef CONFIG_PHYS_64BIT + out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); +#endif + out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); + + for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { + u8 sdest = qp_info[i].sdest; + u16 fliodn = qp_info[i].fliodn; + u16 dliodn = qp_info[i].dliodn; + u16 liodn_off = qp_info[i].liodn_offset; + + out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) | + dliodn); + /* set frame liodn */ + out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); + } +} + +/* Update portal containter to match LAW setup of portal in phy map */ +void fdt_portal(void *blob, const char *compat, const char *container, + u64 addr, u32 size) +{ + int off; + + off = fdt_node_offset_by_compatible(blob, -1, compat); + if (off < 0) + return ; + + off = fdt_parent_offset(blob, off); + /* if non-zero assume we have a container */ + if (off > 0) { + char buf[60]; + const char *p, *name; + u32 *range; + int len; + + /* fixup ranges */ + range = fdt_getprop_w(blob, off, "ranges", &len); + if (range == NULL) { + printf("ERROR: container for %s has no ranges", compat); + return ; + } + + range[0] = 0; + if (len == 16) { + range[1] = addr >> 32; + range[2] = addr & 0xffffffff; + range[3] = size; + } else { + range[1] = addr & 0xffffffff; + range[2] = size; + } + fdt_setprop_inplace(blob, off, "ranges", range, len); + + /* fixup the name */ + name = fdt_get_name(blob, off, &len); + p = memchr(name, '@', len); + + if (p) + len = p - name; + + /* if we are given a container name check it + * against what we found, if it doesnt match exit out */ + if (container && (memcmp(container, name, len))) { + printf("WARNING: container names didn't match %s %s\n", + container, name); + return ; + } + + memcpy(&buf, name, len); + len += sprintf(&buf[len], "@%llx", addr); + fdt_set_name(blob, off, buf); + return ; + } + + printf("ERROR: %s isn't in a container. Not supported\n", compat); +} + +static int fdt_qportal(void *blob, int off, int id, char *name, + enum fsl_dpaa_dev dev, int create) +{ + int childoff, dev_off, num, ret = 0; + uint32_t dev_handle; + u32 liodns[2]; + + childoff = fdt_subnode_offset(blob, off, name); + if (create) { + if (childoff <= 0) + childoff = fdt_add_subnode(blob, off, name); + + if (childoff > 0) { + char handle[64], *p; + + strncpy(handle, name, sizeof(handle)); + p = strchr(handle, '@'); + if (!strncmp(name, "fman", 4)) { + *p = *(p + 1); + p++; + } + *p = '\0'; + + dev_off = fdt_path_offset(blob, handle); + if (dev_off < 0) + return dev_off; + + dev_handle = fdt_get_phandle(blob, dev_off); + if (dev_handle <= 0) { + dev_handle = fdt_alloc_phandle(blob); + fdt_setprop_cell(blob, dev_off, + "linux,phandle", dev_handle); + } + + ret = fdt_setprop(blob, childoff, "dev-handle", + &dev_handle, sizeof(dev_handle)); + if (ret < 0) + return ret; + + num = get_dpaa_liodn(dev, &liodns[0], id); + ret = fdt_setprop(blob, childoff, "fsl,liodn", + &liodns[0], sizeof(u32) * num); + } else { + return childoff; + } + } else { + if (childoff > 0) + ret = fdt_del_node(blob, childoff); + } + + return ret; +} + +void fdt_fixup_qportals(void *blob) +{ + int off, err; + unsigned int maj, min; + u32 rev_1 = in_be32(&qman->ip_rev_1); + char compat[64]; + int compat_len; + + maj = (rev_1 >> 8) & 0xff; + min = rev_1 & 0xff; + + compat_len = sprintf(compat, "fsl,qman-portal-%u.%u", maj, min) + 1; + compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); + while (off != -FDT_ERR_NOTFOUND) { + u32 liodns[2]; + const int *ci = fdt_getprop(blob, off, "cell-index", NULL); + int j, i = *ci; + + err = fdt_setprop(blob, off, "compatible", compat, compat_len); + if (err < 0) + goto err; + + liodns[0] = qp_info[i].dliodn; + liodns[1] = qp_info[i].fliodn; + + err = fdt_setprop(blob, off, "fsl,liodn", + &liodns, sizeof(u32) * 2); + if (err < 0) + goto err; + + i++; + + err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC, + IS_E_PROCESSOR(get_svr())); + if (err < 0) + goto err; + +#ifdef CONFIG_SYS_DPAA_PME + err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1); + if (err < 0) + goto err; +#else + fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0); +#endif +#ifdef CONFIG_SYS_DPAA_FMAN + for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { + char name[] = "fman@0"; + + name[sizeof(name) - 2] = '0' + j; + err = fdt_qportal(blob, off, i, name, + FSL_HW_PORTAL_FMAN1 + j, 1); + if (err < 0) + goto err; + } +#endif + +err: + if (err < 0) { + printf("ERROR: unable to create props for %s: %s\n", + fdt_get_name(blob, off, NULL), fdt_strerror(err)); + return; + } + + off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal"); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 0b5b9da032..53cefaf002 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -136,6 +136,12 @@ __secondary_start_page: mtspr L1CSR2,r8 #endif +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) + mfspr r8,L1CSR2 + oris r8,r8,(L1CSR2_DCWS)@h + mtspr L1CSR2,r8 +#endif + #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index b3cb56a5b0..3278b109fe 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -330,8 +330,18 @@ _start_e500: lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l +#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ + defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@l + li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH + mtspr MAS7,r10 +#else lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif mtspr MAS0,r6 mtspr MAS1,r7 diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 7e96664333..78007177a1 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -288,7 +288,7 @@ UnknownException(struct pt_regs *regs) void ExtIntException(struct pt_regs *regs) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); uint vect; diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index 89c1ff939d..d4abeb1b2f 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -63,9 +63,9 @@ DECLARE_GLOBAL_DATA_PTR; static int mii_discover_phy(struct eth_device *dev); #endif -int fec8xx_miiphy_read(char *devname, unsigned char addr, +int fec8xx_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, +int fec8xx_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value); static struct ether_fcc_info_s @@ -164,9 +164,9 @@ int fec_initialize(bd_t *bis) /* for FEC1 make sure that the name of the interface is the same as the old one for compatibility reasons */ if (i == 0) { - sprintf (dev->name, "FEC ETHERNET"); + sprintf (dev->name, "FEC"); } else { - sprintf (dev->name, "FEC%d ETHERNET", + sprintf (dev->name, "FEC%d", ether_fcc_info[i].ether_index + 1); } @@ -990,7 +990,7 @@ void mii_init (void) * Otherwise they hang in mii_send() !!! Sorry! *****************************************************************************/ -int fec8xx_miiphy_read(char *devname, unsigned char addr, +int fec8xx_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) { short rdreg; /* register working value */ @@ -1007,7 +1007,7 @@ int fec8xx_miiphy_read(char *devname, unsigned char addr, return 0; } -int fec8xx_miiphy_write(char *devname, unsigned char addr, +int fec8xx_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) { short rdreg; /* register working value */ diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index effb967e32..e376c64d52 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -77,7 +77,7 @@ int scc_initialize(bd_t *bis) dev = (struct eth_device*) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); - sprintf(dev->name, "SCC ETHERNET"); + sprintf(dev->name, "SCC"); dev->iobase = 0; dev->priv = 0; dev->init = scc_init; diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index f309f29c04..6e13e5de02 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -266,7 +266,7 @@ int get_clocks_866 (void) long cpuclk = 0; long sccr_reg; - if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) + if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk)) diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index dc3da1689f..5b30fbdc96 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -110,8 +110,16 @@ struct cpu_type *identify_cpu(u32 ver) } int cpu_numcores() { - struct cpu_type *cpu; - cpu = gd->cpu; + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; + struct cpu_type *cpu = gd->cpu; + + /* better to query feature reporting register than just assume 1 */ +#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 +#define MPC8xxx_PICFRR_NCPU_SHIFT 8 + if (cpu == &cpu_type_unknown) + return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> + MPC8xxx_PICFRR_NCPU_SHIFT) + 1; + return cpu->num_cores; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h index 5aea517f25..06706ed78c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h @@ -48,6 +48,9 @@ typedef struct { unsigned long long total_mem; unsigned long long base_address; + + /* DDR3 RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ } common_timing_params_t; #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 4a282bc52d..e82082e74c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -93,7 +93,7 @@ static inline unsigned int compute_cas_write_latency(void) } /* Chip Select Configuration (CSn_CONFIG) */ -static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr, +static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const dimm_params_t *dimm_params) { @@ -106,28 +106,49 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr, unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ + int go_config = 0; /* Compute CS_CONFIG only for existing ranks of each DIMM. */ - if ((((i&1) == 0) - && (dimm_params[i/2].n_ranks == 1)) - || (dimm_params[i/2].n_ranks == 2)) { - unsigned int n_banks_per_sdram_device; - cs_n_en = 1; - if (i == 0) { + switch (i) { + case 0: + if (dimm_params[dimm_number].n_ranks > 0) { + go_config = 1; /* These fields only available in CS0_CONFIG */ intlv_en = popts->memctl_interleaving; intlv_ctl = popts->memctl_interleaving_mode; } + break; + case 1: + if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ + (dimm_number == 1 && dimm_params[1].n_ranks > 0)) + go_config = 1; + break; + case 2: + if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ + (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0)) + go_config = 1; + break; + case 3: + if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ + (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \ + (dimm_number == 3 && dimm_params[3].n_ranks > 0)) + go_config = 1; + break; + default: + break; + } + if (go_config) { + unsigned int n_banks_per_sdram_device; + cs_n_en = 1; ap_n_en = popts->cs_local_opts[i].auto_precharge; odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; n_banks_per_sdram_device - = dimm_params[i/2].n_banks_per_sdram_device; + = dimm_params[dimm_number].n_banks_per_sdram_device; ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; - row_bits_cs_n = dimm_params[i/2].n_row_addr - 12; - col_bits_cs_n = dimm_params[i/2].n_col_addr - 8; + row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; + col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; } - ddr->cs[i].config = (0 | ((cs_n_en & 0x1) << 31) | ((intlv_en & 0x3) << 29) @@ -178,7 +199,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) unsigned char act_pd_exit_mclk; /* Precharge powerdown exit timing (tXP). */ unsigned char pre_pd_exit_mclk; - /* Precharge powerdown exit timing (tAXPD). */ + /* ODT powerdown exit timing (tAXPD). */ unsigned char taxpd_mclk; /* Mode register set cycle time (tMRD). */ unsigned char tmrd_mclk; @@ -190,13 +211,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) * we use the tXP instead of it. * tXP=max(3nCK, 7.5ns) for DDR3. * spec has not the tAXPD, we use - * tAXPD=8, need design to confirm. + * tAXPD=1, need design to confirm. */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ act_pd_exit_mclk = picos_to_mclk(tXP); /* Mode register MR0[A12] is '1' - fast exit */ pre_pd_exit_mclk = act_pd_exit_mclk; - taxpd_mclk = 8; + taxpd_mclk = 1; tmrd_mclk = 4; /* set the turnaround time */ trwt_mclk = 1; @@ -427,6 +448,35 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); } +/* DDR SDRAM Register Control Word */ +static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm) +{ + if (common_dimm->all_DIMMs_registered + && !common_dimm->all_DIMMs_unbuffered) { + ddr->ddr_sdram_rcw_1 = + common_dimm->rcw[0] << 28 | \ + common_dimm->rcw[1] << 24 | \ + common_dimm->rcw[2] << 20 | \ + common_dimm->rcw[3] << 16 | \ + common_dimm->rcw[4] << 12 | \ + common_dimm->rcw[5] << 8 | \ + common_dimm->rcw[6] << 4 | \ + common_dimm->rcw[7]; + ddr->ddr_sdram_rcw_2 = + common_dimm->rcw[8] << 28 | \ + common_dimm->rcw[9] << 24 | \ + common_dimm->rcw[10] << 20 | \ + common_dimm->rcw[11] << 16 | \ + common_dimm->rcw[12] << 12 | \ + common_dimm->rcw[13] << 8 | \ + common_dimm->rcw[14] << 4 | \ + common_dimm->rcw[15]; + debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); + debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); + } +} + /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, @@ -521,6 +571,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, unsigned int d_init; /* DRAM data initialization */ unsigned int rcw_en = 0; /* Register Control Word Enable */ unsigned int md_en = 0; /* Mirrored DIMM Enable */ + unsigned int qd_en = 0; /* quad-rank DIMM Enable */ dll_rst_dis = 1; /* Make this configurable */ dqs_cfg = popts->DQS_config; @@ -562,6 +613,8 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_FSL_DDR3) md_en = popts->mirrored_dimm; #endif + rcw_en = popts->registered_dimm_en; + qd_en = popts->quad_rank_present ? 1 : 0; ddr->ddr_sdram_cfg_2 = (0 | ((frc_sr & 0x1) << 31) | ((sr_ie & 0x1) << 30) @@ -569,6 +622,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((dqs_cfg & 0x3) << 26) | ((odt_cfg & 0x3) << 21) | ((num_pr & 0xf) << 12) + | (qd_en << 9) | ((obc_cfg & 0x1) << 6) | ((ap_en & 0x1) << 5) | ((d_init & 0x1) << 4) @@ -914,6 +968,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, clk_adjust = popts->clk_adjust; ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; + debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); } /* DDR Initialization Address (DDR_INIT_ADDR) */ @@ -977,9 +1032,9 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) unsigned int wodt_off = 0; /* Write to ODT off */ #if defined(CONFIG_FSL_DDR3) - rodt_on = 3; /* 2 clocks */ + rodt_on = 2; /* 2 clocks */ rodt_off = 4; /* 4 clocks */ - wodt_on = 2; /* 1 clocks */ + wodt_on = 1; /* 1 clocks */ wodt_off = 4; /* 4 clocks */ #endif @@ -1052,9 +1107,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, /* * Write leveling repetition time * at least tWLO + 6 clocks clocks - * we set it 32 + * we set it 64 */ - wrlvl_wlr = 0x5; + wrlvl_wlr = 0x6; /* * Write leveling start time * The value use for the DQS_ADJUST for the first sample @@ -1089,52 +1144,12 @@ static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; } -/* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */ -static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int rcw0 = 0; /* RCW0: Register Control Word 0 */ - unsigned int rcw1 = 0; /* RCW1: Register Control Word 1 */ - unsigned int rcw2 = 0; /* RCW2: Register Control Word 2 */ - unsigned int rcw3 = 0; /* RCW3: Register Control Word 3 */ - unsigned int rcw4 = 0; /* RCW4: Register Control Word 4 */ - unsigned int rcw5 = 0; /* RCW5: Register Control Word 5 */ - unsigned int rcw6 = 0; /* RCW6: Register Control Word 6 */ - unsigned int rcw7 = 0; /* RCW7: Register Control Word 7 */ - - ddr->ddr_sdram_rcw_1 = (0 - | ((rcw0 & 0xF) << 28) - | ((rcw1 & 0xF) << 24) - | ((rcw2 & 0xF) << 20) - | ((rcw3 & 0xF) << 16) - | ((rcw4 & 0xF) << 12) - | ((rcw5 & 0xF) << 8) - | ((rcw6 & 0xF) << 4) - | ((rcw7 & 0xF) << 0) - ); -} - -/* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */ -static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr) +static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) { - unsigned int rcw8 = 0; /* RCW0: Register Control Word 8 */ - unsigned int rcw9 = 0; /* RCW1: Register Control Word 9 */ - unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */ - unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */ - unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */ - unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */ - unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */ - unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */ - - ddr->ddr_sdram_rcw_2 = (0 - | ((rcw8 & 0xF) << 28) - | ((rcw9 & 0xF) << 24) - | ((rcw10 & 0xF) << 20) - | ((rcw11 & 0xF) << 16) - | ((rcw12 & 0xF) << 12) - | ((rcw13 & 0xF) << 8) - | ((rcw14 & 0xF) << 4) - | ((rcw15 & 0xF) << 0) - ); + if (popts->addr_hash) { + ddr->ddr_eor = 0x40000000; /* address hash enable */ + puts("Addess hashing enabled.\n"); + } } unsigned int @@ -1201,37 +1216,63 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, /* Chip Select Memory Bounds (CSn_BNDS) */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { unsigned long long ea = 0, sa = 0; - - if (popts->ba_intlv_ctl && (i > 0) && - ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) { - /* Don't set up boundaries for other CS - * other than CS0, if bank interleaving - * is enabled and not CS2+CS3 interleaved. + unsigned int cs_per_dimm + = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR; + unsigned int dimm_number + = i / cs_per_dimm; + unsigned long long rank_density + = dimm_params[dimm_number].rank_density; + + if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) || + ((i == 2) && (popts->ba_intlv_ctl & 0x04)) || + ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) { + /* + * Don't set up boundaries for unused CS + * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3 + * cs2 for cs0_cs1_cs2_cs3 + * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3 * But we need to set the ODT_RD_CFG and * ODT_WR_CFG for CS1_CONFIG here. */ - set_csn_config(i, ddr, popts, dimm_params); - break; + set_csn_config(dimm_number, i, ddr, popts, dimm_params); + continue; } - - if (dimm_params[i/2].n_ranks == 0) { + if (dimm_params[dimm_number].n_ranks == 0) { debug("Skipping setup of CS%u " - "because n_ranks on DIMM %u is 0\n", i, i/2); + "because n_ranks on DIMM %u is 0\n", i, dimm_number); continue; } if (popts->memctl_interleaving && popts->ba_intlv_ctl) { /* * This works superbank 2CS - * There are 2 memory controllers configured + * There are 2 or more memory controllers configured * identically, memory is interleaved between them, * and each controller uses rank interleaving within * itself. Therefore the starting and ending address * on each controller is twice the amount present on * each controller. */ - unsigned long long rank_density - = dimm_params[0].capacity; - ea = (2 * (rank_density >> dbw_cap_adj)) - 1; + unsigned long long ctlr_density = 0; + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1: + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + ctlr_density = dimm_params[0].rank_density * 2; + break; + case FSL_DDR_CS2_CS3: + ctlr_density = dimm_params[0].rank_density; + break; + case FSL_DDR_CS0_CS1_CS2_CS3: + /* + * The four CS interleaving should have been verified by + * populate_memctl_options() + */ + ctlr_density = dimm_params[0].rank_density * 4; + break; + default: + break; + } + ea = (CONFIG_NUM_DDR_CONTROLLERS * + (ctlr_density >> dbw_cap_adj)) - 1; } else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) { /* @@ -1243,8 +1284,6 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, * controller needs to be programmed into its * respective CS0_BNDS. */ - unsigned long long rank_density - = dimm_params[i/2].rank_density; switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { case FSL_DDR_CS0_CS1_CS2_CS3: /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS @@ -1257,9 +1296,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS * and CS2_CNDS need to be set. */ - if (!(i&1)) { - sa = dimm_params[i/2].base_address; - ea = sa + (i * (rank_density >> + if ((i == 2) && (dimm_number == 0)) { + sa = dimm_params[dimm_number].base_address + + 2 * (rank_density >> dbw_cap_adj); + ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1; + } else { + sa = dimm_params[dimm_number].base_address; + ea = sa + (2 * (rank_density >> dbw_cap_adj)) - 1; } break; @@ -1267,16 +1310,31 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, /* CS0+CS1 interleaving, CS0_CNDS needs * to be set */ - sa = common_dimm->base_address; - ea = sa + (2 * (rank_density >> dbw_cap_adj))-1; + if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { + sa = dimm_params[dimm_number].base_address; + ea = sa + (rank_density >> dbw_cap_adj) - 1; + sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); + ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); + } else { + sa = 0; + ea = 0; + } + if (i == 0) + ea += (rank_density >> dbw_cap_adj); break; case FSL_DDR_CS2_CS3: /* CS2+CS3 interleaving*/ - if (i == 2) { - sa = dimm_params[i/2].base_address; - ea = sa + (2 * (rank_density >> - dbw_cap_adj)) - 1; + if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { + sa = dimm_params[dimm_number].base_address; + ea = sa + (rank_density >> dbw_cap_adj) - 1; + sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); + ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); + } else { + sa = 0; + ea = 0; } + if (i == 2) + ea += (rank_density >> dbw_cap_adj); break; default: /* No bank(chip-select) interleaving */ break; @@ -1292,8 +1350,6 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, * memory in the two CS0 ranks. */ if (i == 0) { - unsigned long long rank_density - = dimm_params[0].rank_density; ea = (2 * (rank_density >> dbw_cap_adj)) - 1; } @@ -1303,20 +1359,14 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, * No rank interleaving and no memory controller * interleaving. */ - unsigned long long rank_density - = dimm_params[i/2].rank_density; - sa = dimm_params[i/2].base_address; + sa = dimm_params[dimm_number].base_address; ea = sa + (rank_density >> dbw_cap_adj) - 1; - if (i&1) { - if ((dimm_params[i/2].n_ranks == 1)) { - /* Odd chip select, single-rank dimm */ - sa = 0; - ea = 0; - } else { - /* Odd chip select, dual-rank DIMM */ - sa += rank_density >> dbw_cap_adj; - ea += rank_density >> dbw_cap_adj; - } + if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { + sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); + ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); + } else { + sa = 0; + ea = 0; } } @@ -1329,10 +1379,12 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, ); debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); - set_csn_config(i, ddr, popts, dimm_params); + set_csn_config(dimm_number, i, ddr, popts, dimm_params); set_csn_config_2(i, ddr); } + set_ddr_eor(ddr, popts); + #if !defined(CONFIG_FSL_DDR1) set_timing_cfg_0(ddr); #endif @@ -1361,8 +1413,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sr_cntr(ddr, sr_it); - set_ddr_sdram_rcw_1(ddr); - set_ddr_sdram_rcw_2(ddr); + set_ddr_sdram_rcw(ddr, common_dimm); return check_fsl_memctl_config_regs(ddr); } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index f1220750df..98acb8dd52 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -73,6 +73,7 @@ extern unsigned int populate_memctl_options(int all_DIMMs_registered, memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num); +extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index d4199baa82..29cea53266 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -90,6 +90,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, { unsigned int retval; unsigned int mtb_ps; + int i; if (spd->mem_type) { if (spd->mem_type != SPD_MEMTYPE_DDR3) { @@ -131,8 +132,11 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, case 0x01: /* RDIMM */ case 0x05: /* Mini-RDIMM */ pdimm->registered_dimm = 1; /* register buffered */ + for (i = 0; i < 16; i += 2) { + pdimm->rcw[i] = spd->mod_section.registered.rcw[i/2] & 0x0F; + pdimm->rcw[i+1] = (spd->mod_section.registered.rcw[i/2] >> 4) & 0x0F; + } break; - case 0x02: /* UDIMM */ case 0x03: /* SO-DIMM */ case 0x04: /* Micro-DIMM */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index e888e3ea56..029e566b6b 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -76,7 +76,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms) { - unsigned int i; + unsigned int i, j; unsigned int tCKmin_X_ps = 0; unsigned int tCKmax_ps = 0xFFFFFFFF; @@ -98,7 +98,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, unsigned int tDQSQ_max_ps = 0; unsigned int tQHS_ps = 0; - unsigned int temp1, temp2; + unsigned int temp1, temp2, temp3; unsigned int additive_latency = 0; #if !defined(CONFIG_FSL_DDR3) const unsigned int mclk_ps = get_memory_clk_period_ps(); @@ -118,6 +118,18 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, temp1++; continue; } + if (dimm_params[i].n_ranks == 4 && i != 0) { + printf("Found Quad-rank DIMM in wrong bank, ignored." + " Software may not run as expected.\n"); + temp1++; + continue; + } + if (dimm_params[i].n_ranks == 4 && \ + CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) { + printf("Found Quad-rank DIMM, not able to support."); + temp1++; + continue; + } /* * Find minimum tCKmax_ps to find fastest slow speed, @@ -219,6 +231,20 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, "DIMMs detected!\n"); } + temp1 = 0; + if (outpdimm->all_DIMMs_registered) + for (j = 0; j < 16; j++) { + outpdimm->rcw[j] = dimm_params[0].rcw[j]; + for (i = 1; i < number_of_dimms; i++) + if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) { + temp3 = 1; + break; + } + } + + if (temp1 != 0) + printf("ERROR: Mix different RDIMM detected!\n"); + #if defined(CONFIG_FSL_DDR3) if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms)) return 1; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index faa1af95ef..6d582e97d4 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -100,8 +100,8 @@ const char * step_to_string(unsigned int step) { int step_assign_addresses(fsl_ddr_info_t *pinfo, unsigned int dbw_cap_adj[], - unsigned int *memctl_interleaving, - unsigned int *rank_interleaving) + unsigned int *all_memctl_interleaving, + unsigned int *all_ctlr_rank_interleaving) { int i, j; @@ -152,30 +152,30 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, } } - /* - * Check if all controllers are configured for memory - * controller interleaving. - */ j = 0; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (pinfo->memctl_opts[i].memctl_interleaving) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + if (pinfo->memctl_opts[i].memctl_interleaving) j++; - } - } - if (j == 2) - *memctl_interleaving = 1; + /* + * Not support less than all memory controllers interleaving + * if more than two controllers + */ + if (j == CONFIG_NUM_DDR_CONTROLLERS) + *all_memctl_interleaving = 1; /* Check that all controllers are rank interleaving. */ j = 0; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (pinfo->memctl_opts[i].ba_intlv_ctl) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + if (pinfo->memctl_opts[i].ba_intlv_ctl) j++; - } - } - if (j == 2) - *rank_interleaving = 1; + /* + * All memory controllers must be populated to qualify for + * all controller rank interleaving + */ + if (j == CONFIG_NUM_DDR_CONTROLLERS) + *all_ctlr_rank_interleaving = 1; - if (*memctl_interleaving) { + if (*all_memctl_interleaving) { unsigned long long addr, total_mem_per_ctlr = 0; /* * If interleaving between memory controllers, @@ -316,7 +316,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) &pinfo->memctl_opts[i], pinfo->dimm_params[i], i); } - + check_interleaving_options(pinfo); case STEP_ASSIGN_ADDRESSES: /* STEP 5: Assign addresses to chip selects */ step_assign_addresses(pinfo, diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 46731c8153..774c0e4b42 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <hwconfig.h> #include <asm/fsl_ddr_sdram.h> #include "ddr.h" @@ -23,7 +24,6 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, unsigned int ctrl_num) { unsigned int i; - const char *p; /* Chip select options. */ @@ -204,6 +204,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * meet the tQDSS under different loading. */ popts->wrlvl_en = 1; + popts->zq_en = 1; popts->wrlvl_override = 0; #endif @@ -212,78 +213,128 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * Please refer to doc/README.fsl-ddr for the detail. * * If memory controller interleaving is enabled, then the data - * bus widths must be programmed identically for the 2 memory - * controllers. + * bus widths must be programmed identically for all memory controllers. * - * XXX: Attempt to set both controllers to the same chip select + * XXX: Attempt to set all controllers to the same chip select * interleaving mode. It will do a best effort to get the * requested ranks interleaved together such that the result * should be a subset of the requested configuration. */ #if (CONFIG_NUM_DDR_CONTROLLERS > 1) - if ((p = getenv("memctl_intlv_ctl")) != NULL) { + if (hwconfig_sub("fsl_ddr", "ctlr_intlv")) { if (pdimm[0].n_ranks == 0) { - printf("There is no rank on CS0. Because only rank on " - "CS0 and ranks chip-select interleaved with CS0" + printf("There is no rank on CS0 for controller %d. Because only" + " rank on CS0 and ranks chip-select interleaved with CS0" " are controller interleaved, force non memory " - "controller interleaving\n"); + "controller interleaving\n", ctrl_num); popts->memctl_interleaving = 0; } else { popts->memctl_interleaving = 1; - if (strcmp(p, "cacheline") == 0) + /* + * test null first. if CONFIG_HWCONFIG is not defined + * hwconfig_arg_cmp returns non-zero + */ + if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "null")) { + popts->memctl_interleaving = 0; + debug("memory controller interleaving disabled.\n"); + } else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "cacheline")) popts->memctl_interleaving_mode = FSL_DDR_CACHE_LINE_INTERLEAVING; - else if (strcmp(p, "page") == 0) + else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "page")) popts->memctl_interleaving_mode = FSL_DDR_PAGE_INTERLEAVING; - else if (strcmp(p, "bank") == 0) + else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "bank")) popts->memctl_interleaving_mode = FSL_DDR_BANK_INTERLEAVING; - else if (strcmp(p, "superbank") == 0) + else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "superbank")) popts->memctl_interleaving_mode = FSL_DDR_SUPERBANK_INTERLEAVING; - else - popts->memctl_interleaving_mode = - simple_strtoul(p, NULL, 0); + else { + popts->memctl_interleaving = 0; + printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); + } } } #endif - - if( ((p = getenv("ba_intlv_ctl")) != NULL) && + if ((hwconfig_sub("fsl_ddr", "bank_intlv")) && (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { - if (strcmp(p, "cs0_cs1") == 0) + /* test null first. if CONFIG_HWCONFIG is not defined, + * hwconfig_arg_cmp returns non-zero */ + if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "null")) + debug("bank interleaving disabled.\n"); + else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1")) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; - else if (strcmp(p, "cs2_cs3") == 0) + else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs2_cs3")) popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; - else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0) + else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_and_cs2_cs3")) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; - else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0) + else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_cs2_cs3")) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; else - popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0); - + printf("hwconfig has unrecognized parameter for bank_intlv.\n"); switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { case FSL_DDR_CS0_CS1_CS2_CS3: +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + if (pdimm[0].n_ranks < 4) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(chip-select) for " + "CS0+CS1+CS2+CS3 on controller %d, " + "force non-interleaving!\n", ctrl_num); + } +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(chip-select) for " + "CS0+CS1+CS2+CS3 on controller %d, " + "force non-interleaving!\n", ctrl_num); + } + if (pdimm[0].capacity != pdimm[1].capacity) { + popts->ba_intlv_ctl = 0; + printf("Not identical DIMM size for " + "CS0+CS1+CS2+CS3 on controller %d, " + "force non-interleaving!\n", ctrl_num); + } +#endif + break; case FSL_DDR_CS0_CS1: - if (pdimm[0].n_ranks != 2) { + if (pdimm[0].n_ranks < 2) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " - "CS0+CS1, force non-interleaving!\n"); + "CS0+CS1 on controller %d, " + "force non-interleaving!\n", ctrl_num); } break; case FSL_DDR_CS2_CS3: - if (pdimm[1].n_ranks !=2){ +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + if (pdimm[0].n_ranks < 4) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(chip-select) for CS2+CS3 " + "on controller %d, force non-interleaving!\n", ctrl_num); + } +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (pdimm[1].n_ranks < 2) { popts->ba_intlv_ctl = 0; - printf("Not enough bank(CS) for CS2+CS3, " - "force non-interleaving!\n"); + printf("Not enough bank(chip-select) for CS2+CS3 " + "on controller %d, force non-interleaving!\n", ctrl_num); } +#endif break; case FSL_DDR_CS0_CS1_AND_CS2_CS3: - if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) { +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + if (pdimm[0].n_ranks < 4) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(CS) for CS0+CS1 and " + "CS2+CS3 on controller %d, " + "force non-interleaving!\n", ctrl_num); + } +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) { popts->ba_intlv_ctl = 0; - printf("Not enough bank(CS) for CS0+CS1 or " - "CS2+CS3, force non-interleaving!\n"); + printf("Not enough bank(CS) for CS0+CS1 and " + "CS2+CS3 on controller %d, " + "force non-interleaving!\n", ctrl_num); } +#endif break; default: popts->ba_intlv_ctl = 0; @@ -291,7 +342,48 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } } + if (hwconfig_sub("fsl_ddr", "addr_hash")) { + if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null")) + popts->addr_hash = 0; + else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true")) + popts->addr_hash = 1; + } + + if (pdimm[0].n_ranks == 4) + popts->quad_rank_present = 1; + fsl_ddr_board_options(popts, pdimm, ctrl_num); return 0; } + +void check_interleaving_options(fsl_ddr_info_t *pinfo) +{ + int i, j, check_n_ranks, intlv_fixed = 0; + unsigned long long check_rank_density; + /* + * Check if all controllers are configured for memory + * controller interleaving. Identical dimms are recommended. At least + * the size should be checked. + */ + j = 0; + check_n_ranks = pinfo->dimm_params[0][0].n_ranks; + check_rank_density = pinfo->dimm_params[0][0].rank_density; + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if ((pinfo->memctl_opts[i].memctl_interleaving) && \ + (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \ + (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) { + j++; + } + } + if (j != CONFIG_NUM_DDR_CONTROLLERS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + if (pinfo->memctl_opts[i].memctl_interleaving) { + pinfo->memctl_opts[i].memctl_interleaving = 0; + intlv_fixed = 1; + } + if (intlv_fixed) + printf("Not all DIMMs are identical in size. " + "Memory controller interleaving disabled.\n"); + } +} diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 2fee995690..2cfc37f752 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -985,7 +985,7 @@ u32 DQS_autocalibration(void) puts(str); #if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION) - i = getenv_r("autocalib", tmp, sizeof(tmp)); + i = getenv_f("autocalib", tmp, sizeof(tmp)); if (i < 0) strcpy(tmp, CONFIG_AUTOCALIB); diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index c04eede90d..b31bd0bcc4 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -142,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq) * modify it. */ if (temp == 1) { - mfcpr(CPR0_PLLD, reg); - /* Get current value of fbdv. */ - temp = (reg & PLLD_FBDV_MASK) >> 24; - fbdv = temp ? temp : 32; - /* Get current value of lfbdv. */ - temp = (reg & PLLD_LFBDV_MASK); - lfbdv = temp ? temp : 64; /* * Load register that contains current boot strapping option. */ mfcpr(CPR0_ICFG, reg); - /* Shift strapping option into low 3 bits.*/ - reg = (reg >> 28); + /* + * Strapping option bits (ICS) are already in correct position, + * only masking needed. + */ + reg &= CPR0_ICFG_ICS_MASK; if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) || (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) { + mfcpr(CPR0_PLLD, reg); + + /* Get current value of fbdv. */ + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + + /* Get current value of lfbdv. */ + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + /* * Get current value of FWDVA. Assign current FWDVA to * new FWDVB. @@ -165,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq) mfcpr(CPR0_PLLD, reg); target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; fwdvb = target_fwdvb ? target_fwdvb : 8; + /* * Get current value of FWDVB. Assign current FWDVB to * new FWDVA. */ target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; fwdva = target_fwdva ? target_fwdva : 16; + /* * Update CPR0_PLLD with switched FWDVA and FWDVB. */ @@ -181,6 +189,7 @@ void reconfigure_pll(u32 new_cpu_freq) ((fbdv == 32 ? 0 : fbdv) << 24) | (lfbdv == 64 ? 0 : lfbdv); mtcpr(CPR0_PLLD, reg); + /* Acknowledge that a reset is required. */ reset_needed = 1; } diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 22ed5c25ea..4fec126f40 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -338,7 +338,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) return 0; } -int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, +int emac4xx_miiphy_read (const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) { unsigned long sta_reg; @@ -359,7 +359,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, /* write a phy reg and return the value with a rc */ /***********************************************************/ -int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg, +int emac4xx_miiphy_write (const char *devname, unsigned char addr, unsigned char reg, unsigned short value) { return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value); diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 5296dad569..4bad32f9f5 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1459,6 +1459,11 @@ relocate_code: mtspr SPRN_DTV3,r6 msync isync + + /* Invalidate data cache, now no longer our stack */ + dccci 0,0 + sync + isync #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ /* diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index f70699de27..d0986570e2 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -95,4 +95,7 @@ #define CONFIG_FSL_LBC #endif +/* All PPC boards must swap IDE bytes */ +#define CONFIG_IDE_SWAP_IO + #endif /* _ASM_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h index 55923e09b3..be8260277b 100644 --- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h +++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h @@ -81,6 +81,9 @@ typedef struct dimm_params_s { unsigned int tRTP_ps; /* byte 38, spd->trtp */ unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ unsigned int tQHS_ps; /* byte 45, spd->tqhs */ + + /* DDR3 RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ } dimm_params_t; extern unsigned int ddr_compute_dimm_parameters( diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 02920dbfd7..d576eb85e3 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -119,6 +119,7 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; + unsigned int ddr_eor; } fsl_ddr_cfg_regs_t; typedef struct memctl_options_partial_s { @@ -156,6 +157,7 @@ typedef struct memctl_options_s { unsigned int memctl_interleaving; unsigned int memctl_interleaving_mode; unsigned int ba_intlv_ctl; + unsigned int addr_hash; /* Operational mode parameters */ unsigned int ECC_mode; /* Use ECC? */ @@ -172,6 +174,7 @@ typedef struct memctl_options_s { unsigned int OTF_burst_chop_en; /* mirrior DIMMs for DDR3 */ unsigned int mirrored_dimm; + unsigned int quad_rank_present; /* Global Timing Parameters */ unsigned int cas_latency_override; diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h new file mode 100644 index 0000000000..6c01ffc41b --- /dev/null +++ b/arch/powerpc/include/asm/fsl_fman.h @@ -0,0 +1,212 @@ +/* + * MPC85xx Internal Memory Map + * + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_FMAN_H__ +#define __FSL_FMAN_H__ + +#include <asm/types.h> + +typedef struct fm_bmi_common { + u32 fmbm_init; /* BMI initialization */ + u32 fmbm_cfg1; /* BMI configuration1 */ + u32 fmbm_cfg2; /* BMI configuration2 */ + u32 res0[0x5]; + u32 fmbm_ievr; /* interrupt event register */ + u32 fmbm_ier; /* interrupt enable register */ + u32 fmbm_ifr; /* interrupt force register */ + u32 res1[0x5]; + u32 fmbm_arb[0x8]; /* BMI arbitration */ + u32 res2[0x28]; + u32 fmbm_gde; /* global debug enable */ + u32 fmbm_pp[0x3f]; /* BMI port parameters */ + u32 res3; + u32 fmbm_pfs[0x3f]; /* BMI port FIFO size */ + u32 res4; + u32 fmbm_ppid[0x3f];/* port partition ID */ +} fm_bmi_common_t; + +typedef struct fm_qmi_common { + u32 fmqm_gc; /* general configuration register */ + u32 res0; + u32 fmqm_eie; /* error interrupt event register */ + u32 fmqm_eien; /* error interrupt enable register */ + u32 fmqm_eif; /* error interrupt force register */ + u32 fmqm_ie; /* interrupt event register */ + u32 fmqm_ien; /* interrupt enable register */ + u32 fmqm_if; /* interrupt force register */ + u32 fmqm_gs; /* global status register */ + u32 fmqm_ts; /* task status register */ + u32 fmqm_etfc; /* enqueue total frame counter */ + u32 fmqm_dtfc; /* dequeue total frame counter */ + u32 fmqm_dc0; /* dequeue counter 0 */ + u32 fmqm_dc1; /* dequeue counter 1 */ + u32 fmqm_dc2; /* dequeue counter 2 */ + u32 fmqm_dc3; /* dequeue counter 3 */ + u32 fmqm_dfnoc; /* dequeue FQID not override counter */ + u32 fmqm_dfcc; /* dequeue FQID from context counter */ + u32 fmqm_dffc; /* dequeue FQID from FD counter */ + u32 fmqm_dcc; /* dequeue confirm counter */ + u32 res1[0xc]; + u32 fmqm_dtrc; /* debug trap configuration register */ + u32 fmqm_efddd; /* enqueue frame descriptor dynamic debug */ + u32 res3[0x2]; + u32 res4[0xdc]; /* missing debug regs */ +} fm_qmi_common_t; + +typedef struct fm_bmi { + u8 res[1024]; +} fm_bmi_t; + +typedef struct fm_qmi { + u8 res[1024]; +} fm_qmi_t; + +typedef struct fm_parser { + u8 res[1024]; +} fm_parser_t; + +typedef struct fm_policer { + u8 res[4*1024]; +} fm_policer_t; + +typedef struct fm_keygen { + u8 res[4*1024]; +} fm_keygen_t; + +typedef struct fm_dma { + u32 fmdmsr; /* status register */ + u32 fmdmmr; /* mode register */ + u32 fmdmtr; /* bus threshold register */ + u32 fmdmhy; /* bus hysteresis register */ + u32 fmdmsetr; /* SOS emergency threshold register */ + u32 fmdmtah; /* transfer bus address high register */ + u32 fmdmtal; /* transfer bus address low register */ + u32 fmdmtcid; /* transfer bus communication ID register */ + u32 fmdmra; /* DMA bus internal ram address register */ + u32 fmdmrd; /* DMA bus internal ram data register */ + u32 res0[0xb]; + u32 fmdmdcr; /* debug counter */ + u32 fmdmemsr; /* emrgency smoother register */ + u32 res1; + u32 fmdmplr[32]; /* FM DMA PID-LIODN # register */ + u32 res[0x3c8]; +} fm_dma_t; + +typedef struct fm_fpm { + u32 fpmtnc; /* TNUM control */ + u32 fpmprc; /* Port_ID control */ + u32 res0; + u32 fpmflc; /* flush control */ + u32 fpmdis1; /* dispatch thresholds1 */ + u32 fpmdis2; /* dispatch thresholds2 */ + u32 fmepi; /* error pending interrupts */ + u32 fmrie; /* rams interrupt enable */ + u32 fpmfcevent[0x4];/* FMan controller event 0-3 */ + u32 res1[0x4]; + u32 fpmfcmask[0x4]; /* FMan controller mask 0-3 */ + u32 res2[0x4]; + u32 fpmtsc1; /* timestamp control1 */ + u32 fpmtsc2; /* timestamp control2 */ + u32 fpmtsp; /* time stamp */ + u32 fpmtsf; /* time stamp fraction */ + u32 fpmrcr; /* rams control and event */ + u32 res3[0x3]; + u32 fpmdrd[0x4]; /* data_ram data 0-3 */ + u32 res4[0xc]; + u32 fpmdra; /* data ram access */ + u32 fm_ip_rev_1; /* IP block revision 1 */ + u32 fm_ip_rev_2; /* IP block revision 2 */ + u32 fmrstc; /* reset command */ + u32 fmcld; /* classifier debug control */ + u32 fmnpi; /* normal pending interrupts */ + u32 res5; + u32 fmnee; /* event and enable */ + u32 fpmcev[0x4]; /* CPU event 0-3 */ + u32 res6[0x4]; + u32 fmfp_ps[0x40]; /* port status */ + u32 res7[0x260]; + u32 fpmts[0x80]; /* task status */ + u32 res8[0xa0]; +} fm_fpm_t; + +typedef struct fm_imem { + u8 res[4*1024]; +} fm_imem_t; + +typedef struct fm_soft_parser { + u8 res[4*1024]; +} fm_soft_parser_t; + +typedef struct fm_dtesc { + u8 res[4*1024]; +} fm_dtsec_t; + +typedef struct fm_mdio { + u8 res[4*1024]; +} fm_mdio_t; + +typedef struct fm_10gec { + u8 res[4*1024]; +} fm_10gec_t; + +typedef struct fm_10gec_mdio { + u8 res[4*1024]; +} fm_10gec_mdio_t; + +typedef struct fm_1588 { + u8 res[4*1024]; +} fm_1588_t; + +typedef struct ccsr_fman { + u8 muram[0x80000]; + fm_bmi_common_t fm_bmi_common; + fm_qmi_common_t fm_qmi_common; + u8 res0[2048]; + struct { + fm_bmi_t fm_bmi; + fm_qmi_t fm_qmi; + fm_parser_t fm_parser; + u8 res[1024]; + } port[63]; + fm_policer_t fm_policer; + fm_keygen_t fm_keygen; + fm_dma_t fm_dma; + fm_fpm_t fm_fpm; + fm_imem_t fm_imem; + u8 res1[8*1024]; + fm_soft_parser_t fm_soft_parser; + u8 res2[96*1024]; + struct { + fm_dtsec_t fm_dtesc; + fm_mdio_t fm_mdio; + } mac[4]; + u8 res3[32*1024]; + fm_10gec_t fm_10gec; + fm_10gec_mdio_t fm_10gec_mdio; + u8 res4[48*1024]; + fm_1588_t fm_1588; + u8 res5[4*1024]; +} ccsr_fman_t; + +#endif /*__FSL_FMAN_H__*/ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 12ba1a6a04..0e255ffce8 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -54,6 +54,7 @@ enum law_trgt_if { LAW_TRGT_IF_PCIE_1 = 0x00, LAW_TRGT_IF_PCIE_2 = 0x01, LAW_TRGT_IF_PCIE_3 = 0x02, + LAW_TRGT_IF_PCIE_4 = 0x03, LAW_TRGT_IF_RIO_1 = 0x08, LAW_TRGT_IF_RIO_2 = 0x09, diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h new file mode 100644 index 0000000000..4c17fe232e --- /dev/null +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -0,0 +1,142 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FSL_LIODN_H_ +#define _FSL_LIODN_H_ + +#include <asm/types.h> + +struct liodn_id_table { + const char * compat; + u32 id[2]; + u8 num_ids; + phys_addr_t compat_offset; + unsigned long reg_offset; +}; + +extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid); +extern void set_liodns(void); +extern void fdt_fixup_liodn(void *blob); + +#define SET_LIODN_BASE_1(idA) \ + { .id = { idA }, .num_ids = 1, } + +#define SET_LIODN_BASE_2(idA, idB) \ + { .id = { idA, idB }, .num_ids = 2 } + +#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ + { .compat = name, \ + .id = { idA }, .num_ids = 1, \ + .reg_offset = off + CONFIG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ + { .compat = name, \ + .id = { idA, idB }, .num_ids = 2, \ + .reg_offset = off + CONFIG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \ + SET_LIODN_ENTRY_1(compat, liodn, \ + offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \ + compatoff) + +#define SET_USB_LIODN(usbNum, compat, liodn) \ + SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\ + CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET) + +#define SET_SATA_LIODN(sataNum, liodn) \ + SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\ + CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET) + +#define SET_PCI_LIODN(pciNum, liodn) \ + SET_GUTS_LIODN("fsl,p4080-pcie", liodn, pex##pciNum##liodnr,\ + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) + +/* reg nodes for DMA start @ 0x300 */ +#define SET_DMA_LIODN(dmaNum, liodn) \ + SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\ + CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300) + +#define SET_SDHC_LIODN(sdhcNum, liodn) \ + SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\ + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) + +#define SET_QMAN_LIODN(liodn) \ + SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \ + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \ + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) + +#define SET_BMAN_LIODN(liodn) \ + SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \ + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \ + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) + +#define SET_PME_LIODN(liodn) \ + SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \ + CONFIG_SYS_FSL_CORENET_PME_OFFSET, \ + CONFIG_SYS_FSL_CORENET_PME_OFFSET) + +/* -1 from portID due to how immap has the registers */ +#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \ + CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \ + offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1]) + +/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ +#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ + SET_LIODN_ENTRY_1("fsl,fman-port-1g-rx", liodn, \ + FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \ + +/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ +#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ + SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \ + FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ + +#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ + SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) + +/* This is a bit evil since we treat rtic param as both a string & hex value */ +#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ + SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) + +#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ + SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ + offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, 0) + +extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; +extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; +extern int liodn_tbl_sz, sec_liodn_tbl_sz; +extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz; + +#endif diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h new file mode 100644 index 0000000000..cb32927a83 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -0,0 +1,59 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FSL_PORTALS_H_ +#define _FSL_PORTALS_H_ + +/* entries must be in order and contiguous */ +enum fsl_dpaa_dev { + FSL_HW_PORTAL_SEC, +#ifdef CONFIG_SYS_DPAA_FMAN + FSL_HW_PORTAL_FMAN1, +#if (CONFIG_SYS_NUM_FMAN == 2) + FSL_HW_PORTAL_FMAN2, +#endif +#endif +#ifdef CONFIG_SYS_DPAA_PME + FSL_HW_PORTAL_PME, +#endif +}; + +struct qportal_info { + u16 dliodn; /* DQRR LIODN */ + u16 fliodn; /* frame data LIODN */ + u16 liodn_offset; + u8 sdest; +}; + +#define SET_QP_INFO(dqrr, fdata, off, dest) \ + { .dliodn = dqrr, .fliodn = fdata, .liodn_offset = off, .sdest = dest } + +extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, + u32 *liodns, int liodn_offset); +extern void setup_portals(void); +extern void fdt_fixup_qportals(void *blob); + +extern struct qportal_info qp_info[]; +extern void fdt_portal(void *blob, const char *compat, const char *container, + u64 addr, u32 size); + +#endif diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index c7877b91a1..85518eb6e7 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -32,8 +32,15 @@ enum srds_prtcl { SATA2, SRIO1, SRIO2, - SGMII_FM1, - SGMII_FM2, + SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, + SGMII_FM2_DTSEC1, + SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, + SGMII_FM2_DTSEC4, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3, diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index b1d219b7aa..3dd2b7f53a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -32,6 +32,7 @@ #include <asm/fsl_dma.h> #include <asm/fsl_i2c.h> #include <asm/fsl_lbc.h> +#include <asm/fsl_fman.h> typedef struct ccsr_local { u32 ccsrbarh; /* CCSR Base Addr High */ @@ -172,7 +173,17 @@ typedef struct ccsr_ddr { u32 ddr_sr_cntr; /* self refresh counter */ u32 ddr_sdram_rcw_1; /* Control Words 1 */ u32 ddr_sdram_rcw_2; /* Control Words 2 */ - u8 res8_1b[2456]; + u8 reg_1ab[8]; + u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ + u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ + u8 res8_1b[104]; + u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ + u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ + u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ + u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ + u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ + u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ + u8 res8_1ba[0x908]; u32 ddr_dsr1; /* Debug Status 1 */ u32 ddr_dsr2; /* Debug Status 2 */ u32 ddr_cdr1; /* Control Driver 1 */ @@ -180,7 +191,21 @@ typedef struct ccsr_ddr { u8 res8_1c[200]; u32 ip_rev1; /* IP Block Revision 1 */ u32 ip_rev2; /* IP Block Revision 2 */ - u8 res8_2[512]; + u32 eor; /* Enhanced Optimization Register */ + u8 res8_2[252]; + u32 mtcr; /* Memory Test Control Register */ + u8 res8_3[28]; + u32 mtp1; /* Memory Test Pattern 1 */ + u32 mtp2; /* Memory Test Pattern 2 */ + u32 mtp3; /* Memory Test Pattern 3 */ + u32 mtp4; /* Memory Test Pattern 4 */ + u32 mtp5; /* Memory Test Pattern 5 */ + u32 mtp6; /* Memory Test Pattern 6 */ + u32 mtp7; /* Memory Test Pattern 7 */ + u32 mtp8; /* Memory Test Pattern 8 */ + u32 mtp9; /* Memory Test Pattern 9 */ + u32 mtp10; /* Memory Test Pattern 10 */ + u8 res8_4[184]; u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ @@ -218,6 +243,9 @@ typedef struct ccsr_ddr { u8 res12[184]; } ccsr_ddr_t; +#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ +#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */ + /* I2C Registers */ typedef struct ccsr_i2c { struct fsl_i2c i2c[1]; @@ -1609,6 +1637,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 +#define FSL_CORENET_DEVDISR_PCIE4 0x10000000 #define FSL_CORENET_DEVDISR_RMU 0x08000000 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000 @@ -1618,6 +1647,8 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR_DDR2 0x00080000 #define FSL_CORENET_DEVDISR_DBG 0x00010000 #define FSL_CORENET_DEVDISR_NAL 0x00008000 +#define FSL_CORENET_DEVDISR_SATA1 0x00004000 +#define FSL_CORENET_DEVDISR_SATA2 0x00002000 #define FSL_CORENET_DEVDISR_ELBC 0x00001000 #define FSL_CORENET_DEVDISR_USB1 0x00000800 #define FSL_CORENET_DEVDISR_USB2 0x00000400 @@ -1638,12 +1669,14 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000 +#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000 #define FSL_CORENET_DEVDISR2_FM2 0x00020000 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 +#define FSL_CORENET_NUM_DEVDISR 2 u8 res7[8]; u32 powmgtcsr; /* Power management status & control */ u8 res8[12]; @@ -1672,9 +1705,18 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 +#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ +#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 +#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 +#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 +#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ +#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000 +#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 +#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res19[240]; @@ -1698,10 +1740,15 @@ typedef struct ccsr_gur { u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ - u32 rmuliodnr; /* RIO Message Unit LIODN */ - u32 rduliodnr; /* RIO Doorbell Unit LIODN */ - u32 rpwuliodnr; /* RIO Port Write Unit LIODN */ - u8 res22[52]; + u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */ + u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */ + u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */ + u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */ + u32 sata1liodnr; /* SATA 1 LIODN */ + u32 sata2liodnr; /* SATA 2 LIODN */ + u32 sata3liodnr; /* SATA 3 LIODN */ + u32 sata4liodnr; /* SATA 4 LIODN */ + u8 res22[32]; u32 dma1liodnr; /* DMA 1 LIODN */ u32 dma2liodnr; /* DMA 2 LIODN */ u32 dma3liodnr; /* DMA 3 LIODN */ @@ -1736,6 +1783,12 @@ typedef struct ccsr_gur { u8 res37[380]; } ccsr_gur_t; +/* + * On p4080 we have an LIODN for msg unit (rmu) but not maintenance + * everything after has RMan thus msg unit LIODN is used for maintenance + */ +#define rmuliodnr rio1maintliodnr + typedef struct ccsr_clk { u32 clkc0csr; /* Core 0 Clock control/status */ u8 res1[0x1c]; @@ -2004,38 +2057,125 @@ enum { /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 typedef struct ccsr_sec { - u8 res1[0xfa0]; + u32 res0; + u32 mcfgr; /* Master CFG Register */ + u8 res1[0x8]; + struct { + u32 ms; /* Job Ring LIODN Register, MS */ + u32 ls; /* Job Ring LIODN Register, LS */ + } jrliodnr[4]; + u8 res2[0x30]; + struct { + u32 ms; /* RTIC LIODN Register, MS */ + u32 ls; /* RTIC LIODN Register, LS */ + } rticliodnr[4]; + u8 res3[0x1c]; + u32 decorr; /* DECO Request Register */ + struct { + u32 ms; /* DECO LIODN Register, MS */ + u32 ls; /* DECO LIODN Register, LS */ + } decoliodnr[5]; + u8 res4[0x58]; + u32 dar; /* DECO Avail Register */ + u32 drr; /* DECO Reset Register */ + u8 res5[0xe78]; u32 crnr_ms; /* CHA Revision Number Register, MS */ u32 crnr_ls; /* CHA Revision Number Register, LS */ u32 ctpr_ms; /* Compile Time Parameters Register, MS */ -#define SEC_CTPR_MS_AXI_LIODN 0x08000000 -#define SEC_CTPR_MS_QI 0x02000000 u32 ctpr_ls; /* Compile Time Parameters Register, LS */ - u8 res2[0x10]; + u8 res6[0x10]; u32 far_ms; /* Fault Address Register, MS */ u32 far_ls; /* Fault Address Register, LS */ u32 falr; /* Fault Address LIODN Register */ u32 fadr; /* Fault Address Detail Register */ - u8 res3[0x4]; + u8 res7[0x4]; u32 csta; /* CAAM Status Register */ - u8 res4[0x8]; + u8 res8[0x8]; u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ -#define SEC_RVID_MA 0x0f000000 u32 ccbvid; /* CHA Cluster Block Version ID Register */ u32 chavid_ms; /* CHA Version ID Register, MS */ u32 chavid_ls; /* CHA Version ID Register, LS */ u32 chanum_ms; /* CHA Number Register, MS */ -#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000 -#define SEC_CHANUM_MS_JQNUM_SHIFT 28 -#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 -#define SEC_CHANUM_MS_DECONUM_SHIFT 24 u32 chanum_ls; /* CHA Number Register, LS */ - u32 caamvid_ms; /* CAAM Version ID Register, MS */ - u32 caamvid_ls; /* CAAM Version ID Register, LS */ - u8 res5[0xf000]; + u32 secvid_ms; /* SEC Version ID Register, MS */ + u32 secvid_ls; /* SEC Version ID Register, LS */ + u8 res9[0x6020]; + u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ + u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ + u8 res10[0x8fd8]; } ccsr_sec_t; + +#define SEC_CTPR_MS_AXI_LIODN 0x08000000 +#define SEC_CTPR_MS_QI 0x02000000 +#define SEC_RVID_MA 0x0f000000 +#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JRNUM_SHIFT 28 +#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 +#define SEC_CHANUM_MS_DECONUM_SHIFT 24 #endif +typedef struct ccsr_qman { + struct { + u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ + u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ + u32 res; + u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */ + } qcsp[32]; + + /* Not actually reserved, but irrelevant to u-boot */ + u8 res[0xbf8 - 0x200]; + u32 ip_rev_1; + u32 ip_rev_2; + u32 fqd_bare; /* FQD Extended Base Addr Register */ + u32 fqd_bar; /* FQD Base Addr Register */ + u8 res1[0x8]; + u32 fqd_ar; /* FQD Attributes Register */ + u8 res2[0xc]; + u32 pfdr_bare; /* PFDR Extended Base Addr Register */ + u32 pfdr_bar; /* PFDR Base Addr Register */ + u8 res3[0x8]; + u32 pfdr_ar; /* PFDR Attributes Register */ + u8 res4[0x4c]; + u32 qcsp_bare; /* QCSP Extended Base Addr Register */ + u32 qcsp_bar; /* QCSP Base Addr Register */ + u8 res5[0x78]; + u32 ci_sched_cfg; /* Initiator Scheduling Configuration */ + u32 srcidr; /* Source ID Register */ + u32 liodnr; /* LIODN Register */ + u8 res6[4]; + u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ + u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ + u8 res7[0x2e8]; +} ccsr_qman_t; + +typedef struct ccsr_bman { + /* Not actually reserved, but irrelevant to u-boot */ + u8 res[0xbf8]; + u32 ip_rev_1; + u32 ip_rev_2; + u32 fbpr_bare; /* FBPR Extended Base Addr Register */ + u32 fbpr_bar; /* FBPR Base Addr Register */ + u8 res1[0x8]; + u32 fbpr_ar; /* FBPR Attributes Register */ + u8 res2[0xf0]; + u32 srcidr; /* Source ID Register */ + u32 liodnr; /* LIODN Register */ + u8 res7[0x2f4]; +} ccsr_bman_t; + +typedef struct ccsr_pme { + u8 res0[0x804]; + u32 liodnbr; /* LIODN Base Register */ + u8 res1[0x1f8]; + u32 srcidr; /* Source ID Register */ + u8 res2[8]; + u32 liodnr; /* LIODN Register */ + u8 res3[0x1e8]; + u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/ + u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/ + u8 res4[0x400]; +} ccsr_pme_t; + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2044,16 +2184,41 @@ typedef struct ccsr_sec { #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 -#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 +#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 +#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 +#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 -#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 +#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 +#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 +#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 +#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 +#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 +#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 +#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 +#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 -#define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */ +#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 +#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 +#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 +#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 +#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 +#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 +#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 +#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 +#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000 +#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 +#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 +#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 +#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 +#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 +#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 #else #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 @@ -2098,6 +2263,8 @@ typedef struct ccsr_sec { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) +#define CONFIG_SYS_FSL_CORENET_PME_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ @@ -2132,7 +2299,7 @@ typedef struct ccsr_sec { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_ADDR \ +#define CONFIG_SYS_MPC8xxx_PIC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) #define CONFIG_SYS_MPC85xx_CPM_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) @@ -2146,6 +2313,12 @@ typedef struct ccsr_sec { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_FM1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) +#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) +#define CONFIG_SYS_FSL_FM2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) #define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) @@ -2157,6 +2330,8 @@ typedef struct ccsr_sec { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) #define CONFIG_SYS_PCIE3_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) +#define CONFIG_SYS_PCIE4_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET) #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 4bebb68565..4e60cbb7a8 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1250,12 +1250,15 @@ typedef struct immap { extern immap_t *immr; -#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC86xx_DDR_OFFSET 0x2000 #define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET) -#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC86xx_DDR2_OFFSET 0x6000 #define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) +#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000 +#define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET) + #define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000 #ifdef CONFIG_MPC8610 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 89f283a6c5..84a1e2ec0d 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -495,6 +495,7 @@ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ +#define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */ #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 7b09fb51e2..0e00d8619e 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -169,7 +169,7 @@ typedef int (init_fnc_t) (void); static int init_baudrate (void) { char tmp[64]; /* long enough for environment variables */ - int i = getenv_r ("baudrate", tmp, sizeof (tmp)); + int i = getenv_f("baudrate", tmp, sizeof (tmp)); gd->baudrate = (i > 0) ? (int) simple_strtoul (tmp, NULL, 10) @@ -442,7 +442,7 @@ void board_init_f (ulong bootflag) /* * reserve protected RAM */ - i = getenv_r ("pram", (char *)tmp, sizeof (tmp)); + i = getenv_f("pram", (char *)tmp, sizeof (tmp)); reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM; addr -= (reg << 10); /* size is in kB */ debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); @@ -790,7 +790,7 @@ void board_init_r (gd_t *id, ulong dest_addr) * Fill in missing fields of bd_info. * We do this here, where we have "normal" access to the * environment; we used to do this still running from ROM, - * where had to use getenv_r(), which can be pretty slow when + * where had to use getenv_f(), which can be pretty slow when * the environment is in EEPROM. */ diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 3064121143..4c3e2fe795 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -253,7 +253,7 @@ static int boot_body_linux(bootm_headers_t *images) if (ret) return ret; -#if defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_SYS_BOOTMAPSZ) ret = boot_relocate_fdt(lmb, bootmap_base, of_flat_tree, &of_size); if (ret) return ret; @@ -292,7 +292,7 @@ static int boot_body_linux(bootm_headers_t *images) if (*initrd_start && *initrd_end) fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); } -#endif /* CONFIG_OF_LIBFDT */ +#endif /* CONFIG_OF_LIBFDT && CONFIG_SYS_BOOTMAPSZ */ return 0; } diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index b776c21d60..4f6970965b 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -88,7 +88,7 @@ ulong monitor_flash_len; static int init_baudrate(void) { char tmp[64]; /* long enough for environment variables */ - int i = getenv_r("baudrate", tmp, sizeof(tmp)); + int i = getenv_f("baudrate", tmp, sizeof(tmp)); gd->baudrate = (i > 0) ? (int)simple_strtoul(tmp, NULL, 10) |