diff options
Diffstat (limited to 'arch')
116 files changed, 3052 insertions, 294 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 239289b885..e574b0d441 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -28,6 +28,7 @@ config M68K select HAVE_PRIVATE_LIBGCC select SYS_BOOT_GET_CMDLINE select SYS_BOOT_GET_KBD + select SUPPORT_OF_CONTROL config MICROBLAZE bool "MicroBlaze architecture" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 00be3d1721..01ff57cf1b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1262,6 +1262,28 @@ config TARGET_LS1012AFRDM development platform that supports the QorIQ LS1012A Layerscape Architecture processor. +config TARGET_LS1028AQDS + bool "Support ls1028aqds" + select ARCH_LS1028A + select ARM64 + select ARMV8_MULTIENTRY + help + Support for Freescale LS1028AQDS platform + The LS1028A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS1028A + Layerscape Architecture processor. + +config TARGET_LS1028ARDB + bool "Support ls1028ardb" + select ARCH_LS1028A + select ARM64 + select ARMV8_MULTIENTRY + help + Support for Freescale LS1028ARDB platform + The LS1028A Development System (RDB) is a high-performance + development platform that supports the QorIQ LS1028A + Layerscape Architecture processor. + config TARGET_LS1088ARDB bool "Support ls1088ardb" select ARCH_LS1088A @@ -1466,6 +1488,7 @@ config ARCH_STM32MP imply CMD_DM imply CMD_POWEROFF imply ENV_VARS_UBOOT_RUNTIME_CONFIG + imply USE_PREBOOT help Support for STM32MP SoC family developed by STMicroelectronics, MPUs based on ARM cortex A core @@ -1666,6 +1689,7 @@ source "board/freescale/ls2080a/Kconfig" source "board/freescale/ls2080aqds/Kconfig" source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1088a/Kconfig" +source "board/freescale/ls1028a/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index 3db31c0209..5de63053d5 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -49,6 +49,9 @@ unsigned long long get_ticks(void) ulong timer_get_boot_us(void) { + if (!gd->arch.timer_rate_hz) + timer_init(); + return lldiv(get_ticks(), gd->arch.timer_rate_hz / 1000000); } diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 7405c3a4a1..8a97d5b3fb 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -104,6 +104,7 @@ config PSCI_RESET !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \ !TARGET_LS1012AFRWY && \ + !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f48481f465..a843c1eb65 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -20,6 +20,40 @@ config ARCH_LS1012A select SYS_I2C_MXC_I2C2 imply PANIC_HANG +config ARCH_LS1028A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_FSL_HAS_CCI400 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select FSL_TZASC_1 + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A008514 if !TFABOOT + select SYS_FSL_ERRATUM_A009663 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + imply PANIC_HANG + config ARCH_LS1043A bool select ARMV8_SET_SMPEN @@ -242,8 +276,9 @@ config FSL_LAYERSCAPE config FSL_PCIE_COMPAT string "PCIe compatible of Kernel DT" - depends on PCIE_LAYERSCAPE + depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4 default "fsl,ls1012a-pcie" if ARCH_LS1012A + default "fsl,ls1028a-pcie" if ARCH_LS1028A default "fsl,ls1043a-pcie" if ARCH_LS1043A default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A @@ -343,6 +378,7 @@ config SYS_FSL_ERRATUM_A010539 config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" + default 2 if ARCH_LS1028A default 4 if ARCH_LS1043A default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A @@ -377,7 +413,7 @@ config QSPI_AHB_INIT config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 - default 0x3090000 if ARCH_LS1088A + default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A default 0x180000 if FSL_LSCH2 help Offset for CCI400 base @@ -446,6 +482,7 @@ config CLUSTER_CLK_FREQ config SYS_FSL_PCLK_DIV int "Platform clock divider" + default 1 if ARCH_LS1028A default 1 if ARCH_LS1043A default 1 if ARCH_LS1046A default 1 if ARCH_LS1088A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index e9bc987a9c..a8d3cf91fc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -48,3 +48,7 @@ endif ifneq ($(CONFIG_ARCH_LS1088A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o endif + +ifneq ($(CONFIG_ARCH_LS1028A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o +endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 12d709e23e..edb9c96658 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -58,6 +58,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), @@ -246,18 +247,34 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) +#endif +#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #endif +#ifdef SYS_PCIE5_PHYS_ADDR + { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR, + SYS_PCIE5_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif +#ifdef SYS_PCIE6_PHYS_ADDR + { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR, + SYS_PCIE6_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | @@ -341,11 +358,13 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#endif { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_SIZE3, PTE_BLOCK_MEMTYPE(MT_NORMAL) | @@ -448,16 +467,20 @@ static void fix_pcie_mmu_map(void) final_map[i].virt = 0x2800000000ULL; final_map[i].size = 0x800000000ULL; break; +#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR case CONFIG_SYS_PCIE3_PHYS_ADDR: final_map[i].phys = 0x3000000000ULL; final_map[i].virt = 0x3000000000ULL; final_map[i].size = 0x800000000ULL; break; +#endif +#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR case CONFIG_SYS_PCIE4_PHYS_ADDR: final_map[i].phys = 0x3800000000ULL; final_map[i].virt = 0x3800000000ULL; final_map[i].size = 0x800000000ULL; break; +#endif default: break; } @@ -785,12 +808,8 @@ enum env_location env_get_location(enum env_operation op, int prio) if (prio) return ENVL_UNKNOWN; -#ifdef CONFIG_CHAIN_OF_TRUST - /* Check Boot Mode - * If Boot Mode is Secure, return ENVL_NOWHERE - */ - if (fsl_check_boot_mode_secure() == 1) - goto done; +#ifdef CONFIG_ENV_IS_NOWHERE + return env_loc; #endif switch (src) { @@ -820,9 +839,6 @@ enum env_location env_get_location(enum env_operation op, int prio) break; } -#ifdef CONFIG_CHAIN_OF_TRUST -done: -#endif return env_loc; } #endif /* CONFIG_TFABOOT */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index a0e262169e..ad55573c85 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -8,6 +8,7 @@ SoC overview 6. LS2088A 7. LS2081A 8. LX2160A + 9. LS1028A LS1043A --------- @@ -328,3 +329,53 @@ LX2160A SoC has 2 more similar SoC personalities 2)LX2080A, few difference w.r.t. LX2160A: a) Eight 64-bit ARM v8 Cortex-A72 CPUs + + +LS1028A +-------- +The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with +a GPU and LCD controller, as well as two TSN-enabled Ethernet controllers and +a TSNenabled 4-port switch. + +The high performance Cortex-A72 cores, performing above 16,000 CoreMarks, +combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and +Octal/Quad SPI interfaces provide capabilities for a number of industrial and +embedded applications. The device provides excellent integration with the +new Time-Sensitive Networking standard, and enables a number of +TSN applications. + +The LS1028A SoC includes the following function and features: + - Two 64-bit ARM v8 A72 CPUs + - Cache Coherent interconnect (CCI-400) + - One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC + - eDP/Displayport interface + - Graphics processing unit + - One Configurable x4 SerDes + - Ethernet interfaces + - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one + ethernet MAC supporting 1G, 100M, 10M. + - Switched: TSN IP to support four 2.5/1G interfaces. + - None of the MACs support MACSEC + - Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII + - Support for 10G-SXGMII and 10G-QXGMII. + - Energy efficient Ethernet support (802.3az) + - IEEE 1588 support + - High-speed peripheral interfaces + - Two PCIe 3.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controller + - Additional peripheral interfaces + - Two high-speed USB 2.0/3.0 controllers with integrated PHY each + supporting host or device modes + - Two Enhanced secure digital host controllers (SD/SDIO/eMMC) + - Two Serial peripheral interface (SPI) controllers + - Eight I2C controllers + - Two UART controllers + - Additional six Industrual UARTs (LPUART). + - One FlexSPI controller + - General Purpose IO (GPIO) + - Two CAN-FD interfaces + - Eight Flextimers with PWM I/O + - Support for hardware virtualization and partitioning enforcement + - Layerscape Trust Architecture + - Service Processor (SP) provides pre-boot initialization and secure-boot + capabilities diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c new file mode 100644 index 0000000000..ef598c4cba --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; + u8 rcw_lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} }, + {0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} }, + {0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} }, + {0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} }, + {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} }, + {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} }, + {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} }, + {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0ec7bc987d..31ef2b66a3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -329,6 +329,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2088a-rdb-qspi.dtb \ fsl-ls1088a-rdb.dtb \ fsl-ls1088a-qds.dtb \ + fsl-ls1028a-rdb.dtb \ + fsl-ls1028a-qds.dtb \ fsl-lx2160a-rdb.dtb \ fsl-lx2160a-qds.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index f22cbf4b2a..1125e5753b 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -136,7 +136,9 @@ sata: sata@3200000 { compatible = "fsl,ls1012a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x0 0x20140520 0x0 0x4>; /* ecc sata addr */ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 69 4>; clocks = <&clockgen 4 0>; status = "disabled"; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts new file mode 100644 index 0000000000..46a0419d77 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1028AQDS device tree source + * + * Copyright 2019 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1028a.dtsi" + +/ { + model = "NXP Layerscape 1028a QDS Board"; + compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; +}; + +&dspi0 { + status = "okay"; +}; + +&dspi1 { + status = "okay"; +}; + +&dspi2 { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts new file mode 100644 index 0000000000..932cfa2275 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1028ARDB device tree source + * + * Copyright 2019 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1028a.dtsi" + +/ { + model = "NXP Layerscape 1028a RDB Board"; + compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; +}; + +&dspi0 { + status = "okay"; +}; + +&dspi1 { + status = "okay"; +}; + +&dspi2 { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi new file mode 100644 index 0000000000..e6a443aa77 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1028a SOC common device tree source + * + * Copyright 2019 NXP + * + */ + +/ { + compatible = "fsl,ls1028a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + clockgen: clocking@1300000 { + compatible = "fsl,ls1028a-clockgen"; + reg = <0x0 0x1300000 0x0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + memory@01080000 { + device_type = "memory"; + reg = <0x00000000 0x01080000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06040000 0 0x40000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <1 9 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ + <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ + <1 11 0x8>, /* Virtual PPI, active-low */ + <1 10 0x8>; /* Hypervisor PPI, active-low */ + }; + + fspi: flexspi@20C0000 { + compatible = "nxp,dn-fspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20C0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/ + reg-names = "FSPI", "FSPI-memory"; + num-cs = <1>; + status = "disabled"; + }; + + serial0: serial@21c0500 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + interrupts = <0 32 0x1>; /* edge triggered */ + status = "disabled"; + }; + + serial1: serial@21c0600 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + interrupts = <0 32 0x1>; /* edge triggered */ + status = "disabled"; + }; + + pcie@3400000 { + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 + 0x00 0x03480000 0x0 0x40000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x80 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 + 0x00 0x03580000 0x0 0x40000 /* lut registers */ + 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ + 0x88 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c4: i2c@2040000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2040000 0x0 0x10000>; + interrupts = <0 74 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c5: i2c@2050000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2050000 0x0 0x10000>; + interrupts = <0 74 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c6: i2c@2060000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2060000 0x0 0x10000>; + interrupts = <0 75 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c7: i2c@2070000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2070000 0x0 0x10000>; + interrupts = <0 75 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + usb1: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; + dr_mode = "host"; + status = "disabled"; + }; + + usb2: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; + dr_mode = "host"; + status = "disabled"; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + litte-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 26 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <0 26 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + }; + + esdhc0: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; + big-endian; + bus-width = <4>; + status = "disabled"; + }; + + esdhc1: esdhc@2150000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2150000 0x0 0x10000>; + interrupts = <0 63 0x4>; + big-endian; + non-removable; + bus-width = <4>; + status = "disabled"; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1028a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 4>; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + cluster1_core0_watchdog: wdt@c000000 { + compatible = "arm,sp805-wdt"; + reg = <0x0 0xc000000 0x0 0x1000>; + }; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index bb70992f9e..b159c3ca73 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -290,7 +290,9 @@ sata: sata@3200000 { compatible = "fsl,ls1043a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 69 4>; clocks = <&clockgen 4 0>; status = "disabled"; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 5ac10e05d7..fdf93fd268 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -294,7 +294,9 @@ sata: sata@3200000 { compatible = "fsl,ls1046a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 69 4>; clocks = <&clockgen 4 1>; status = "disabled"; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 9455e03466..7c705858fd 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -153,7 +153,9 @@ sata: sata@3200000 { compatible = "fsl,ls1088a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 133 4>; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 510b070582..28220781d3 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -176,4 +176,89 @@ status = "disabled"; }; + + pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */ + 0x00 0x03480000 0x0 0x40000 /* LUT registers */ + 0x00 0x034c0000 0x0 0x40000 /* PF control registers */ + 0x80 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + }; + + pcie@3500000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */ + 0x00 0x03580000 0x0 0x40000 /* LUT registers */ + 0x00 0x035c0000 0x0 0x40000 /* PF control registers */ + 0x88 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; + }; + + pcie@3600000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */ + 0x00 0x03680000 0x0 0x40000 /* LUT registers */ + 0x00 0x036c0000 0x0 0x40000 /* PF control registers */ + 0x90 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; + }; + + pcie@3700000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */ + 0x00 0x03780000 0x0 0x40000 /* LUT registers */ + 0x00 0x037c0000 0x0 0x40000 /* PF control registers */ + 0x98 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; + }; + + pcie@3800000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */ + 0x00 0x03880000 0x0 0x40000 /* LUT registers */ + 0x00 0x038c0000 0x0 0x40000 /* PF control registers */ + 0xa0 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; + }; + + pcie@3900000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */ + 0x00 0x03980000 0x0 0x40000 /* LUT registers */ + 0x00 0x039c0000 0x0 0x40000 /* PF control registers */ + 0xa8 0x00000000 0x0 0x1000>; /* configuration space */ + reg-names = "ccsr", "lut", "pf_ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; + }; }; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 7670a39617..8a0f473e25 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -406,7 +406,9 @@ sata: sata@3200000 { compatible = "fsl,ls1021a-ahci"; - reg = <0x3200000 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x0 0x20220520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 101 4>; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi index 0446fd441e..60c419251b 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi @@ -16,10 +16,6 @@ #size-cells = <1>; model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */ - chosen { - cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */ - }; - /* Clock sources */ clocks { #address-cells = <1>; diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi index 7d9b95ccf1..dc30360b0a 100644 --- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi @@ -16,8 +16,8 @@ * address mapping : RBC * Tc > + 85C : N */ -#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.43" -#define DDR_MEM_SPEED 533 +#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.44" +#define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x20000000 #define DDR_MSTR 0x00041401 @@ -108,11 +108,11 @@ #define DDR_DX1DLLCR 0x40000000 #define DDR_DX1DQTR 0xFFFFFFFF #define DDR_DX1DQSTR 0x3DB02000 -#define DDR_DX2GCR 0x0000CE81 +#define DDR_DX2GCR 0x0000CE80 #define DDR_DX2DLLCR 0x40000000 #define DDR_DX2DQTR 0xFFFFFFFF #define DDR_DX2DQSTR 0x3DB02000 -#define DDR_DX3GCR 0x0000CE81 +#define DDR_DX3GCR 0x0000CE80 #define DDR_DX3DLLCR 0x40000000 #define DDR_DX3DQTR 0xFFFFFFFF #define DDR_DX3DQSTR 0x3DB02000 diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi index 8a5a821ec4..8158a56f13 100644 --- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -1,9 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - */ - -/* STM32MP157C ED1 and ED2 BOARD configuration + * + * STM32MP157C ED1 BOARD configuration * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. * Reference used NT5CC256M16DP-DI from NANYA * @@ -15,10 +14,11 @@ * timing mode optimized * Scheduling/QoS options : type = 2 * address mapping : RBC + * Tc > + 85C : N */ -#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36" -#define DDR_MEM_SPEED 533 +#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.44" +#define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x40000000 #define DDR_MSTR 0x00040401 @@ -62,7 +62,7 @@ #define DDR_ADDRMAP11 0x00000000 #define DDR_ODTCFG 0x06000600 #define DDR_ODTMAP 0x00000001 -#define DDR_SCHED 0x00001201 +#define DDR_SCHED 0x00000C01 #define DDR_SCHED1 0x00000000 #define DDR_PERFHPR1 0x01000001 #define DDR_PERFLPR1 0x08000200 @@ -74,15 +74,15 @@ #define DDR_PCCFG 0x00000010 #define DDR_PCFGR_0 0x00010000 #define DDR_PCFGW_0 0x00000000 -#define DDR_PCFGQOS0_0 0x02100B03 +#define DDR_PCFGQOS0_0 0x02100C03 #define DDR_PCFGQOS1_0 0x00800100 -#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS0_0 0x01100C03 #define DDR_PCFGWQOS1_0 0x01000200 #define DDR_PCFGR_1 0x00010000 #define DDR_PCFGW_1 0x00000000 -#define DDR_PCFGQOS0_1 0x02100B03 -#define DDR_PCFGQOS1_1 0x00800100 -#define DDR_PCFGWQOS0_1 0x01100B03 +#define DDR_PCFGQOS0_1 0x02100C03 +#define DDR_PCFGQOS1_1 0x00800040 +#define DDR_PCFGWQOS0_1 0x01100C03 #define DDR_PCFGWQOS1_1 0x01000200 #define DDR_PGCR 0x01442E02 #define DDR_PTR0 0x0022AA5B @@ -100,7 +100,7 @@ #define DDR_MR2 0x00000208 #define DDR_MR3 0x00000000 #define DDR_ODTCR 0x00010000 -#define DDR_ZQ0CR1 0x0000005B +#define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 #define DDR_DX0DLLCR 0x40000000 #define DDR_DX0DQTR 0xFFFFFFFF diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 903d5096c7..eb21c09e01 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -229,6 +229,67 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#elif defined(CONFIG_ARCH_LS1028A) +#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 +#define CONFIG_FSL_TZASC_400 + +/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + +#define SRDS_MAX_LANES 4 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06040000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* SEC */ +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index d62754e045..bdeb62576c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -34,10 +34,19 @@ #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 +#ifdef CONFIG_ARCH_LS2080A #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 +#else +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 +#define SYS_PCIE5_PHYS_SIZE 0x800000000 +#define SYS_PCIE6_PHYS_SIZE 0x800000000 +#endif #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 9fab88ab2f..24c1b0e482 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -167,10 +167,25 @@ #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) -#ifdef CONFIG_ARCH_LS1088A +#ifdef CONFIG_ARCH_LX2160A +#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) +#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) +#endif + +#ifdef CONFIG_ARCH_LX2160A +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL +#define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL +#define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL +#elif CONFIG_ARCH_LS1088A #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL +#elif CONFIG_ARCH_LS1028A +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL #else #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL @@ -375,6 +390,12 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 30 +#elif defined(CONFIG_ARCH_LS1028A) +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 +#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 #endif #define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_MASK 0x00000400 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 7d95c4e2f5..234440b5fe 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -83,6 +83,7 @@ enum boot_src get_boot_src(void); /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ #define SVR_LS1043A_P23 0x879202 #define SVR_LS1023A_P23 0x87920A +#define SVR_LS1028A 0x870B00 #define SVR_LS1046A 0x870700 #define SVR_LS1026A 0x870708 #define SVR_LS1048A 0x870320 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index e017d8b558..c53cc57e56 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -87,7 +87,7 @@ #define FSL_PEX_STREAM_ID_NUM (0x100) #endif -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_PEX_STREAM_ID_END 18 diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index c3ca8cdf3b..27d0b6a370 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void); #endif void do_bridge_reset(int enable, unsigned int mask); +void socfpga_pl310_clear(void); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index db1983dc31..49dadd4c3d 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -70,6 +70,60 @@ void v7_outer_cache_disable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } + +void socfpga_pl310_clear(void) +{ + u32 mask = 0xff, ena = 0; + + icache_enable(); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x0, &pl310->pl310_tag_latency_ctrl); + writel(0x10, &pl310->pl310_data_latency_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + ena = readl(&pl310->pl310_ctrl); + ena |= L2X0_CTRL_EN; + + /* + * Invalidate the PL310 L2 cache. Keep the invalidation code + * entirely in L1 I-cache to avoid any bus traffic through + * the L2. + */ + asm volatile( + ".align 5 \n" + " b 3f \n" + "1: str %1, [%4] \n" + " dsb \n" + " isb \n" + " str %0, [%2] \n" + " dsb \n" + " isb \n" + "2: ldr %0, [%2] \n" + " cmp %0, #0 \n" + " bne 2b \n" + " str %0, [%3] \n" + " dsb \n" + " isb \n" + " b 4f \n" + "3: b 1b \n" + "4: nop \n" + : "+r"(mask), "+r"(ena) + : "r"(&pl310->pl310_inv_way), + "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) + : "memory", "cc"); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} #endif #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index b466307f98..b820cb0673 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -110,6 +110,7 @@ void board_init_f(ulong dummy) socfpga_init_security_policies(); socfpga_sdram_remap_zero(); + socfpga_pl310_clear(); /* Assert reset to all except L4WD0 and L4TIMER0 */ socfpga_per_reset_all(); diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 1a60cdc897..87b76b47de 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -5,7 +5,6 @@ #include <common.h> #include <asm/io.h> -#include <asm/pl310.h> #include <asm/u-boot.h> #include <asm/utils.h> #include <image.h> @@ -25,8 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; @@ -63,60 +60,6 @@ u32 spl_boot_mode(const u32 boot_device) } #endif -static void socfpga_pl310_clear(void) -{ - u32 mask = 0xff, ena = 0; - - icache_enable(); - - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x111, &pl310->pl310_tag_latency_ctrl); - writel(0x121, &pl310->pl310_data_latency_ctrl); - - /* enable BRESP, instruction and data prefetch, full line of zeroes */ - setbits_le32(&pl310->pl310_aux_ctrl, - L310_AUX_CTRL_DATA_PREFETCH_MASK | - L310_AUX_CTRL_INST_PREFETCH_MASK | - L310_SHARED_ATT_OVERRIDE_ENABLE); - - /* Enable the L2 cache */ - ena = readl(&pl310->pl310_ctrl); - ena |= L2X0_CTRL_EN; - - /* - * Invalidate the PL310 L2 cache. Keep the invalidation code - * entirely in L1 I-cache to avoid any bus traffic through - * the L2. - */ - asm volatile( - ".align 5 \n" - " b 3f \n" - "1: str %1, [%4] \n" - " dsb \n" - " isb \n" - " str %0, [%2] \n" - " dsb \n" - " isb \n" - "2: ldr %0, [%2] \n" - " cmp %0, #0 \n" - " bne 2b \n" - " str %0, [%3] \n" - " dsb \n" - " isb \n" - " b 4f \n" - "3: b 1b \n" - "4: nop \n" - : "+r"(mask), "+r"(ena) - : "r"(&pl310->pl310_inv_way), - "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) - : "memory", "cc"); - - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -} - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 73aa382712..77f66c65c0 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -17,12 +17,20 @@ config SPL select SPL_DM_RESET select SPL_SERIAL_SUPPORT select SPL_SYSCON + imply BOOTSTAGE_STASH if SPL_BOOTSTAGE + imply SPL_BOOTSTAGE if BOOTSTAGE imply SPL_DISPLAY_PRINT imply SPL_LIBDISK_SUPPORT config SYS_SOC default "stm32mp" +config SYS_MALLOC_LEN + default 0x2000000 + +config ENV_SIZE + default 0x1000 + config TARGET_STM32MP1 bool "Support stm32mp1xx" select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED @@ -33,6 +41,10 @@ config TARGET_STM32MP1 select STM32_RCC select STM32_RESET select SYS_ARCH_TIMER + imply BOOTCOUNT_LIMIT + imply BOOTSTAGE + imply CMD_BOOTCOUNT + imply CMD_BOOTSTAGE imply SYSRESET_PSCI if STM32MP1_TRUSTED imply SYSRESET_SYSCON if !STM32MP1_TRUSTED help @@ -70,6 +82,18 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 Partition on the second MMC to load U-Boot from when the MMC is being used in raw mode +config BOOTSTAGE_STASH_ADDR + default 0xC3000000 + +if BOOTCOUNT_LIMIT +config SYS_BOOTCOUNT_SINGLEWORD + default y + +# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) +config SYS_BOOTCOUNT_ADDR + default 0x5C00A154 +endif + if DEBUG_UART config DEBUG_UART_BOARD_INIT diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 9ed8d8c56c..0166649685 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -7,9 +7,9 @@ #include <dm.h> #include <misc.h> #include <asm/io.h> -#include <linux/iopoll.h> #include <asm/arch/stm32mp1_smc.h> #include <linux/arm-smccc.h> +#include <linux/iopoll.h> #define BSEC_OTP_MAX_VALUE 95 diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h index 18575842ba..b8a17cfbdd 100644 --- a/arch/arm/mach-stm32mp/include/mach/ddr.h +++ b/arch/arm/mach-stm32mp/include/mach/ddr.h @@ -6,6 +6,13 @@ #ifndef __MACH_STM32MP_DDR_H_ #define __MACH_STM32MP_DDR_H_ -int board_ddr_power_init(void); +/* DDR power initializations */ +enum ddr_type { + STM32MP_DDR3, + STM32MP_LPDDR2, + STM32MP_LPDDR3, +}; + +int board_ddr_power_init(enum ddr_type ddr_type); #endif diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index c526c88e3e..6795352044 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -88,6 +88,7 @@ enum boot_device { #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) +#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) #define TAMP_BOOT_MODE_SHIFT 8 diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index c2dff38c36..139bb09292 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -47,14 +47,14 @@ static u32 __secure stm32mp_get_gicd_base_address(void) return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; } -static void __secure stm32mp_smp_kick_all_cpus(void) +static void __secure stm32mp_raise_sgi0(int cpu) { u32 gic_dist_addr; gic_dist_addr = stm32mp_get_gicd_base_address(); - /* kick all CPUs (except this one) by writing to GICD_SGIR */ - writel(1U << 24, gic_dist_addr + GICD_SGIR); + /* ask cpu with SGI0 */ + writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR); } void __secure psci_arch_cpu_entry(void) @@ -62,6 +62,9 @@ void __secure psci_arch_cpu_entry(void) u32 cpu = psci_get_cpu_id(); psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); + + /* reset magic in TAMP register */ + writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); } int __secure psci_features(u32 function_id, u32 psci_fid) @@ -127,6 +130,16 @@ int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON) return ARM_PSCI_RET_ALREADY_ON; + /* reset magic in TAMP register */ + if (readl(TAMP_BACKUP_MAGIC_NUMBER)) + writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); + /* + * ROM code need a first SGI0 after core reset + * core is ready when magic is set to 0 in ROM code + */ + while (readl(TAMP_BACKUP_MAGIC_NUMBER)) + stm32mp_raise_sgi0(cpu); + /* store target PC and context id*/ psci_save(cpu, pc, context_id); @@ -142,7 +155,8 @@ int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, writel(BOOT_API_A7_CORE0_MAGIC_NUMBER, TAMP_BACKUP_MAGIC_NUMBER); - stm32mp_smp_kick_all_cpus(); + /* Generate an IT to start the core */ + stm32mp_raise_sgi0(cpu); return ARM_PSCI_RET_SUCCESS; } diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 1f6df5c870..fef108105b 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -6,36 +6,69 @@ config SYS_ARCH # processor family config MCF520x + select OF_CONTROL + select DM + select DM_SERIAL bool config MCF52x2 + select OF_CONTROL + select DM + select DM_SERIAL bool config MCF523x + select OF_CONTROL + select DM + select DM_SERIAL bool config MCF530x + select OF_CONTROL + select DM + select DM_SERIAL bool config MCF5301x + select OF_CONTROL + select DM + select DM_SERIAL bool config MCF532x + select OF_CONTROL + select DM + select DM_SERIAL bool config MCF537x + select OF_CONTROL + select DM + select DM_SERIAL bool config MCF5441x + select OF_CONTROL + select DM + select DM_SERIAL bool config MCF5445x + select OF_CONTROL + select DM + select DM_SERIAL bool config MCF5227x + select OF_CONTROL + select DM + select DM_SERIAL bool config MCF547x_8x + select OF_CONTROL + select DM + select DM_SERIAL bool # processor type diff --git a/arch/m68k/cpu/mcf5227x/Makefile b/arch/m68k/cpu/mcf5227x/Makefile index ef43893c51..6a38c4838e 100644 --- a/arch/m68k/cpu/mcf5227x/Makefile +++ b/arch/m68k/cpu/mcf5227x/Makefile @@ -6,4 +6,4 @@ # ccflags-y += -DET_DEBUG extra-y = start.o -obj-y = cpu.o speed.o cpu_init.o interrupts.o +obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c index 0d6a484a45..3bbc42f508 100644 --- a/arch/m68k/cpu/mcf5227x/cpu_init.c +++ b/arch/m68k/cpu/mcf5227x/cpu_init.c @@ -16,6 +16,15 @@ #include <asm/rtc.h> #include <linux/compiler.h> +void cfspi_port_conf(void) +{ + gpio_t *gpio = (gpio_t *)MMAP_GPIO; + + out_8(&gpio->par_dspi, + GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK); +} + /* * Breath some life into the CPU... * @@ -93,6 +102,8 @@ void cpu_init_f(void) #endif icache_enable(); + + cfspi_port_conf(); } /* @@ -137,57 +148,3 @@ void uart_port_conf(int port) break; } } - -#ifdef CONFIG_CF_DSPI -void cfspi_port_conf(void) -{ - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - out_8(&gpio->par_dspi, - GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK); -} - -int cfspi_claim_bus(uint bus, uint cs) -{ - dspi_t *dspi = (dspi_t *) MMAP_DSPI; - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) - return -1; - - /* Clear FIFO and resume transfer */ - clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); - - switch (cs) { - case 0: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK); - setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); - break; - case 2: - clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); - setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2); - break; - } - - return 0; -} - -void cfspi_release_bus(uint bus, uint cs) -{ - dspi_t *dspi = (dspi_t *) MMAP_DSPI; - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Clear FIFO */ - clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); - - switch (cs) { - case 0: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); - break; - case 2: - clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); - break; - } -} -#endif diff --git a/arch/m68k/cpu/mcf5227x/dspi.c b/arch/m68k/cpu/mcf5227x/dspi.c new file mode 100644 index 0000000000..8fc4da271e --- /dev/null +++ b/arch/m68k/cpu/mcf5227x/dspi.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 + * Angelo Dureghello <angleo@sysam.it> + * + * CPU specific dspi routines + */ + +#include <common.h> +#include <asm/immap.h> +#include <asm/io.h> + +#ifdef CONFIG_CF_DSPI +void dspi_chip_select(int cs) +{ + struct gpio *gpio = (struct gpio *)MMAP_GPIO; + + switch (cs) { + case 0: + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); + break; + case 2: + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); + setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2); + break; + } +} + +void dspi_chip_unselect(int cs) +{ + struct gpio *gpio = (struct gpio *)MMAP_GPIO; + + switch (cs) { + case 0: + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); + break; + case 2: + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); + break; + } +} +#endif /* CONFIG_CF_DSPI */ diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S index e1b6c35133..61f9c6859c 100644 --- a/arch/m68k/cpu/mcf5227x/start.S +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -378,7 +378,8 @@ _start: clr.l %sp@- /* run low-level board init code (from flash) */ - bsr board_init_f + move.l #board_init_f, %a1 + jsr (%a1) /* board_init_f() does not return */ diff --git a/arch/m68k/cpu/mcf5445x/Makefile b/arch/m68k/cpu/mcf5445x/Makefile index be2cb2a6fb..ba90fc3c34 100644 --- a/arch/m68k/cpu/mcf5445x/Makefile +++ b/arch/m68k/cpu/mcf5445x/Makefile @@ -6,4 +6,4 @@ # ccflags-y += -DET_DEBUG extra-y = start.o -obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o +obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 7632d9262c..8f4991c1cb 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -66,6 +66,32 @@ void init_fbcs(void) #endif } +#ifdef CONFIG_CF_DSPI +void cfspi_port_conf(void) +{ + gpio_t *gpio = (gpio_t *)MMAP_GPIO; + +#ifdef CONFIG_MCF5445x + out_8(&gpio->par_dspi, + GPIO_PAR_DSPI_SIN_SIN | + GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK); +#endif + +#ifdef CONFIG_MCF5441x + pm_t *pm = (pm_t *)MMAP_PM; + + out_8(&gpio->par_dspi0, + GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT | + GPIO_PAR_DSPI0_SCK_DSPI0SCK); + out_8(&gpio->srcr_dspiow, 3); + + /* DSPI0 */ + out_8(&pm->pmcr0, 23); +#endif +} +#endif + /* * Breath some life into the CPU... * @@ -204,6 +230,10 @@ void cpu_init_f(void) GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS); +#ifdef CONFIG_CF_SPI + cfspi_port_conf(); +#endif + #ifdef CONFIG_SYS_FSL_I2C out_be16(&gpio->par_feci2c, GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); @@ -433,115 +463,3 @@ int fecpin_setclear(struct eth_device *dev, int setclear) } #endif -#ifdef CONFIG_CF_DSPI -void cfspi_port_conf(void) -{ - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - -#ifdef CONFIG_MCF5445x - out_8(&gpio->par_dspi, - GPIO_PAR_DSPI_SIN_SIN | - GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK); -#endif - -#ifdef CONFIG_MCF5441x - pm_t *pm = (pm_t *) MMAP_PM; - - out_8(&gpio->par_dspi0, - GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT | - GPIO_PAR_DSPI0_SCK_DSPI0SCK); - out_8(&gpio->srcr_dspiow, 3); - - /* DSPI0 */ - out_8(&pm->pmcr0, 23); -#endif -} - -int cfspi_claim_bus(uint bus, uint cs) -{ - dspi_t *dspi = (dspi_t *) MMAP_DSPI; - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) - return -1; - - /* Clear FIFO and resume transfer */ - clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); - -#ifdef CONFIG_MCF5445x - switch (cs) { - case 0: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); - setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); - break; - case 1: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); - setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); - break; - case 2: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); - setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); - break; - case 3: - clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); - setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3); - break; - case 5: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); - setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); - break; - } -#endif - -#ifdef CONFIG_MCF5441x - switch (cs) { - case 0: - clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK); - setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0); - break; - case 1: - clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); - setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); - break; - } -#endif - - return 0; -} - -void cfspi_release_bus(uint bus, uint cs) -{ - dspi_t *dspi = (dspi_t *) MMAP_DSPI; - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Clear FIFO */ - clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); - -#ifdef CONFIG_MCF5445x - switch (cs) { - case 0: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); - break; - case 1: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); - break; - case 2: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); - break; - case 3: - clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); - break; - case 5: - clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); - break; - } -#endif - -#ifdef CONFIG_MCF5441x - if (cs == 1) - clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); -#endif -} - -#endif diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c new file mode 100644 index 0000000000..b0e2f2cb01 --- /dev/null +++ b/arch/m68k/cpu/mcf5445x/dspi.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 + * Angelo Dureghello <angleo@sysam.it> + * + * CPU specific dspi routines + */ + +#include <common.h> +#include <asm/immap.h> +#include <asm/io.h> + +#ifdef CONFIG_CF_DSPI +void dspi_chip_select(int cs) +{ + struct gpio *gpio = (struct gpio *)MMAP_GPIO; + +#ifdef CONFIG_MCF5445x + switch (cs) { + case 0: + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); + break; + case 1: + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); + break; + case 2: + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); + break; + case 3: + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); + setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3); + break; + case 5: + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); + break; + } +#endif +#ifdef CONFIG_MCF5441x + switch (cs) { + case 0: + clrbits_8(&gpio->par_dspi0, + ~GPIO_PAR_DSPI0_PCS0_MASK); + setbits_8(&gpio->par_dspi0, + GPIO_PAR_DSPI0_PCS0_DSPI0PCS0); + break; + case 1: + clrbits_8(&gpio->par_dspiow, + GPIO_PAR_DSPIOW_DSPI0PSC1); + setbits_8(&gpio->par_dspiow, + GPIO_PAR_DSPIOW_DSPI0PSC1); + break; + } +#endif +} + +void dspi_chip_unselect(int cs) +{ + struct gpio *gpio = (struct gpio *)MMAP_GPIO; + +#ifdef CONFIG_MCF5445x + switch (cs) { + case 0: + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); + break; + case 1: + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); + break; + case 2: + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); + break; + case 3: + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); + break; + case 5: + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); + break; + } +#endif +#ifdef CONFIG_MCF5441x + if (cs == 1) + clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); +#endif +} +#endif /* CONFIG_CF_DSPI */ diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index 7cb5db7ff0..4dd57bf39c 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -131,7 +131,8 @@ _start: * then (and always) gd struct space will be reserved */ move.l %sp, -(%sp) - bsr board_init_f_alloc_reserve + move.l #board_init_f_alloc_reserve, %a1 + jsr (%a1) /* update stack and frame-pointers */ move.l %d0, %sp @@ -139,7 +140,8 @@ _start: /* initialize reserved area */ move.l %d0, -(%sp) - bsr board_init_f_init_reserve + move.l #board_init_f_init_reserve, %a1 + jsr (%a1) /* run low-level CPU init code (from flash) */ jbsr cpu_init_f diff --git a/arch/m68k/cpu/u-boot.lds b/arch/m68k/cpu/u-boot.lds index 96451208e5..64cf2ff5ef 100644 --- a/arch/m68k/cpu/u-boot.lds +++ b/arch/m68k/cpu/u-boot.lds @@ -68,13 +68,15 @@ SECTIONS __ex_table : { *(__ex_table) } __stop___ex_table = .; - . = ALIGN(256); + . = ALIGN(4); __init_begin = .; .text.init : { *(.text.init) } .data.init : { *(.data.init) } - . = ALIGN(256); + . = ALIGN(4); __init_end = .; + _end = .; + __bss_start = .; .bss (NOLOAD) : { diff --git a/arch/m68k/dts/M5208EVBE.dts b/arch/m68k/dts/M5208EVBE.dts new file mode 100644 index 0000000000..e78513f3b8 --- /dev/null +++ b/arch/m68k/dts/M5208EVBE.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5208.dtsi" + +/ { + model = "Freescale M5208EVBE"; + compatible = "fsl,M5208EVBE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M52277EVB.dts b/arch/m68k/dts/M52277EVB.dts new file mode 100644 index 0000000000..a2210c8811 --- /dev/null +++ b/arch/m68k/dts/M52277EVB.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5227x.dtsi" + +/ { + model = "Freescale M52277EVB"; + compatible = "fsl,M52277EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M52277EVB_stmicro.dts b/arch/m68k/dts/M52277EVB_stmicro.dts new file mode 100644 index 0000000000..5fd3ca5efd --- /dev/null +++ b/arch/m68k/dts/M52277EVB_stmicro.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5227x.dtsi" + +/ { + model = "Freescale M52277_stmicro"; + compatible = "fsl,M52277_stmicro"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5235EVB.dts b/arch/m68k/dts/M5235EVB.dts new file mode 100644 index 0000000000..1a32539323 --- /dev/null +++ b/arch/m68k/dts/M5235EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf523x.dtsi" + +/ { + model = "Freescale M5235EVB"; + compatible = "fsl,M5235EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5235EVB_Flash32.dts b/arch/m68k/dts/M5235EVB_Flash32.dts new file mode 100644 index 0000000000..fcbffb23f5 --- /dev/null +++ b/arch/m68k/dts/M5235EVB_Flash32.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf523x.dtsi" + +/ { + model = "Freescale M5235EVB_Flash32"; + compatible = "fsl,M5235EVB_Flash32"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5249EVB.dts b/arch/m68k/dts/M5249EVB.dts new file mode 100644 index 0000000000..b2a1be9090 --- /dev/null +++ b/arch/m68k/dts/M5249EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5249.dtsi" + +/ { + model = "Freescale M5249EVB"; + compatible = "fsl,M5249EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5253DEMO.dts b/arch/m68k/dts/M5253DEMO.dts new file mode 100644 index 0000000000..7ebaa9a2e0 --- /dev/null +++ b/arch/m68k/dts/M5253DEMO.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5253.dtsi" + +/ { + model = "Freescale M5253DEMO"; + compatible = "fsl,M5253DEMO"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5272C3.dts b/arch/m68k/dts/M5272C3.dts new file mode 100644 index 0000000000..6efb8a4cc5 --- /dev/null +++ b/arch/m68k/dts/M5272C3.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5272.dtsi" + +/ { + model = "Freescale M5272C3"; + compatible = "fsl,M5272C3"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5275EVB.dts b/arch/m68k/dts/M5275EVB.dts new file mode 100644 index 0000000000..cd9eb7d145 --- /dev/null +++ b/arch/m68k/dts/M5275EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5275.dtsi" + +/ { + model = "Freescale M5275EVB"; + compatible = "fsl,M5275EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5282EVB.dts b/arch/m68k/dts/M5282EVB.dts new file mode 100644 index 0000000000..9527caafc2 --- /dev/null +++ b/arch/m68k/dts/M5282EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5282.dtsi" + +/ { + model = "Freescale M5282EVB"; + compatible = "fsl,M5282EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M53017EVB.dts b/arch/m68k/dts/M53017EVB.dts new file mode 100644 index 0000000000..b267488e0f --- /dev/null +++ b/arch/m68k/dts/M53017EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5301x.dtsi" + +/ { + model = "Freescale M53017EVB"; + compatible = "fsl,M53017EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5329AFEE.dts b/arch/m68k/dts/M5329AFEE.dts new file mode 100644 index 0000000000..7d121d68e7 --- /dev/null +++ b/arch/m68k/dts/M5329AFEE.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5329.dtsi" + +/ { + model = "Freescale M5329AFEE"; + compatible = "fsl,M5329AFEE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5329BFEE.dts b/arch/m68k/dts/M5329BFEE.dts new file mode 100644 index 0000000000..cd087b6ea6 --- /dev/null +++ b/arch/m68k/dts/M5329BFEE.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5329.dtsi" + +/ { + model = "Freescale M5329BFEE"; + compatible = "fsl,M5329BFEE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5373EVB.dts b/arch/m68k/dts/M5373EVB.dts new file mode 100644 index 0000000000..930f911d4a --- /dev/null +++ b/arch/m68k/dts/M5373EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf537x.dtsi" + +/ { + model = "Freescale M5373EVB"; + compatible = "fsl,M5373EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M54418TWR.dts b/arch/m68k/dts/M54418TWR.dts new file mode 100644 index 0000000000..7765c7abbb --- /dev/null +++ b/arch/m68k/dts/M54418TWR.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR"; + compatible = "fsl,M54418TWR"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR_nand_mii.dts b/arch/m68k/dts/M54418TWR_nand_mii.dts new file mode 100644 index 0000000000..9b1cb85325 --- /dev/null +++ b/arch/m68k/dts/M54418TWR_nand_mii.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR_nand_mii"; + compatible = "fsl,M54418TWR_nand_mii"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR_nand_rmii.dts b/arch/m68k/dts/M54418TWR_nand_rmii.dts new file mode 100644 index 0000000000..824a66af48 --- /dev/null +++ b/arch/m68k/dts/M54418TWR_nand_rmii.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR_nand_rmii"; + compatible = "fsl,M54418TWR_nand_rmii"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts new file mode 100644 index 0000000000..74fa197ea9 --- /dev/null +++ b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR_nand_rmii_lowfreq"; + compatible = "fsl,M54418TWR_nand_rmii_lowfreq"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR_serial_mii.dts b/arch/m68k/dts/M54418TWR_serial_mii.dts new file mode 100644 index 0000000000..22f27b5612 --- /dev/null +++ b/arch/m68k/dts/M54418TWR_serial_mii.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR_serial_mii"; + compatible = "fsl,M54418TWR_serial_mii"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR_serial_rmii.dts b/arch/m68k/dts/M54418TWR_serial_rmii.dts new file mode 100644 index 0000000000..0ddefd9da2 --- /dev/null +++ b/arch/m68k/dts/M54418TWR_serial_rmii.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR_serial_rmii"; + compatible = "fsl,M54418TWR_serial_rmii"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54451EVB.dts b/arch/m68k/dts/M54451EVB.dts new file mode 100644 index 0000000000..b57bfea2cb --- /dev/null +++ b/arch/m68k/dts/M54451EVB.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54451EVB"; + compatible = "fsl,M54451EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54451EVB_stmicro.dts b/arch/m68k/dts/M54451EVB_stmicro.dts new file mode 100644 index 0000000000..9a088e16d0 --- /dev/null +++ b/arch/m68k/dts/M54451EVB_stmicro.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54451EVB_stmicro"; + compatible = "fsl,M54451EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54455EVB.dts b/arch/m68k/dts/M54455EVB.dts new file mode 100644 index 0000000000..dd11181033 --- /dev/null +++ b/arch/m68k/dts/M54455EVB.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54455EVB"; + compatible = "fsl,M54455EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54455EVB_a66.dts b/arch/m68k/dts/M54455EVB_a66.dts new file mode 100644 index 0000000000..70d544b72d --- /dev/null +++ b/arch/m68k/dts/M54455EVB_a66.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54455EVB_a66"; + compatible = "fsl,M54455EVB_a66"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54455EVB_i66.dts b/arch/m68k/dts/M54455EVB_i66.dts new file mode 100644 index 0000000000..b37a87213f --- /dev/null +++ b/arch/m68k/dts/M54455EVB_i66.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54455EVB_i66"; + compatible = "fsl,M54455EVB_i66"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54455EVB_intel.dts b/arch/m68k/dts/M54455EVB_intel.dts new file mode 100644 index 0000000000..c92228fc8b --- /dev/null +++ b/arch/m68k/dts/M54455EVB_intel.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54455EVB_intel"; + compatible = "fsl,M5275EVB_intel"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; + diff --git a/arch/m68k/dts/M54455EVB_stm33.dts b/arch/m68k/dts/M54455EVB_stm33.dts new file mode 100644 index 0000000000..9e467f94a1 --- /dev/null +++ b/arch/m68k/dts/M54455EVB_stm33.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54455EVB_stm33"; + compatible = "fsl,M5275EVB_stm33"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M5475AFE.dts b/arch/m68k/dts/M5475AFE.dts new file mode 100644 index 0000000000..0c0a79befa --- /dev/null +++ b/arch/m68k/dts/M5475AFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475AFE"; + compatible = "fsl,M5475AFE"; +}; + diff --git a/arch/m68k/dts/M5475BFE.dts b/arch/m68k/dts/M5475BFE.dts new file mode 100644 index 0000000000..c4d14097cd --- /dev/null +++ b/arch/m68k/dts/M5475BFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475BFE"; + compatible = "fsl,M5475BFE"; +}; + diff --git a/arch/m68k/dts/M5475CFE.dts b/arch/m68k/dts/M5475CFE.dts new file mode 100644 index 0000000000..4c92c332ba --- /dev/null +++ b/arch/m68k/dts/M5475CFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475CFE"; + compatible = "fsl,M5475CFE"; +}; + diff --git a/arch/m68k/dts/M5475DFE.dts b/arch/m68k/dts/M5475DFE.dts new file mode 100644 index 0000000000..c41c1b3c12 --- /dev/null +++ b/arch/m68k/dts/M5475DFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475DFE"; + compatible = "fsl,M5475DFE"; +}; + diff --git a/arch/m68k/dts/M5475EFE.dts b/arch/m68k/dts/M5475EFE.dts new file mode 100644 index 0000000000..5a920b241a --- /dev/null +++ b/arch/m68k/dts/M5475EFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475EFE"; + compatible = "fsl,M5475EFE"; +}; + diff --git a/arch/m68k/dts/M5475FFE.dts b/arch/m68k/dts/M5475FFE.dts new file mode 100644 index 0000000000..d312a6ae8d --- /dev/null +++ b/arch/m68k/dts/M5475FFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475FFE"; + compatible = "fsl,M5475FFE"; +}; + diff --git a/arch/m68k/dts/M5475GFE.dts b/arch/m68k/dts/M5475GFE.dts new file mode 100644 index 0000000000..9e794dafa6 --- /dev/null +++ b/arch/m68k/dts/M5475GFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475GFE"; + compatible = "fsl,M5475GFE"; +}; + diff --git a/arch/m68k/dts/M5485AFE.dts b/arch/m68k/dts/M5485AFE.dts new file mode 100644 index 0000000000..3466751174 --- /dev/null +++ b/arch/m68k/dts/M5485AFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485AFE"; + compatible = "fsl,M5485AFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485BFE.dts b/arch/m68k/dts/M5485BFE.dts new file mode 100644 index 0000000000..6d48795a4d --- /dev/null +++ b/arch/m68k/dts/M5485BFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485BFE"; + compatible = "fsl,M5485BFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485CFE.dts b/arch/m68k/dts/M5485CFE.dts new file mode 100644 index 0000000000..d1a7d9d383 --- /dev/null +++ b/arch/m68k/dts/M5485CFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485CFE"; + compatible = "fsl,M5485CFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485DFE.dts b/arch/m68k/dts/M5485DFE.dts new file mode 100644 index 0000000000..7c362e26e5 --- /dev/null +++ b/arch/m68k/dts/M5485DFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485DFE"; + compatible = "fsl,M5485DFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485EFE.dts b/arch/m68k/dts/M5485EFE.dts new file mode 100644 index 0000000000..4c688dce2b --- /dev/null +++ b/arch/m68k/dts/M5485EFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485EFE"; + compatible = "fsl,M5485EFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485FFE.dts b/arch/m68k/dts/M5485FFE.dts new file mode 100644 index 0000000000..87ec2c543d --- /dev/null +++ b/arch/m68k/dts/M5485FFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485FFE"; + compatible = "fsl,M5485FFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485GFE.dts b/arch/m68k/dts/M5485GFE.dts new file mode 100644 index 0000000000..9f67e5516b --- /dev/null +++ b/arch/m68k/dts/M5485GFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485GFE"; + compatible = "fsl,M5485GFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485HFE.dts b/arch/m68k/dts/M5485HFE.dts new file mode 100644 index 0000000000..2eb2213d78 --- /dev/null +++ b/arch/m68k/dts/M5485HFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485HFE"; + compatible = "fsl,M5485HFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile new file mode 100644 index 0000000000..e059f23ccd --- /dev/null +++ b/arch/m68k/dts/Makefile @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0+ + +dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \ + M52277EVB_stmicro.dtb +dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \ + M5235EVB_Flash32.dtb +dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb +dtb-$(CONFIG_TARGET_EB_CPU5282) += eb_cpu5282.dtb \ + eb_cpu5282_internal.dtb +dtb-$(CONFIG_TARGET_M5208EVBE) += M5208EVBE.dtb +dtb-$(CONFIG_TARGET_M5249EVB) += M5249EVB.dtb +dtb-$(CONFIG_TARGET_M5253DEMO) += M5253DEMO.dtb +dtb-$(CONFIG_TARGET_M5272C3) += M5272C3.dtb +dtb-$(CONFIG_TARGET_M5275EVB) += M5275EVB.dtb +dtb-$(CONFIG_TARGET_M5282EVB) += M5282EVB.dtb +dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb +dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb +dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb +dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb +dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \ + M54418TWR_nand_mii.dtb \ + M54418TWR_nand_rmii.dtb \ + M54418TWR_serial_mii.dtb \ + M54418TWR_serial_rmii.dtb \ + M54418TWR_nand_rmii_lowfreq.dtb +dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \ + M54451EVB_stmicro.dtb +dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \ + M54455EVB_intel.dtb \ + M54455EVB_stm33.dtb \ + M54455EVB_a66.dtb \ + M54455EVB_i66.dtb +dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb +dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb +dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \ + M5475BFE.dtb \ + M5475CFE.dtb \ + M5475DFE.dtb \ + M5475EFE.dtb \ + M5475FFE.dtb \ + M5475GFE.dtb +dtb-$(CONFIG_TARGET_M5485EVB) += M5485AFE.dtb \ + M5485BFE.dtb \ + M5485CFE.dtb \ + M5485DFE.dtb \ + M5485EFE.dtb \ + M5485FFE.dtb \ + M5485GFE.dtb \ + M5485HFE.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/m68k/dts/amcore.dts b/arch/m68k/dts/amcore.dts new file mode 100644 index 0000000000..c21fb8ff79 --- /dev/null +++ b/arch/m68k/dts/amcore.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5307.dtsi" + +/ { + model = "Sysam AMCORE"; + compatible = "sysam,AMCORE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/astro_mcf5373l.dts b/arch/m68k/dts/astro_mcf5373l.dts new file mode 100644 index 0000000000..1b1a46ac2d --- /dev/null +++ b/arch/m68k/dts/astro_mcf5373l.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf537x.dtsi" + +/ { + model = "Astro mcf5373l"; + compatible = "astro,mcf5373l"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/cobra5272.dts b/arch/m68k/dts/cobra5272.dts new file mode 100644 index 0000000000..f3b74975de --- /dev/null +++ b/arch/m68k/dts/cobra5272.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5272.dtsi" + +/ { + model = "Cobra 5272"; + compatible = "cobra,M5272"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/eb_cpu5282.dts b/arch/m68k/dts/eb_cpu5282.dts new file mode 100644 index 0000000000..4641e9cb56 --- /dev/null +++ b/arch/m68k/dts/eb_cpu5282.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5282.dtsi" + +/ { + model = "BuS eb_cpuM5282"; + compatible = "bus,eb_cpuM5282"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/eb_cpu5282_internal.dts b/arch/m68k/dts/eb_cpu5282_internal.dts new file mode 100644 index 0000000000..0acb7935f4 --- /dev/null +++ b/arch/m68k/dts/eb_cpu5282_internal.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5282.dtsi" + +/ { + model = "BuS eb_cpu5282_internals"; + compatible = "bus,eb_cpu5282_internals"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi new file mode 100644 index 0000000000..558d8bf41a --- /dev/null +++ b/arch/m68k/dts/mcf5208.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5208"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi new file mode 100644 index 0000000000..8c95edddb6 --- /dev/null +++ b/arch/m68k/dts/mcf5227x.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5227x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi new file mode 100644 index 0000000000..9e79d472ec --- /dev/null +++ b/arch/m68k/dts/mcf523x.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf523x"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5249.dtsi b/arch/m68k/dts/mcf5249.dtsi new file mode 100644 index 0000000000..248b3dc68b --- /dev/null +++ b/arch/m68k/dts/mcf5249.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5249"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@1c0 { + compatible = "fsl,mcf-uart"; + reg = <0x1c0 0x40>; + status = "disabled"; + }; + + uart1: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5253.dtsi b/arch/m68k/dts/mcf5253.dtsi new file mode 100644 index 0000000000..3bde2d6202 --- /dev/null +++ b/arch/m68k/dts/mcf5253.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5253"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@1c0 { + compatible = "fsl,mcf-uart"; + reg = <0x1c0 0x40>; + status = "disabled"; + }; + + uart1: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart3: uart@c00 { + compatible = "fsl,mcf-uart"; + reg = <0xc00 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi new file mode 100644 index 0000000000..29355528d0 --- /dev/null +++ b/arch/m68k/dts/mcf5271.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5271"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5272.dtsi b/arch/m68k/dts/mcf5272.dtsi new file mode 100644 index 0000000000..a56117728b --- /dev/null +++ b/arch/m68k/dts/mcf5272.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5272"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@100 { + compatible = "fsl,mcf-uart"; + reg = <0x100 0x40>; + status = "disabled"; + }; + + uart1: uart@140 { + compatible = "fsl,mcf-uart"; + reg = <0x140 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi new file mode 100644 index 0000000000..b375609d4a --- /dev/null +++ b/arch/m68k/dts/mcf5275.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5275"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi new file mode 100644 index 0000000000..3ad1be7bb5 --- /dev/null +++ b/arch/m68k/dts/mcf5282.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5282"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi new file mode 100644 index 0000000000..0891e4dfd5 --- /dev/null +++ b/arch/m68k/dts/mcf5301x.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5301x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5307.dtsi b/arch/m68k/dts/mcf5307.dtsi new file mode 100644 index 0000000000..e199cf9991 --- /dev/null +++ b/arch/m68k/dts/mcf5307.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5307"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* MBAR */ + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@1c0 { + compatible = "fsl,mcf-uart"; + reg = <0x1c0 0x40>; + status = "disabled"; + }; + + uart1: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi new file mode 100644 index 0000000000..aeaa6430af --- /dev/null +++ b/arch/m68k/dts/mcf5329.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5329"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi new file mode 100644 index 0000000000..aeaa6430af --- /dev/null +++ b/arch/m68k/dts/mcf537x.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5329"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi new file mode 100644 index 0000000000..71b392adc3 --- /dev/null +++ b/arch/m68k/dts/mcf5441x.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5441x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + uart3: uart@fc06c000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc06c000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + + dspi1: dspi@fc03c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc03c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + + dspi2: dspi@ec038000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xec038000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + + dspi3: dspi@ec03c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xec03c00 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi new file mode 100644 index 0000000000..ccbee29a6c --- /dev/null +++ b/arch/m68k/dts/mcf5445x.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf5445x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf54xx.dtsi b/arch/m68k/dts/mcf54xx.dtsi new file mode 100644 index 0000000000..537bb424f3 --- /dev/null +++ b/arch/m68k/dts/mcf54xx.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/ { + compatible = "fsl,mcf54x5"; + + aliases { + /* TO DO, clarify on serial, this SoC seems to have SPC and + * no UARTS. + */ + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x10000>; + reg = <0x80000000 0x10000>; + + dspi0: dspi@8a00 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8a00 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts new file mode 100644 index 0000000000..fd8ce4fa35 --- /dev/null +++ b/arch/m68k/dts/stmark2.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Sysam stmark2"; + compatible = "sysam,stmark2"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + spi-mode = <3>; + status = "okay"; + + flash: is25lp128@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <60000000>; + reg = <1>; + }; +}; diff --git a/arch/m68k/include/asm/coldfire/dspi.h b/arch/m68k/include/asm/coldfire/dspi.h index afd5c79f35..ddd8f33805 100644 --- a/arch/m68k/include/asm/coldfire/dspi.h +++ b/arch/m68k/include/asm/coldfire/dspi.h @@ -138,4 +138,8 @@ typedef struct dspi { /* Bit definitions and macros for DRFDR group */ #define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF)) +/* Architecture-related operations */ +void dspi_chip_select(int cs); +void dspi_chip_unselect(int cs); + #endif /* __DSPI_H__ */ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9cf8e9800d..5cb9bdf2ee 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -84,13 +84,13 @@ config ARCH_MTMIPS select DM_SERIAL imply DM_SPI imply DM_SPI_FLASH - select ARCH_MISC_INIT select MIPS_TUNE_24KC select OF_CONTROL select ROM_EXCEPTION_VECTORS select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_LITTLE_ENDIAN + select SYS_MALLOC_CLEAR_ON_INIT select SYSRESET config ARCH_JZ47XX diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c index fcd0484a6d..b0a6397d68 100644 --- a/arch/mips/mach-mtmips/cpu.c +++ b/arch/mips/mach-mtmips/cpu.c @@ -68,18 +68,3 @@ int print_cpuinfo(void) return 0; } - -int arch_misc_init(void) -{ - /* - * It has been noticed, that sometimes the d-cache is not in a - * "clean-state" when U-Boot is running on MT7688. This was - * detected when using the ethernet driver (which uses d-cache) - * and a TFTP command does not complete. Flushing the complete - * d-cache (again?) here seems to fix this issue. - */ - flush_dcache_range(gd->bd->bi_memstart, - gd->bd->bi_memstart + gd->ram_size - 1); - - return 0; -} diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 0057f195b3..aebf168a89 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -352,7 +352,6 @@ config TARGET_T2080QDS select PHYS_64BIT select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE select FSL_DDR_INTERACTIVE - imply CMD_SATA config TARGET_T2080RDB bool "Support T2080RDB" @@ -361,6 +360,7 @@ config TARGET_T2080RDB select SUPPORT_SPL select PHYS_64BIT imply CMD_SATA + imply FSL_SATA imply PANIC_HANG config TARGET_T2081QDS @@ -1081,10 +1081,8 @@ config ARCH_T2080 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 select FSL_IFC - imply CMD_SATA imply CMD_NAND imply CMD_REGINFO - imply FSL_SATA config ARCH_T2081 bool diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index db65ea5725..d2bebb08b6 100644 --- a/arch/powerpc/dts/t2080.dtsi +++ b/arch/powerpc/dts/t2080.dtsi @@ -58,5 +58,50 @@ device_type = "open-pic"; clock-frequency = <0x0>; }; + + esdhc: esdhc@114000 { + compatible = "fsl,esdhc"; + reg = <0x114000 0x1000>; + interrupts = <48 2 0 0>; + clock-frequency = <0>; + sdhci,auto-cmd12; + bus-width = <4>; + voltage-ranges = <1800 1800 3300 3300>; + }; + + usb0: usb@210000 { + compatible = "fsl-usb2-mph"; + reg = <0x210000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <44 0x2 0 0>; + phy_type = "utmi"; + }; + + usb1: usb@211000 { + compatible = "fsl-usb2-dr"; + reg = <0x211000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <45 0x2 0 0>; + dr_mode = "host"; + phy_type = "utmi"; + }; + + sata0: sata@220000 { + compatible = "fsl,pq-sata-v2"; + reg = <0x220000 0x1000>; + interrupts = <68 0x2 0 0>; + sata-number = <0x0>; + sata-fpdma = <0x0>; + }; + + sata1: sata@221000 { + compatible = "fsl,pq-sata-v2"; + reg = <0x221000 0x1000>; + interrupts = <69 0x2 0 0>; + sata-number = <0x0>; + sata-fpdma = <0x0>; + }; }; }; |