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-rw-r--r--arch/arm/Kconfig22
-rw-r--r--arch/arm/dts/Makefile4
-rw-r--r--arch/arm/dts/zynq-cse-qspi-single.dts4
-rw-r--r--arch/arm/dts/zynq-zc702.dts1
-rw-r--r--arch/arm/dts/zynqmp-a2197-g-revA.dts282
-rw-r--r--arch/arm/dts/zynqmp-a2197-m-revA.dts461
-rw-r--r--arch/arm/dts/zynqmp-a2197-p-revA.dts567
-rw-r--r--arch/arm/dts/zynqmp-a2197-revA.dts89
-rw-r--r--arch/arm/dts/zynqmp-clk.dtsi1
-rw-r--r--arch/arm/dts/zynqmp-mini-qspi.dts2
-rw-r--r--arch/arm/dts/zynqmp.dtsi44
-rw-r--r--arch/arm/mach-versal/Kconfig12
-rw-r--r--arch/arm/mach-versal/cpu.c84
-rw-r--r--arch/arm/mach-versal/include/mach/hardware.h23
-rw-r--r--arch/arm/mach-versal/include/mach/sys_proto.h61
-rw-r--r--arch/arm/mach-zynqmp/Makefile4
-rw-r--r--arch/arm/mach-zynqmp/cpu.c24
-rw-r--r--arch/arm/mach-zynqmp/include/mach/sys_proto.h24
-rw-r--r--arch/arm/mach-zynqmp/pmu_ipc.c112
-rw-r--r--arch/microblaze/Kconfig8
-rw-r--r--arch/microblaze/include/asm/config.h4
-rw-r--r--arch/microblaze/lib/bootm.c136
22 files changed, 1728 insertions, 241 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 384e382e24..c5027c1338 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -462,6 +462,22 @@ config TPL_USE_ARCH_MEMSET
Such implementation may be faster under some conditions
but may increase the binary size.
+config SET_STACK_SIZE
+ bool "Enable an option to set max stack size that can be used"
+ default y if ARCH_VERSAL || ARCH_ZYNQMP
+ help
+ This will enable an option to set max stack size that can be
+ used by u-boot.
+
+config STACK_SIZE
+ hex "Define max stack size that can be used by u-boot"
+ depends on SET_STACK_SIZE
+ default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
+ help
+ Defines Max stack size that can be used by u-boot so that the
+ initrd_high will be calculated as base stack pointer minus this
+ stack size.
+
config ARM64_SUPPORT_AARCH32
bool "ARM64 system support AArch32 execution state"
depends on ARM64
@@ -980,6 +996,7 @@ config ARCH_VERSAL
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
+ imply BOARD_LATE_INIT
config ARCH_VF610
bool "Freescale Vybrid"
@@ -1034,16 +1051,21 @@ config ARCH_ZYNQMP
select CLK
select DM
select DM_ETH if NET
+ select DM_MAILBOX
select DM_MMC if MMC
select DM_SERIAL
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
select DM_USB if USB
+ select FIRMWARE
select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
+ select SPL_DM_MAILBOX if SPL
+ select SPL_FIRMWARE if SPL
select SPL_SEPARATE_BSS if SPL
select SUPPORT_SPL
+ select ZYNQMP_IPI
imply BOARD_LATE_INIT
imply CMD_DM
imply FAT_WRITE
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 73d47f5ac4..727da1a280 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -247,6 +247,10 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
+ zynqmp-a2197-revA.dtb \
+ zynqmp-a2197-g-revA.dtb \
+ zynqmp-a2197-m-revA.dtb \
+ zynqmp-a2197-p-revA.dtb \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
diff --git a/arch/arm/dts/zynq-cse-qspi-single.dts b/arch/arm/dts/zynq-cse-qspi-single.dts
index 0d680dfc06..ac6982a74e 100644
--- a/arch/arm/dts/zynq-cse-qspi-single.dts
+++ b/arch/arm/dts/zynq-cse-qspi-single.dts
@@ -7,6 +7,10 @@
#include "zynq-cse-qspi.dtsi"
+/ {
+ model = "Zynq CSE QSPI SINGLE Board";
+};
+
&flash0 {
spi-rx-bus-width = <4>;
};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 54231cd580..d10695740f 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -16,6 +16,7 @@
serial0 = &uart1;
spi0 = &qspi;
mmc0 = &sdhci0;
+ usb0 = &usb0;
};
memory@0 {
diff --git a/arch/arm/dts/zynqmp-a2197-g-revA.dts b/arch/arm/dts/zynqmp-a2197-g-revA.dts
new file mode 100644
index 0000000000..c6072b5f42
--- /dev/null
+++ b/arch/arm/dts/zynqmp-a2197-g-revA.dts
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller on MGT
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Versal System Controller on a2197 MGT Char board RevA";
+ compatible = "xlnx,zynqmp-a2197-g-revA", "xlnx,zynqmp-a2197-revA",
+ "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ mmc0 = &sdhci0;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = <&eeprom>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio_bank = <0>;
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&gem0 { /* eth MDIO 76/77 */
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii";
+ is-internal-pcspma;
+ phy0: phy@0 { /* marwell m88e1512 */
+ reg = <0>;
+ reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
+/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
+ };
+/* phy-names = "...";
+ phys = <&lane0 PHY_TYPE_SGMII ... >
+ Note: lane0 sgmii/lane1 usb3 */
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "", "", "", "", "", /* 0 - 4 */
+ "", "", "", "", "", /* 5 - 9 */
+ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+ "", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "", "", "", "", "", /* 45 - 49 */
+ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
+ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
+ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
+ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
+ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
+ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
+ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
+ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
+ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
+ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
+ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
+ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
+ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
+ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
+ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ i2c-mux@74 { /* u94 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
+ };
+ i2c@1 { /* CM_I2C_SCL - Samtec */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ i2c@2 { /* PMBUS - AFX_PMBUS */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ tps544@d { /* u85 */
+ compatible = "ti,tps544b25";
+ reg = <0xd>;
+ };
+ tps544@10 { /* u73 */
+ compatible = "ti,tps544b25";
+ reg = <0x10>;
+ };
+ tps544@11 { /* u76 */
+ compatible = "ti,tps544b25";
+ reg = <0x11>;
+ };
+ tps544@12 { /* u77 */
+ compatible = "ti,tps544b25";
+ reg = <0x12>;
+ };
+ tps544@13 { /* u80 */
+ compatible = "ti,tps544b25";
+ reg = <0x13>;
+ };
+ tps544@14 { /* u81 */
+ compatible = "ti,tps544b25";
+ reg = <0x14>;
+ };
+ tps544@15 { /* u83 */
+ compatible = "ti,tps544b25";
+ reg = <0x15>;
+ };
+ tps544@16 { /* u63 */
+ compatible = "ti,tps544b25";
+ reg = <0x16>;
+ };
+ tps544@17 { /* u66 */
+ compatible = "ti,tps544b25";
+ reg = <0x17>;
+ };
+ tps544@18 { /* u67 */
+ compatible = "ti,tps544b25";
+ reg = <0x18>;
+ };
+ tps544@19 { /* u69 */
+ compatible = "ti,tps544b25";
+ reg = <0x19>;
+ };
+ tps544@1d { /* u88 */
+ compatible = "ti,tps544b25";
+ reg = <0x1d>;
+ };
+ tps544@1e { /* u89 */
+ compatible = "ti,tps544b25";
+ reg = <0x1e>;
+ };
+ tps544@1f { /* u87 */
+ compatible = "ti,tps544b25";
+ reg = <0x1f>;
+ };
+ tps544@20 { /* u71 */
+ compatible = "ti,tps544b25";
+ reg = <0x20>;
+ };
+ ina226@40 { /* u74 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+ ina226@41 { /* u75 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ ina226@42 { /* u78 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <1000>;
+ };
+ ina226@44 { /* u82 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+ ina226@45 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */
+ compatible = "ti,tps53681"; /* FIXME no linux driver */
+ reg = <0xc0>;
+ };
+ };
+ i2c@3 { /* fmc1 via JA2G */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ eeprom_fmc1: eeprom@50 { /* on FMC */
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+ };
+ i2c@4 { /* fmc2 via JA3G */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ eeprom_fmc2: eeprom@50 { /* on FMC */
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+ };
+ i2c@5 { /* fmc3 via JA4G */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ eeprom_fmc3: eeprom@50 { /* on FMC */
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+ };
+ i2c@6 { /* ddr dimm */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ /* 7 unused */
+ };
+};
+
+&usb0 { /* USB0 MIO52-63 */
+ status = "okay";
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+};
diff --git a/arch/arm/dts/zynqmp-a2197-m-revA.dts b/arch/arm/dts/zynqmp-a2197-m-revA.dts
new file mode 100644
index 0000000000..e4b45eafe4
--- /dev/null
+++ b/arch/arm/dts/zynqmp-a2197-m-revA.dts
@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Versal System Controller on a2197 Memory Char board RevA";
+ compatible = "xlnx,zynqmp-a2197-m-revA", "xlnx,zynqmp-a2197-revA",
+ "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = <&eeprom>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
+ };
+};
+
+&qspi {
+ status = "okay";
+ is-dual = <1>;
+ flash@0 {
+ compatible = "m25p80", "spi-flash"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio_bank = <0>; /* FIXME tap delay */
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 { /* uart1 MIO40-41 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&sdhci1 { /* sd1 MIO45-51 cd in place */
+ status = "disable";
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio_bank = <1>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
+ phy0: phy@0 { /* marwell m88e1512 - SGMII */
+ reg = <0>;
+/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
+ };
+/* phy-names = "...";
+ phys = <&lane0 PHY_TYPE_SGMII ... >
+ Note: lane0 sgmii/lane1 usb3 */
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
+ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
+ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
+ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
+ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
+ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", "", "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ i2c-mux@74 { /* u46 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+ i2c@0 { /* PMBUS must be enabled via SW21 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ reg_vcc1v2_lp4: tps544@15 { /* u97 */
+ compatible = "ti,tps544b25";
+ reg = <0x15>;
+ };
+ reg_vcc1v1_lp4: tps544@16 { /* u95 */
+ compatible = "ti,tps544b25";
+ reg = <0x16>;
+ };
+ reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
+ compatible = "ti,tps544b25";
+ reg = <0x17>;
+ };
+ /* UTIL_PMBUS connection */
+ reg_vcc1v8: tps544@13 { /* u92 */
+ compatible = "ti,tps544b25";
+ reg = <0x13>;
+ };
+ reg_vcc3v3: tps544@14 { /* u93 */
+ compatible = "ti,tps544b25";
+ reg = <0x14>;
+ };
+ reg_vcc5v0: tps544@1e { /* u94 */
+ compatible = "ti,tps544b25";
+ reg = <0x1e>;
+ };
+ };
+ i2c@1 { /* PMBUS_INA226 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ vcc_aux: ina226@42 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc_ram: ina226@43 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v1_lp4: ina226@46 { /* u96 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v2_lp4: ina226@47 { /* u98 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ vdd1_1v8_lp4: ina226@48 { /* u100 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vcc0v6_lp4: ina226@49 { /* u101 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* PMBUS1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ reg_vccint: tps53681@c0 { /* u69 */
+ compatible = "ti,tps53681"; /* FIXME no linux driver */
+ reg = <0xc0>;
+ };
+ reg_vcc_pmc: tps544@7 { /* u80 */
+ compatible = "ti,tps544b25";
+ reg = <0x7>;
+ };
+ reg_vcc_ram: tps544@8 { /* u82 */
+ compatible = "ti,tps544b25";
+ reg = <0x8>;
+ };
+ reg_vcc_pslp: tps544@9 { /* u83 */
+ compatible = "ti,tps544b25";
+ reg = <0x9>;
+ };
+ reg_vcc_psfp: tps544@a { /* u84 */
+ compatible = "ti,tps544b25";
+ reg = <0xa>;
+ };
+ reg_vccaux: tps544@d { /* u85 */
+ compatible = "ti,tps544b25";
+ reg = <0xd>;
+ };
+ reg_vccaux_pmc: tps544@e { /* u87 */
+ compatible = "ti,tps544b25";
+ reg = <0xe>;
+ };
+ reg_vcco_500: tps544@f { /* u88 */
+ compatible = "ti,tps544b25";
+ reg = <0xf>;
+ };
+ reg_vcco_501: tps544@10 { /* u89 */
+ compatible = "ti,tps544b25";
+ reg = <0x10>;
+ };
+ reg_vcco_502: tps544@11 { /* u90 */
+ compatible = "ti,tps544b25";
+ reg = <0x11>;
+ };
+ reg_vcco_503: tps544@12 { /* u91 */
+ compatible = "ti,tps544b25";
+ reg = <0x12>;
+ };
+ };
+ i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reg = <3>; */
+ };
+ i2c@4 { /* LP_I2C_SM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* connected to U20G */
+ };
+ /* 5-7 unused */
+ };
+};
+
+/* TODO sysctrl via J239 */
+/* TODO samtec J212G/H via J242 */
+/* TODO teensy via U30 PCA9543A bus 1 */
+&i2c1 { /* i2c1 MIO 36-37 */
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Must be enabled via J242 */
+ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
+ dc_i2c: i2c@0 { /* DC_I2C */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ si570_ref_clk: clock-generator@5d { /* u26 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different */
+ clock-frequency = <33333333>;
+ clock-output-names = "REF_CLK"; /* FIXME */
+ };
+ /* Connection via Samtec U20D */
+ /* Use for storing information about X-PRC card */
+ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ /* Use for setting up certain features on X-PRC card */
+ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr_sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr_sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr_sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr_sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ };
+ i2c@1 { /* UTIL_PMBUS - FIXME incorrect schematics */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reg = <1>; */
+ };
+ i2c@2 { /* C0_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_c0_lp4: clock-generator@5d { /* u10 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C0_LP4_SI570_CLK";
+ };
+ };
+ i2c@3 { /* C1_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_c1_lp4: clock-generator@5d { /* u10 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C1_LP4_SI570_CLK";
+ };
+ };
+ i2c@4 { /* C2_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si570_c2_lp4: clock-generator@5d { /* u10 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C2_LP4_SI570_CLK";
+ };
+ };
+ i2c@5 { /* C3_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ si570_c3_lp4: clock-generator@5d { /* u15 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C3_LP4_SI570_CLK";
+ };
+ };
+ i2c@6 { /* HSDP_SI570 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ si570_hsdp: clock-generator@5d { /* u19 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "HSDP_SI570";
+ };
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ /* dr_mode = "peripheral"; */
+ maximum-speed = "high-speed";
+};
+
+&usb1 {
+ status = "disabled"; /* not at mem board */
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_1 {
+ /delete-property/ phy-names ;
+ /delete-property/ phys ;
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk ;
+ snps,dis_u3_susphy_quirk ;
+ status = "disabled";
+};
diff --git a/arch/arm/dts/zynqmp-a2197-p-revA.dts b/arch/arm/dts/zynqmp-a2197-p-revA.dts
new file mode 100644
index 0000000000..322b36e391
--- /dev/null
+++ b/arch/arm/dts/zynqmp-a2197-p-revA.dts
@@ -0,0 +1,567 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */
+ compatible = "xlnx,zynqmp-a2197-p-revA", "xlnx,zynqmp-a2197-revA",
+ "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = <&eeprom>;
+ /* xlnx,fmc-eeprom = FIXME */
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio_bank = <0>;
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 { /* uart1 MIO40-41 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&sdhci1 { /* sd1 MIO45-51 cd in place */
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio_bank = <1>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ is-internal-pcspma;
+ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "", "", "", "", "", /* 0 - 4 */
+ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
+ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+ "", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
+ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
+ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
+ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
+ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
+ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
+ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
+ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
+ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
+ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
+ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
+ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
+ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
+ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
+ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
+ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
+ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
+ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c@0 { /* PMBUS1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J98 */
+ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x7>;
+ regulator-name = "reg_vcc_fmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2600000>;
+ /* enable-gpio = <&gpio0 23 0x4>; optional */
+ };
+ reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x8>;
+ };
+ reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x9>;
+ };
+ reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0xa>;
+ };
+ reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */
+ compatible = "ti,tps53681"; /* FIXME no linux driver */
+ reg = <0xc0>;
+ /* vccint, vcc_io_soc */
+ };
+ };
+ i2c@1 { /* PMBUS1_INA226 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts comming to SC */
+ vcc_fmc: ina226@42 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc_ram: ina226@43 { /* u82 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pslp: ina226@44 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ vcc_psfp: ina226@45 { /* u87 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* PMBUS2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* On connector J104 */
+ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0xd>;
+ };
+ reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0xe>;
+ };
+ reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0xf>;
+ };
+ reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x10>;
+ };
+ reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x11>;
+ };
+ reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x12>;
+ };
+ reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x13>;
+ };
+ reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x14>;
+ };
+ reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x15>;
+ };
+ reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x16>;
+ };
+ reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x17>;
+ };
+ reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x19>;
+ };
+ reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1a>;
+ };
+ reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1b>;
+ };
+ reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1c>;
+ };
+ reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1d>;
+ };
+ reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1e>;
+ };
+ reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1f>;
+ };
+ };
+ i2c@3 { /* PMBUS2_INA226 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u89 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccaux_fmc: ina226@41 { /* u91 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcco_500: ina226@42 { /* u92 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcco_501: ina226@43 { /* u94 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcco_502: ina226@44 { /* u96 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ vcco_503: ina226@45 { /* u98 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ vcc_1v8: ina226@46 { /* u100 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ vcc_3v3: ina226@47 { /* u103 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ vcc_1v2_ddr4: ina226@48 { /* u105 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <1000>;
+ };
+ vcc1v1_lp4: ina226@49 { /* u107 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ vadj_fmc: ina226@4a { /* u110 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ mgtyavcc: ina226@4b { /* u112 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <1000>;
+ };
+ mgtyavtt: ina226@4c { /* u113 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <1000>;
+ };
+ mgtyvccaux: ina226@4d { /* u116 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ vcc_bat: ina226@4e { /* u12 */
+ compatible = "ti,ina226";
+ reg = <0x4e>;
+ shunt-resistor = <10000000>; /* 10 ohm */
+ };
+ };
+ i2c@4 { /* LP_I2C_SM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* connected to J212G */
+ /* zynqmp sm alert or samtec J212H */
+ };
+ /* 5-7 unused */
+ };
+};
+
+&i2c1 { /* i2c1 MIO 36-37 */
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Must be enabled via J242 */
+ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ dc_i2c: i2c@0 { /* DC_I2C */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u34 - m24128 16kB */
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x54>;
+ };
+ si570_ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* 570JAC000900DG */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different */
+ clock-frequency = <33333333>;
+ clock-output-names = "REF_CLK"; /* FIXME */
+ };
+ /* Connection via Samtec J212D */
+ /* Use for storing information about X-PRC card */
+ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ /* Use for setting up certain features on X-PRC card */
+ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr_sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr_sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr_sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr_sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ };
+ i2c@1 { /* FMCP1_IIC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ i2c@2 { /* FMCP2_IIC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* FIXME connection to Samtec J53C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ i2c@3 { /* DDR4_DIMM1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_ddr_dimm1: clock-generator@60 { /* u2 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>; /* 570BAB000299DG */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "REF_CLK"; /* FIXME */
+ };
+ /* 0x50 SPD? */
+ };
+ i2c@4 { /* DDR4_DIMM2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si570_ddr_dimm2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>; /* 570BAB000299DG */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "REF_CLK"; /* FIXME */
+ };
+ /* 0x50 SPD? */
+ };
+ i2c@5 { /* LPDDR4_SI570_CLK */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ si570_lpddr4: clock-generator@60 { /* u4 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>; /* 570BAB000299DG */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "LPDDR4_SI570_CLK";
+ };
+ };
+ i2c@6 { /* HSDP_SI570 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ si570_hsdp: clock-generator@5d { /* u5 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* 570JAC000900DG */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "HSDP_SI570";
+ };
+ };
+ i2c@7 { /* PCIE_CLK */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
+ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */
+ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
+ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */
+ #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
+ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
+ reg = <0xd8>;
+ /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
+ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
+
+ };
+
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ maximum-speed = "super-speed";
+};
+
+&usb1 {
+ status = "okay";
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_1 {
+ /delete-property/ phy-names ;
+ /delete-property/ phys ;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk ;
+ snps,dis_u3_susphy_quirk ;
+ status = "okay";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts b/arch/arm/dts/zynqmp-a2197-revA.dts
new file mode 100644
index 0000000000..3153138542
--- /dev/null
+++ b/arch/arm/dts/zynqmp-a2197-revA.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Versal System Controller on a2197 board RevA";
+ compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ clock-frequency = <400000>;
+ i2c-mux@74 { /* this cover MGT board */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ u-boot,dm-pre-reloc;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */
+ compatible = "atmel,24c32";
+ u-boot,dm-pre-reloc;
+ reg = <0x50>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ clock-frequency = <400000>;
+ i2c-mux@74 { /* This cover processor board */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ u-boot,dm-pre-reloc;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */
+ compatible = "atmel,24c32";
+ u-boot,dm-pre-reloc;
+ reg = <0x50>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi
index a795efdc15..c70f85a430 100644
--- a/arch/arm/dts/zynqmp-clk.dtsi
+++ b/arch/arm/dts/zynqmp-clk.dtsi
@@ -38,6 +38,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
+ u-boot,dm-pre-reloc;
};
clk600: clk600 {
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index 1716d5179d..e4ba5ae9b6 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -64,7 +64,7 @@
&qspi {
status = "okay";
flash0: flash@0 {
- compatible = "n25q512a11", "spi-flash";
+ compatible = "n25q512a11", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index dfb6ebc64c..8e35171dd0 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -96,6 +96,29 @@
};
};
+ zynqmp_ipi {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <&gic>;
+ interrupts = <0 35 4>;
+ xlnx,ipi-id = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipi_mailbox_pmu1: mailbox@ff990400 {
+ u-boot,dm-pre-reloc;
+ reg = <0x0 0xff9905c0 0x0 0x20>,
+ <0x0 0xff9905e0 0x0 0x20>,
+ <0x0 0xff990e80 0x0 0x20>,
+ <0x0 0xff990ea0 0x0 0x20>;
+ reg-names = "local_request_region" , "local_response_region",
+ "remote_request_region", "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <4>;
+ };
+ };
+
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
@@ -116,11 +139,22 @@
method = "smc";
};
- pmufw: firmware {
- compatible = "xlnx,zynqmp-pm";
- method = "smc";
- interrupt-parent = <&gic>;
- interrupts = <0 35 4>;
+ firmware {
+ zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ #power-domain-cells = <0x1>;
+ u-boot,dm-pre-reloc;
+
+ zynqmp_power: zynqmp-power {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-power";
+ interrupt-parent = <&gic>;
+ interrupts = <0 35 4>;
+ mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
};
timer {
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index 26d1756371..a08e5ae414 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@@ -36,11 +36,6 @@ config COUNTER_FREQUENCY
config ZYNQ_SDHCI_MAX_FREQ
default 200000000
-config VERSAL_OF_BOARD_DTB_ADDR
- hex
- default 0x1000
- depends on OF_BOARD
-
config IOU_SWITCH_DIVISOR0
hex "IOU switch divisor0"
default 0x20
@@ -54,4 +49,11 @@ config SYS_MEM_RSVD_FOR_MMU
MMU table than the one which will be allocated during
relocation.
+config DEFINE_TCM_OCM_MMAP
+ bool "Define TCM and OCM memory in MMU Table"
+ default y if MP
+ help
+ This option if enabled defines the TCM and OCM memory and its
+ memory attributes in MMU table entry.
+
endif
diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c
index 70c1908ec4..49f1e51c8e 100644
--- a/arch/arm/mach-versal/cpu.c
+++ b/arch/arm/mach-versal/cpu.c
@@ -12,14 +12,21 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct mm_region versal_mem_map[] = {
+#define VERSAL_MEM_MAP_USED 5
+
+#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+#define TCM_MAP 1
+#else
+#define TCM_MAP 0
+#endif
+
+/* +1 is end of list which needs to be empty */
+#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
+
+static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
{
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x70000000UL,
@@ -34,12 +41,6 @@ static struct mm_region versal_mem_map[] = {
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
- .virt = 0xffe00000UL,
- .phys = 0xffe00000UL,
- .size = 0x00200000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
.virt = 0x400000000UL,
.phys = 0x400000000UL,
.size = 0x200000000UL,
@@ -59,12 +60,36 @@ static struct mm_region versal_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
}
};
+void mem_map_fill(void)
+{
+ int banks = VERSAL_MEM_MAP_USED;
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+ versal_mem_map[banks].virt = 0xffe00000UL;
+ versal_mem_map[banks].phys = 0xffe00000UL;
+ versal_mem_map[banks].size = 0x00200000UL;
+ versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ banks = banks + 1;
+#endif
+
+ for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /* Zero size means no more DDR that's this is end */
+ if (!gd->bd->bi_dram[i].size)
+ break;
+
+ versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
+ versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
+ versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
+ versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ banks = banks + 1;
+ }
+}
+
struct mm_region *mem_map = versal_mem_map;
u64 get_page_table_size(void)
@@ -83,16 +108,27 @@ int reserve_mmu(void)
}
#endif
-#if defined(CONFIG_OF_BOARD)
-void *board_fdt_blob_setup(void)
+int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+ u32 arg3, u32 *ret_payload)
{
- static void *fw_dtb = (void *)CONFIG_VERSAL_OF_BOARD_DTB_ADDR;
+ struct pt_regs regs;
+
+ if (current_el() == 3)
+ return 0;
- if (fdt_magic(fw_dtb) != FDT_MAGIC) {
- printf("DTB is not passed via %llx\n", (u64)fw_dtb);
- return NULL;
+ regs.regs[0] = PM_SIP_SVC | api_id;
+ regs.regs[1] = ((u64)arg1 << 32) | arg0;
+ regs.regs[2] = ((u64)arg3 << 32) | arg2;
+
+ smc_call(&regs);
+
+ if (ret_payload) {
+ ret_payload[0] = (u32)regs.regs[0];
+ ret_payload[1] = upper_32_bits(regs.regs[0]);
+ ret_payload[2] = (u32)regs.regs[1];
+ ret_payload[3] = upper_32_bits(regs.regs[1]);
+ ret_payload[4] = (u32)regs.regs[2];
}
- return fw_dtb;
+ return regs.regs[0];
}
-#endif
diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h
index 23fbc3d8f5..e26beab2e9 100644
--- a/arch/arm/mach-versal/include/mach/hardware.h
+++ b/arch/arm/mach-versal/include/mach/hardware.h
@@ -51,3 +51,26 @@ struct rpu_regs {
};
#define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR)
+
+#define VERSAL_CRP_BASEADDR 0xF1260000
+
+struct crp_regs {
+ u32 reserved0[128];
+ u32 boot_mode_usr;
+};
+
+#define crp_base ((struct crp_regs *)VERSAL_CRP_BASEADDR)
+
+/* Bootmode setting values */
+#define BOOT_MODES_MASK 0x0000000F
+#define QSPI_MODE_24BIT 0x00000001
+#define QSPI_MODE_32BIT 0x00000002
+#define SD_MODE 0x00000003 /* sd 0 */
+#define SD_MODE1 0x00000005 /* sd 1 */
+#define EMMC_MODE 0x00000006
+#define USB_MODE 0x00000007
+#define OSPI_MODE 0x00000008
+#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
+#define JTAG_MODE 0x00000000
+#define BOOT_MODE_USE_ALT 0x100
+#define BOOT_MODE_ALT_SHIFT 12
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h
index 1dc7bf6656..2f5ad02bf4 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -8,4 +8,65 @@ enum {
TCM_SPLIT,
};
+enum pm_api_id {
+ PM_GET_API_VERSION = 1,
+ PM_SET_CONFIGURATION,
+ PM_GET_NODE_STATUS,
+ PM_GET_OPERATING_CHARACTERISTIC,
+ PM_REGISTER_NOTIFIER,
+ PM_REQUEST_SUSPEND,
+ PM_SELF_SUSPEND,
+ PM_FORCE_POWERDOWN,
+ PM_ABORT_SUSPEND,
+ PM_REQUEST_WAKEUP,
+ PM_SET_WAKEUP_SOURCE,
+ PM_SYSTEM_SHUTDOWN,
+ PM_REQUEST_NODE,
+ PM_RELEASE_NODE,
+ PM_SET_REQUIREMENT,
+ PM_SET_MAX_LATENCY,
+ PM_RESET_ASSERT,
+ PM_RESET_GET_STATUS,
+ PM_MMIO_WRITE,
+ PM_MMIO_READ,
+ PM_PM_INIT_FINALIZE,
+ PM_FPGA_LOAD,
+ PM_FPGA_GET_STATUS,
+ PM_GET_CHIPID,
+ PM_SECURE_SHA = 26,
+ PM_SECURE_RSA,
+ PM_PINCTRL_REQUEST,
+ PM_PINCTRL_RELEASE,
+ PM_PINCTRL_GET_FUNCTION,
+ PM_PINCTRL_SET_FUNCTION,
+ PM_PINCTRL_CONFIG_PARAM_GET,
+ PM_PINCTRL_CONFIG_PARAM_SET,
+ PM_IOCTL,
+ PM_QUERY_DATA,
+ PM_CLOCK_ENABLE,
+ PM_CLOCK_DISABLE,
+ PM_CLOCK_GETSTATE,
+ PM_CLOCK_SETDIVIDER,
+ PM_CLOCK_GETDIVIDER,
+ PM_CLOCK_SETRATE,
+ PM_CLOCK_GETRATE,
+ PM_CLOCK_SETPARENT,
+ PM_CLOCK_GETPARENT,
+ PM_SECURE_IMAGE,
+ PM_FPGA_READ = 46,
+ PM_SECURE_AES,
+ PM_CLOCK_PLL_GETPARAM = 49,
+ PM_REGISTER_ACCESS = 52,
+ PM_EFUSE_ACCESS,
+ PM_FEATURE_CHECK = 63,
+ PM_API_MAX,
+};
+
+#define PM_SIP_SVC 0xC2000000
+#define PAYLOAD_ARG_CNT 4U
+
void tcm_init(u8 mode);
+void mem_map_fill(void);
+
+int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+ u32 arg3, u32 *ret_payload);
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index f3765e45b1..8a3b074724 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -8,7 +8,3 @@ obj-y += cpu.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
-
-ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
-obj-$(CONFIG_SPL_BUILD) += pmu_ipc.o
-endif
diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c
index 5ef1a52862..bb21cbcadf 100644
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@@ -9,6 +9,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
+#include <zynqmp_firmware.h>
#define ZYNQ_SILICON_VER_MASK 0xF000
#define ZYNQ_SILICON_VER_SHIFT 12
@@ -179,29 +180,6 @@ int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
return regs.regs[0];
}
-unsigned int __maybe_unused zynqmp_pmufw_version(void)
-{
- int ret;
- u32 ret_payload[PAYLOAD_ARG_CNT];
- static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID;
-
- /*
- * Get PMU version only once and later
- * just return stored values instead of
- * asking PMUFW again.
- */
- if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) {
- ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
- ret_payload);
- pm_api_version = ret_payload[1];
-
- if (ret)
- panic("PMUFW is not found - Please load it!\n");
- }
-
- return pm_api_version;
-}
-
static int zynqmp_mmio_rawwrite(const u32 address,
const u32 mask,
const u32 value)
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 915badc6fb..69e729fb76 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -10,7 +10,6 @@
#define PAYLOAD_ARG_CNT 5
#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
-#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D
#define KEY_PTR_LEN 32
#define ZYNQMP_FPGA_BIT_AUTH_DDR 1
@@ -21,21 +20,6 @@
#define ZYNQMP_FPGA_AUTH_DDR 1
-#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001
-
-#define ZYNQMP_PM_VERSION_MAJOR 1
-#define ZYNQMP_PM_VERSION_MINOR 0
-#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
-#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
-
-#define ZYNQMP_PM_VERSION \
- ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
- ZYNQMP_PM_VERSION_MINOR)
-
-#define ZYNQMP_PM_VERSION_INVALID ~0
-
-#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
-
enum {
IDCODE,
VERSION,
@@ -54,12 +38,16 @@ enum {
TCM_SPLIT,
};
+struct zynqmp_ipi_msg {
+ size_t len;
+ u32 *buf;
+};
+
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
unsigned int zynqmp_get_silicon_version(void);
void handoff_setup(void);
-unsigned int zynqmp_pmufw_version(void);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
int zynqmp_mmio_read(const u32 address, u32 *value);
int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
@@ -72,6 +60,4 @@ int chip_id(unsigned char id);
void tcm_init(u8 mode);
#endif
-void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
-
#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-zynqmp/pmu_ipc.c b/arch/arm/mach-zynqmp/pmu_ipc.c
deleted file mode 100644
index d8858ea3ff..0000000000
--- a/arch/arm/mach-zynqmp/pmu_ipc.c
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Inter-Processor Communication with the Platform Management Unit (PMU)
- * firmware.
- *
- * (C) Copyright 2019 Luca Ceresoli
- * Luca Ceresoli <luca@lucaceresoli.net>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-
-/* IPI bitmasks, register base and register offsets */
-#define IPI_BIT_MASK_APU 0x00001
-#define IPI_BIT_MASK_PMU0 0x10000
-#define IPI_REG_BASE_APU 0xFF300000
-#define IPI_REG_BASE_PMU0 0xFF330000
-#define IPI_REG_OFFSET_TRIG 0x00
-#define IPI_REG_OFFSET_OBR 0x04
-
-/* IPI mailbox buffer offsets */
-#define IPI_BUF_BASE_APU 0xFF990400
-#define IPI_BUF_OFFSET_TARGET_PMU 0x1C0
-#define IPI_BUF_OFFSET_REQ 0x00
-#define IPI_BUF_OFFSET_RESP 0x20
-
-#define PMUFW_PAYLOAD_ARG_CNT 8
-
-/* PMUFW commands */
-#define PMUFW_CMD_SET_CONFIGURATION 2
-
-static void pmu_ipc_send_request(const u32 *req, size_t req_len)
-{
- u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
- IPI_BUF_OFFSET_TARGET_PMU +
- IPI_BUF_OFFSET_REQ);
- size_t i;
-
- for (i = 0; i < req_len; i++)
- writel(req[i], &mbx[i]);
-}
-
-static void pmu_ipc_read_response(unsigned int *value, size_t count)
-{
- u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
- IPI_BUF_OFFSET_TARGET_PMU +
- IPI_BUF_OFFSET_RESP);
- size_t i;
-
- for (i = 0; i < count; i++)
- value[i] = readl(&mbx[i]);
-}
-
-/**
- * Send request to PMU and get the response.
- *
- * @req: Request buffer. Byte 0 is the API ID, other bytes are optional
- * parameters.
- * @req_len: Request length in number of 32-bit words.
- * @res: Response buffer. Byte 0 is the error code, other bytes are
- * optional parameters. Optional, if @res_maxlen==0 the parameters
- * will not be read.
- * @res_maxlen: Space allocated for the response in number of 32-bit words.
- *
- * @return Error code returned by the PMU (i.e. the first word of the response)
- */
-static int pmu_ipc_request(const u32 *req, size_t req_len,
- u32 *res, size_t res_maxlen)
-{
- u32 status;
-
- if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
- res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
- return -EINVAL;
-
- pmu_ipc_send_request(req, req_len);
-
- /* Raise Inter-Processor Interrupt to PMU and wait for response */
- writel(IPI_BIT_MASK_PMU0, IPI_REG_BASE_APU + IPI_REG_OFFSET_TRIG);
- do {
- status = readl(IPI_REG_BASE_APU + IPI_REG_OFFSET_OBR);
- } while (status & IPI_BIT_MASK_PMU0);
-
- pmu_ipc_read_response(res, res_maxlen);
-
- return 0;
-}
-
-/**
- * Send a configuration object to the PMU firmware.
- *
- * @cfg_obj: Pointer to the configuration object
- * @size: Size of @cfg_obj in bytes
- */
-void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
-{
- const u32 request[] = {
- PMUFW_CMD_SET_CONFIGURATION,
- (u32)((u64)cfg_obj)
- };
- u32 response;
- int err;
-
- printf("Loading PMUFW cfg obj (%ld bytes)\n", size);
-
- err = pmu_ipc_request(request, ARRAY_SIZE(request), &response, 1);
- if (err)
- panic("Cannot load PMUFW configuration object (%d)\n", err);
- if (response != 0)
- panic("PMUFW returned 0x%08x status!\n", response);
-}
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 5cc68d63c4..5ce8261451 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -20,6 +20,14 @@ config TARGET_MICROBLAZE_GENERIC
endchoice
+config STACK_SIZE
+ hex "Define max stack size that can be used by u-boot"
+ default 0x200000
+ help
+ Defines Max stack size that can be used by u-boot so that the
+ initrd_high will be calculated as base stack pointer minus this
+ stack size.
+
source "board/xilinx/microblaze-generic/Kconfig"
config SPL_LDSCRIPT
diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h
index 45966eef91..1124272915 100644
--- a/arch/microblaze/include/asm/config.h
+++ b/arch/microblaze/include/asm/config.h
@@ -6,8 +6,12 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_LMB
+
#ifndef CONFIG_SPL_BUILD
#define CONFIG_NEEDS_MANUAL_RELOC
#endif
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
#endif
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index ec332944d8..11e534715d 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -15,71 +15,111 @@
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
-int do_bootm_linux(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("addik %0, r1, 0" : "=r"(ret) : );
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
{
- /* First parameter is mapped to $r5 for kernel boot args */
- void (*thekernel) (char *, ulong, ulong);
- char *commandline = env_get("bootargs");
- ulong rd_data_start, rd_data_end;
+ ulong sp, bank_end;
+ int bank;
/*
- * allow the PREP bootm subcommand, it is required for bootm to work
+ * Booting a (Linux) kernel image
+ *
+ * Allocate space for command line and board info - the
+ * address should be as high as possible within the reach of
+ * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+ * memory, which means far enough below the current stack
+ * pointer.
*/
- if (flag & BOOTM_STATE_OS_PREP)
- return 0;
+ sp = get_sp();
+ debug("## Current stack ends at 0x%08lx ", sp);
- if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
- return 1;
-
- int ret;
+ /* adjust sp by 4K to be safe */
+ sp -= 4096;
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ if (sp < gd->bd->bi_dram[bank].start)
+ continue;
+ bank_end = gd->bd->bi_dram[bank].start +
+ gd->bd->bi_dram[bank].size;
+ if (sp >= bank_end)
+ continue;
+ lmb_reserve(lmb, sp, bank_end - sp);
+ break;
+ }
+}
- char *of_flat_tree = NULL;
-#if defined(CONFIG_OF_LIBFDT)
- /* did generic code already find a device tree? */
- if (images->ft_len)
- of_flat_tree = images->ft_addr;
-#endif
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+ void (*thekernel)(char *cmdline, ulong rd, ulong dt);
+ ulong dt = (ulong)images->ft_addr;
+ ulong rd_start = images->initrd_start;
+ ulong cmdline = images->cmdline_start;
+ int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
thekernel = (void (*)(char *, ulong, ulong))images->ep;
- /* find ramdisk */
- ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_MICROBLAZE,
- &rd_data_start, &rd_data_end);
- if (ret)
- return 1;
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
- if (!of_flat_tree && argc > 1)
- of_flat_tree = (char *)simple_strtoul(argv[1], NULL, 16);
-
- /* fixup the initrd now that we know where it should be */
- if (images->rd_start && images->rd_end && of_flat_tree) {
- ret = fdt_initrd(of_flat_tree, images->rd_start,
- images->rd_end);
- if (ret)
- return 1;
- }
-
#ifdef DEBUG
printf("## Transferring control to Linux (at address 0x%08lx) ",
(ulong)thekernel);
- printf("ramdisk 0x%08lx, FDT 0x%08lx...\n",
- rd_data_start, (ulong) of_flat_tree);
+ printf("cmdline 0x%08lx, ramdisk 0x%08lx, FDT 0x%08lx...\n",
+ cmdline, rd_start, dt);
#endif
#ifdef XILINX_USE_DCACHE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
#endif
- /*
- * Linux Kernel Parameters (passing device tree):
- * r5: pointer to command line
- * r6: pointer to ramdisk
- * r7: pointer to the fdt, followed by the board info data
- */
- thekernel(commandline, rd_data_start, (ulong)of_flat_tree);
- /* does not return */
+ if (!fake) {
+ /*
+ * Linux Kernel Parameters (passing device tree):
+ * r5: pointer to command line
+ * r6: pointer to ramdisk
+ * r7: pointer to the fdt, followed by the board info data
+ */
+ thekernel((char *)cmdline, rd_start, dt);
+ /* does not return */
+ }
+}
+
+static void boot_prep_linux(bootm_headers_t *images)
+{
+ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ printf("using: FDT\n");
+ if (image_setup_linux(images)) {
+ printf("FDT creation failed! hanging...");
+ hang();
+ }
+ }
+}
+
+int do_bootm_linux(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ images->cmdline_start = (ulong)env_get("bootargs");
+
+ /* cmdline init is the part of 'prep' and nothing to do for 'bdt' */
+ if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+ return -1;
+
+ if (flag & BOOTM_STATE_OS_PREP) {
+ boot_prep_linux(images);
+ return 0;
+ }
+
+ if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+ boot_jump_linux(images, flag);
+ return 0;
+ }
+
+ boot_prep_linux(images);
+ boot_jump_linux(images, flag);
return 1;
}
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