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-rw-r--r--arch/arm/Kconfig11
-rw-r--r--arch/arm/cpu/armv8/start.S23
-rw-r--r--arch/arm/dts/zynqmp-e-a2197-00-revA.dts33
-rw-r--r--arch/arm/lib/crt0_64.S8
-rw-r--r--arch/arm/mach-versal/Kconfig3
-rw-r--r--arch/arm/mach-zynq/Kconfig3
-rw-r--r--arch/arm/mach-zynq/cpu.c6
-rw-r--r--arch/arm/mach-zynq/spl.c2
-rw-r--r--arch/arm/mach-zynqmp-r5/cpu.c11
-rw-r--r--arch/arm/mach-zynqmp/Kconfig3
-rw-r--r--arch/arm/mach-zynqmp/handoff.c2
-rw-r--r--arch/microblaze/include/asm/io.h22
12 files changed, 94 insertions, 33 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 68d6d1afd6..6a0227819b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,8 +16,8 @@ config POSITION_INDEPENDENT
help
U-Boot expects to be linked to a specific hard-coded address, and to
be loaded to and run from that address. This option lifts that
- restriction, thus allowing the code to be loaded to and executed
- from almost any address. This logic relies on the relocation
+ restriction, thus allowing the code to be loaded to and executed from
+ almost any 4K aligned address. This logic relies on the relocation
information that is embedded in the binary to support U-Boot
relocating itself to the top-of-RAM later during execution.
@@ -1155,7 +1155,8 @@ config ARCH_ZYNQMP
select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
- select SPL_DM_SPI if SPI
+ select SPL_DM if SPL
+ select SPL_DM_SPI if SPI && SPL_DM
select SPL_DM_SPI_FLASH if SPL_DM_SPI
select SPL_DM_MAILBOX if SPL
select SPL_FIRMWARE if SPL
@@ -2000,10 +2001,6 @@ source "board/tcl/sl50/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
-source "board/xilinx/Kconfig"
-source "board/xilinx/zynq/Kconfig"
-source "board/xilinx/zynqmp/Kconfig"
-source "board/xilinx/versal/Kconfig"
source "board/phytium/durian/Kconfig"
source "board/xen/xenguest_arm64/Kconfig"
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 002698b501..e5c2856cf5 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -59,6 +59,23 @@ reset:
save_boot_params_ret:
#if CONFIG_POSITION_INDEPENDENT
+ /* Verify that we're 4K aligned. */
+ adr x0, _start
+ ands x0, x0, #0xfff
+ b.eq 1f
+0:
+ /*
+ * FATAL, can't continue.
+ * U-Boot needs to be loaded at a 4K aligned address.
+ *
+ * We use ADRP and ADD to load some symbol addresses during startup.
+ * The ADD uses an absolute (non pc-relative) lo12 relocation
+ * thus requiring 4K alignment.
+ */
+ wfi
+ b 0b
+1:
+
/*
* Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
* executed at a different address than it was linked at.
@@ -67,8 +84,10 @@ pie_fixup:
adr x0, _start /* x0 <- Runtime value of _start */
ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
sub x9, x0, x1 /* x9 <- Run-vs-link offset */
- adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
- adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
+ adrp x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
+ add x2, x2, #:lo12:__rel_dyn_start
+ adrp x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
+ add x3, x3, #:lo12:__rel_dyn_end
pie_fix_loop:
ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
ldr x4, [x2], #8 /* x4 <- addend */
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index a8bbb14f6c..aae3c626f5 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -230,16 +230,16 @@
#io-channel-cells = <1>;
label = "ina226-vccint";
reg = <0x40>;
- shunt-resistor = <5000>; /* R440 */
- /* 0.78V @ 32A 1 of 6 Phases*/
+ shunt-resistor = <500>; /* R440 */
+ /* 0.80V @ 32A 1 of 6 Phases*/
};
vcc_soc: ina226@41 { /* u161 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-vcc-soc";
reg = <0x41>;
- shunt-resistor = <2000>; /* R1186 */
- /* 0.78V @ 18A */
+ shunt-resistor = <500>; /* R1702 */
+ /* 0.80V @ 18A */
};
vcc_pmc: ina226@42 { /* u163 */
compatible = "ti,ina226";
@@ -554,6 +554,31 @@
reg = <7>;
};
};
+ i2c-mux@75 { /* u214 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 { /* SFP0_IIC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* SFP0 */
+ };
+ i2c@1 { /* SFP1_IIC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* SFP1 */
+ };
+ i2c@2 { /* QSFP1_I2C */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* QSFP1 */
+ };
+ /* 3 - 7 unused */
+ };
};
&xilinx_ams {
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 04afa518ac..9d2319c0e8 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -73,7 +73,12 @@ ENTRY(_main)
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr x0, =(CONFIG_SPL_STACK)
#elif defined(CONFIG_INIT_SP_RELATIVE)
+#if CONFIG_POSITION_INDEPENDENT
+ adrp x0, __bss_start /* x0 <- Runtime &__bss_start */
+ add x0, x0, #:lo12:__bss_start
+#else
adr x0, __bss_start
+#endif
add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET
#else
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
@@ -102,7 +107,8 @@ ENTRY(_main)
adr lr, relocation_return
#if CONFIG_POSITION_INDEPENDENT
/* Add in link-vs-runtime offset */
- adr x0, _start /* x0 <- Runtime value of _start */
+ adrp x0, _start /* x0 <- Runtime value of _start */
+ add x0, x0, #:lo12:_start
ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */
sub x9, x9, x0 /* x9 <- Run-vs-link offset */
add lr, lr, x9
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index e1d66e8d32..ebd2da3887 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@@ -62,4 +62,7 @@ config VERSAL_NO_DDR
This option configures MMU with no DDR to avoid speculative
access to DDR memory where DDR is not present.
+source "board/xilinx/Kconfig"
+source "board/xilinx/versal/Kconfig"
+
endif
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 79f831e6df..e54310383b 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -70,4 +70,7 @@ config BOOT_INIT_FILE
config ZYNQ_SDHCI_MAX_FREQ
default 52000000
+source "board/xilinx/Kconfig"
+source "board/xilinx/zynq/Kconfig"
+
endif
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index 77b7cb1307..3befc12028 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -17,8 +17,7 @@
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA)
xilinx_desc fpga = {
.family = xilinx_zynq,
.iface = devcfg,
@@ -111,8 +110,7 @@ static int __maybe_unused cpu_desc_id(void)
#if defined(CONFIG_ARCH_EARLY_INIT_R)
int arch_early_init_r(void)
{
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+#if CONFIG_IS_ENABLED(FPGA)
int cpu_id = cpu_desc_id();
if (cpu_id < 0)
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 239ce3436a..cb8cfd2f35 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -34,7 +34,7 @@ void board_init_f(ulong dummy)
void spl_board_init(void)
{
preloader_console_init();
-#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA_SUPPORT)
+#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA)
arch_early_init_r();
#endif
board_init();
diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c
index b3402d7189..87c1d75f9f 100644
--- a/arch/arm/mach-zynqmp-r5/cpu.c
+++ b/arch/arm/mach-zynqmp-r5/cpu.c
@@ -11,11 +11,9 @@
DECLARE_GLOBAL_DATA_PTR;
struct mpu_region_config region_config[] = {
- { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
- O_I_WB_RD_WR_ALLOC, REGION_1GB },
- { 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO,
- O_I_WB_RD_WR_ALLOC, REGION_512MB },
- { 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO,
+ { 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
+ SHARED_WRITE_BUFFERED, REGION_4GB },
+ { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_1GB },
};
@@ -23,8 +21,7 @@ int arch_cpu_init(void)
{
gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
- setup_mpu_regions(region_config, sizeof(region_config) /
- sizeof(struct mpu_region_config));
+ setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
return 0;
}
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index d82a737a69..f1301f6661 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -171,4 +171,7 @@ config SD1_LSHFT_MODE
endchoice
+source "board/xilinx/Kconfig"
+source "board/xilinx/zynqmp/Kconfig"
+
endif
diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c
index 64e5320acc..7d7ab9da6e 100644
--- a/arch/arm/mach-zynqmp/handoff.c
+++ b/arch/arm/mach-zynqmp/handoff.c
@@ -65,7 +65,7 @@ struct xfsbl_atf_handoff_params {
struct xfsbl_partition partition[FSBL_MAX_PARTITIONS];
};
-#ifdef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_ATF
struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry,
uintptr_t bl33_entry,
uintptr_t fdt_addr)
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 8e6be0ae26..632bb236fb 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -50,14 +50,24 @@
#define outw(x, addr) ((void)writew(x, addr))
#define outl(x, addr) ((void)writel(x, addr))
-/* Some #definitions to keep strange Xilinx code happy */
-#define in_8(addr) readb(addr)
-#define in_be16(addr) readw(addr)
-#define in_be32(addr) readl(addr)
+#define out_arch(type, endian, addr, x) \
+ __raw_write##type(cpu_to_##endian(x), addr)
+#define in_arch(type, endian, addr) \
+ endian##_to_cpu(__raw_read##type(addr))
+
+#define out_le16(addr, x) out_arch(w, le16, addr, x)
+#define out_le32(addr, x) out_arch(l, le32, addr, x)
+
+#define in_le16(addr) in_arch(w, le16, addr)
+#define in_le32(addr) in_arch(l, le32, addr)
+
+#define in_8(addr) readb(addr)
+#define in_be16(addr) in_arch(w, be16, addr)
+#define in_be32(addr) in_arch(l, be32, addr)
#define out_8(addr, x) outb(x, addr)
-#define out_be16(addr, x) outw(x, addr)
-#define out_be32(addr, x) outl(x, addr)
+#define out_be16(addr, x) out_arch(w, be16, addr, x)
+#define out_be32(addr, x) out_arch(l, be32, addr, x)
#define inb_p(port) inb((port))
#define outb_p(val, port) outb((val), (port))
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