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-rw-r--r--arch/x86/cpu/acpi_gpe.c6
-rw-r--r--arch/x86/cpu/apollolake/spl.c12
-rw-r--r--arch/x86/cpu/u-boot-spl.lds12
-rw-r--r--arch/x86/dts/chromebook_coral.dts6
-rw-r--r--arch/x86/include/asm/intel_gnvs.h34
-rw-r--r--arch/x86/include/asm/zimage.h10
-rw-r--r--arch/x86/lib/spl.c2
-rw-r--r--arch/x86/lib/tpl.c7
-rw-r--r--arch/x86/lib/zimage.c33
9 files changed, 96 insertions, 26 deletions
diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c
index 83128c33c2..da01e71335 100644
--- a/arch/x86/cpu/acpi_gpe.c
+++ b/arch/x86/cpu/acpi_gpe.c
@@ -4,6 +4,8 @@
* Written by Simon Glass <sjg@chromium.org>
*/
+#define LOG_CATEGORY UCLASS_IRQ
+
#include <common.h>
#include <dm.h>
#include <irq.h>
@@ -102,8 +104,8 @@ static const struct udevice_id acpi_gpe_ids[] = {
{ }
};
-U_BOOT_DRIVER(acpi_gpe_drv) = {
- .name = "acpi_gpe",
+U_BOOT_DRIVER(intel_acpi_gpe) = {
+ .name = "intel_acpi_gpe",
.id = UCLASS_IRQ,
.of_match = acpi_gpe_ids,
.ops = &acpi_gpe_ops,
diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c
index 8991d5e648..f2d25734c6 100644
--- a/arch/x86/cpu/apollolake/spl.c
+++ b/arch/x86/cpu/apollolake/spl.c
@@ -3,6 +3,8 @@
* Copyright 2019 Google LLC
*/
+#define LOG_CATEGORY LOGC_BOOT
+
#include <common.h>
#include <binman_sym.h>
#include <bootstage.h>
@@ -33,12 +35,11 @@ static int rom_load_image(struct spl_image_info *spl_image,
int ret;
spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
- spl_image->entry_point = spl_phase() == PHASE_TPL ?
- CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
+ spl_image->entry_point = spl_get_image_text_base();
spl_image->load_addr = spl_image->entry_point;
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
- debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
+ log_debug("Reading from mapped SPI %lx, size %lx\n", spl_pos, spl_size);
if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
@@ -56,7 +57,8 @@ static int rom_load_image(struct spl_image_info *spl_image,
return ret;
}
spl_pos += map_base & ~0xff000000;
- debug(", base %lx, pos %lx\n", map_base, spl_pos);
+ log_debug(", base %lx, pos %lx, load %lx\n", map_base, spl_pos,
+ spl_image->load_addr);
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
cpu_flush_l1d_to_l2();
@@ -121,7 +123,7 @@ static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
spl_pos &= ~0xff000000;
- debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
+ log_debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
ret = spi_flash_read_dm(dev, spl_pos, spl_size,
(void *)spl_image->load_addr);
cpu_flush_l1d_to_l2();
diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds
index e6c22895b3..b82e53ab12 100644
--- a/arch/x86/cpu/u-boot-spl.lds
+++ b/arch/x86/cpu/u-boot-spl.lds
@@ -43,11 +43,23 @@ SECTIONS
__binman_sym_start = .;
KEEP(*(SORT(.binman_sym*)));
__binman_sym_end = .;
+
+ /*
+ * Force 32-byte alignment so that it lines up with the start of
+ * bss, which may have up to 32-byte alignment. This ensures
+ * that the end of the .bin file matches up with
+ * _image_binary_end or __bss_end - see board_fdt_blob_setup().
+ * The alignment of BSS depends on what is in it, so can range
+ * from 4 to 32 bytes.
+ */
+ . = ALIGN(32);
}
_image_binary_end = .;
+#if CONFIG_IS_ENABLED(SEPARATE_BSS)
. = 0x120000;
+#endif
.bss (OVERLAY) : {
__bss_start = .;
*(.bss*)
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index 9319123c0c..2ffe3b423c 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -575,6 +575,12 @@
acpi,name = "SDCD";
};
+ emmc: emmc@1c,0 {
+ reg = <0x0000e000 0 0 0 0>;
+ compatible = "intel,apl-emmc";
+ non-removable;
+ };
+
pch: pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,apl-pch";
diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h
index 7f9f101371..69a20812e5 100644
--- a/arch/x86/include/asm/intel_gnvs.h
+++ b/arch/x86/include/asm/intel_gnvs.h
@@ -9,6 +9,7 @@
#ifndef _INTEL_GNVS_H_
#define _INTEL_GNVS_H_
+#include <linux/bitops.h>
/*
* The chromeos_acpi portion of ACPI GNVS is assumed to live from offset
* 0x100 - 0x1000. When defining acpi_global_nvs, use check_member
@@ -19,6 +20,11 @@
#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
enum {
+ BOOT_REASON_OTHER = 0,
+ BOOT_REASON_S3DIAG = 9
+};
+
+enum {
CHSW_RECOVERY_X86 = BIT(1),
CHSW_RECOVERY_EC = BIT(2),
CHSW_DEVELOPER_SWITCH = BIT(5),
@@ -26,6 +32,22 @@ enum {
};
enum {
+ RECOVERY_REASON_NONE = 0,
+ RECOVERY_REASON_ME = 1
+};
+
+enum {
+ ACTIVE_ECFW_RO = 0,
+ ACTIVE_ECFW_RW = 1
+};
+
+enum {
+ BINF_RECOVERY = 0,
+ BINF_RW_A = 1,
+ BINF_RW_B = 2
+};
+
+enum {
FIRMWARE_TYPE_AUTO_DETECT = -1,
FIRMWARE_TYPE_RECOVERY = 0,
FIRMWARE_TYPE_NORMAL = 1,
@@ -40,14 +62,14 @@ struct __packed chromeos_acpi_gnvs {
u32 active_main_fw; /* 04 (0=recovery, 1=A, 2=B) */
u32 activeec_fw; /* 08 (0=RO, 1=RW) */
u16 switches; /* 0c CHSW */
- u8 vbt4[256]; /* 0e HWID */
- u8 vbt5[64]; /* 10e FWID */
- u8 vbt6[64]; /* 14e FRID - 275 */
+ u8 hwid[256]; /* 0e HWID */
+ u8 fwid[64]; /* 10e FWID */
+ u8 frid[64]; /* 14e FRID - 275 */
u32 main_fw_type; /* 18e (2 = developer mode) */
- u32 vbt8; /* 192 recovery reason */
- u32 vbt9; /* 196 fmap base address */
+ u32 recovery_reason; /* 192 recovery reason */
+ u32 fmap_base; /* 196 fmap base address */
u8 vdat[3072]; /* 19a VDAT space filled by verified boot */
- u32 vbt10; /* d9a smbios bios version */
+ u32 fwid_ptr; /* d9a smbios bios version */
u32 mehh[8]; /* d9e management engine hash */
u32 ramoops_base; /* dbe ramoops base address */
u32 ramoops_len; /* dc2 ramoops length */
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 64c0e6e857..6679767d16 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -62,6 +62,16 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
ulong initrd_addr, ulong initrd_size, ulong cmdline_force);
+/**
+ * zimage_dump() - Dump the metadata of a zimage
+ *
+ * This shows all available information in a zimage that has been loaded.
+ *
+ * @base_ptr: Pointer to the boot parameters, typically at address
+ * DEFAULT_SETUP_BASE
+ */
+void zimage_dump(struct boot_params *base_ptr);
+
void setup_video(struct screen_info *screen_info);
void setup_efi_info(struct efi_info *efi_info);
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index cf22fa2d7b..6699de49c6 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -115,8 +115,8 @@ static int x86_spl_init(void)
}
#ifndef CONFIG_SYS_COREBOOT
-# ifndef CONFIG_TPL
memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
+# ifndef CONFIG_TPL
/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
ret = interrupt_init();
diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c
index 04ff32277f..c84a0c9bc7 100644
--- a/arch/x86/lib/tpl.c
+++ b/arch/x86/lib/tpl.c
@@ -111,7 +111,12 @@ int spl_spi_load_image(void)
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
- debug("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point);
+ debug("Jumping to %s at %lx\n", spl_phase_name(spl_next_phase()),
+ (ulong)spl_image->entry_point);
+#ifdef DEBUG
+ print_buffer(spl_image->entry_point, (void *)spl_image->entry_point, 1,
+ 0x20, 0);
+#endif
jump_to_spl(spl_image->entry_point);
hang();
}
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 708025b207..602788e016 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -109,8 +109,11 @@ static void build_command_line(char *command_line, int auto_boot)
if (env_command_line)
strcat(command_line, env_command_line);
-
- printf("Kernel command line: \"%s\"\n", command_line);
+#ifdef DEBUG
+ printf("Kernel command line:");
+ puts(command_line);
+ printf("\n");
+#endif
}
static int kernel_magic_ok(struct setup_header *hdr)
@@ -354,7 +357,8 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
build_command_line(cmd_line, auto_boot);
ret = bootm_process_cmdline(cmd_line, max_size, BOOTM_CL_ALL);
if (ret) {
- printf("Cmdline setup failed (err=%d)\n", ret);
+ printf("Cmdline setup failed (max_size=%x, bootproto=%x, err=%d)\n",
+ max_size, bootproto, ret);
return ret;
}
printf("Kernel command line: \"");
@@ -600,19 +604,12 @@ static void show_loader(struct setup_header *hdr)
printf("\n");
}
-int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+void zimage_dump(struct boot_params *base_ptr)
{
- struct boot_params *base_ptr = state.base_ptr;
struct setup_header *hdr;
const char *version;
int i;
- if (argc > 1)
- base_ptr = (void *)simple_strtoul(argv[1], NULL, 16);
- if (!base_ptr) {
- printf("No zboot setup_base\n");
- return CMD_RET_FAILURE;
- }
printf("Setup located at %p:\n\n", base_ptr);
print_num64("ACPI RSDP addr", base_ptr->acpi_rsdp_addr);
@@ -688,6 +685,20 @@ int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
print_num("Handover offset", hdr->handover_offset);
if (get_boot_protocol(hdr, false) >= 0x215)
print_num("Kernel info offset", hdr->kernel_info_offset);
+}
+
+static int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct boot_params *base_ptr = state.base_ptr;
+
+ if (argc > 1)
+ base_ptr = (void *)simple_strtoul(argv[1], NULL, 16);
+ if (!base_ptr) {
+ printf("No zboot setup_base\n");
+ return CMD_RET_FAILURE;
+ }
+ zimage_dump(base_ptr);
return 0;
}
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