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-rw-r--r--arch/x86/cpu/baytrail/cpu.c2
-rw-r--r--arch/x86/cpu/broadwell/Makefile4
-rw-r--r--arch/x86/cpu/broadwell/cpu.c2
-rw-r--r--arch/x86/cpu/cpu.c4
-rw-r--r--arch/x86/cpu/i386/cpu.c32
-rw-r--r--arch/x86/cpu/ivybridge/bd82x6x.c17
-rw-r--r--arch/x86/cpu/ivybridge/cpu.c2
-rw-r--r--arch/x86/cpu/quark/quark.c2
-rw-r--r--arch/x86/cpu/x86_64/cpu.c7
-rw-r--r--arch/x86/include/asm/cb_sysinfo.h8
-rw-r--r--arch/x86/include/asm/coreboot_tables.h2
-rw-r--r--arch/x86/include/asm/string.h6
-rw-r--r--arch/x86/lib/Makefile4
-rw-r--r--arch/x86/lib/coreboot/cb_sysinfo.c13
-rw-r--r--arch/x86/lib/fsp2/fsp_init.c2
-rw-r--r--arch/x86/lib/mrccache.c2
-rw-r--r--arch/x86/lib/spl.c19
17 files changed, 69 insertions, 59 deletions
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 4fb6a48554..4a7b4f617f 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -64,7 +64,7 @@ static int baytrail_uart_init(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, baytrail_uart_init);
+EVENT_SPY(EVT_DM_POST_INIT_F, baytrail_uart_init);
static void set_max_freq(void)
{
diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 52d56c65be..3e1f76d611 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -2,7 +2,6 @@
#
# Copyright (c) 2016 Google, Inc
-obj-y += adsp.o
obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += cpu.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += cpu_full.o
@@ -14,6 +13,8 @@ obj-y += refcode.o
endif
ifndef CONFIG_SPL_BUILD
# obj-y += cpu_from_spl.o
+obj-y += adsp.o
+obj-y += sata.o
endif
endif
@@ -29,5 +30,4 @@ obj-y += pch.o
obj-y += pinctrl_broadwell.o
obj-y += power_state.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += refcode.o
-obj-y += sata.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += sdram.o
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index 7877961451..f30aebfe4c 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -40,7 +40,7 @@ static int broadwell_init_cpu(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, broadwell_init_cpu);
+EVENT_SPY(EVT_DM_POST_INIT_F, broadwell_init_cpu);
void set_max_freq(void)
{
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 6fe6eaf6c8..dddd281e96 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -351,8 +351,8 @@ long locate_coreboot_table(void)
{
long addr;
- /* We look for LBIO in the first 4K of RAM and again at 960KB */
- addr = detect_coreboot_table_at(0x0, 0x1000);
+ /* We look for LBIO from addresses 1K-4K and again at 960KB */
+ addr = detect_coreboot_table_at(0x400, 0xc00);
if (addr < 0)
addr = detect_coreboot_table_at(0xf0000, 0x1000);
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index c7f6c5a013..91cd5d7c9e 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -572,6 +572,7 @@ int cpu_has_64bit(void)
has_long_mode();
}
+/* Base address for page tables used for 64-bit mode */
#define PAGETABLE_BASE 0x80000
#define PAGETABLE_SIZE (6 * 4096)
@@ -614,43 +615,20 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target)
}
/*
- * Jump from SPL to U-Boot
+ * cpu_jump_to_64bit_uboot() - Jump from SPL to U-Boot
*
- * This function is work-in-progress with many issues to resolve.
- *
- * It works by setting up several regions:
- * ptr - a place to put the code that jumps into 64-bit mode
- * gdt - a place to put the global descriptor table
- * pgtable - a place to put the page tables
- *
- * The cpu_call64() code is copied from ROM and then manually patched so that
- * it has the correct GDT address in RAM. U-Boot is copied from ROM into
- * its pre-relocation address. Then we jump to the cpu_call64() code in RAM,
- * which changes to 64-bit mode and starts U-Boot.
+ * It works by setting up page tables and calling the code to enter 64-bit long
+ * mode
*/
int cpu_jump_to_64bit_uboot(ulong target)
{
- typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
uint32_t *pgtable;
- func_t func;
- char *ptr;
pgtable = (uint32_t *)PAGETABLE_BASE;
-
build_pagetable(pgtable);
- extern long call64_stub_size;
- ptr = malloc(call64_stub_size);
- if (!ptr) {
- printf("Failed to allocate the cpu_call64 stub\n");
- return -ENOMEM;
- }
- memcpy(ptr, cpu_call64, call64_stub_size);
-
- func = (func_t)ptr;
-
/* Jump to U-Boot */
- func((ulong)pgtable, 0, (ulong)target);
+ cpu_call64(PAGETABLE_BASE, 0, (ulong)target);
return -EFAULT;
}
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 89312a8634..417290f559 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -31,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define RCBA_AUDIO_CONFIG_HDA BIT(31)
#define RCBA_AUDIO_CONFIG_MASK 0xfe
-#ifndef CONFIG_HAVE_FSP
static int pch_revision_id = -1;
static int pch_type = -1;
@@ -162,15 +161,19 @@ void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
static int bd82x6x_probe(struct udevice *dev)
{
- if (!(gd->flags & GD_FLG_RELOC))
- return 0;
+ /* make sure the LPC is inited since it provides the gpio base */
+ uclass_first_device(UCLASS_LPC, &dev);
+
+ if (!IS_ENABLED(CONFIG_HAVE_FSP)) {
+ if (!(gd->flags & GD_FLG_RELOC))
+ return 0;
- /* Cause the SATA device to do its init */
- uclass_first_device(UCLASS_AHCI, &dev);
+ /* Cause the SATA device to do its init */
+ uclass_first_device(UCLASS_AHCI, &dev);
+ }
return 0;
}
-#endif /* CONFIG_HAVE_FSP */
static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
{
@@ -269,8 +272,6 @@ U_BOOT_DRIVER(bd82x6x_drv) = {
.name = "bd82x6x",
.id = UCLASS_PCH,
.of_match = bd82x6x_ids,
-#ifndef CONFIG_HAVE_FSP
.probe = bd82x6x_probe,
-#endif
.ops = &bd82x6x_pch_ops,
};
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index cffc5d5b1d..c988d7ff47 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -86,7 +86,7 @@ static int ivybridge_cpu_init(void *ctx, struct event *ev)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, ivybridge_cpu_init);
+EVENT_SPY(EVT_DM_POST_INIT_F, ivybridge_cpu_init);
#define PCH_EHCI0_TEMP_BAR0 0xe8000000
#define PCH_EHCI1_TEMP_BAR0 0xe8000400
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 0a1fbb34d4..1be8e38cdf 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -263,7 +263,7 @@ static int quark_init_pcie(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, quark_init_pcie);
+EVENT_SPY(EVT_DM_POST_INIT_F, quark_init_pcie);
int checkcpu(void)
{
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 6a38761291..d1c3873dd6 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -50,3 +50,10 @@ int x86_cpu_init_f(void)
{
return 0;
}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ /* this was already done in SPL */
+}
+#endif
diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h
index 0201ac6b03..2c78b22d0d 100644
--- a/arch/x86/include/asm/cb_sysinfo.h
+++ b/arch/x86/include/asm/cb_sysinfo.h
@@ -16,6 +16,8 @@
#define SYSINFO_MAX_GPIOS 8
/* Up to 10 MAC addresses */
#define SYSINFO_MAX_MACS 10
+/* Track the first 32 unimplemented tags */
+#define SYSINFO_MAX_UNIMPL 32
/**
* struct sysinfo_t - Information passed to U-Boot from coreboot
@@ -133,6 +135,9 @@
* @mtc_size: Size of MTC region
* @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning
* not used
+ * @rsdp: Pointer to ACPI RSDP table
+ * @unimpl_count: Number of entries in unimpl_map[]
+ * @unimpl: List of unimplemented IDs (bottom 8 bits only)
*/
struct sysinfo_t {
unsigned int cpu_khz;
@@ -211,6 +216,9 @@ struct sysinfo_t {
u64 mtc_start;
u32 mtc_size;
void *chromeos_vpd;
+ void *rsdp;
+ u32 unimpl_count;
+ u8 unimpl[SYSINFO_MAX_UNIMPL];
};
extern struct sysinfo_t lib_sysinfo;
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index f131de56a4..4de137fbab 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -422,6 +422,8 @@ struct cb_tsc_info {
#define CB_TAG_SERIALNO 0x002a
#define CB_MAX_SERIALNO_LENGTH 32
+#define CB_TAG_ACPI_RSDP 0x0043
+
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
struct cb_cmos_option_table {
diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h
index c15b264a5c..5c49b0f009 100644
--- a/arch/x86/include/asm/string.h
+++ b/arch/x86/include/asm/string.h
@@ -14,7 +14,11 @@ extern char *strrchr(const char *s, int c);
#undef __HAVE_ARCH_STRCHR
extern char *strchr(const char *s, int c);
-#ifdef CONFIG_X86_64
+/*
+ * Our assembly routines do not work on in 64-bit mode and we don't do a lot of
+ * copying in SPL, so code size is more important there.
+ */
+#if defined(CONFIG_SPL_BUILD) || !IS_ENABLED(CONFIG_X86_32BIT_INIT)
#undef __HAVE_ARCH_MEMCPY
extern void *memcpy(void *, const void *, __kernel_size_t);
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index a6f2244147..b0612ae6dd 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -10,7 +10,9 @@ obj-y += bios.o
obj-y += bios_asm.o
obj-y += bios_interrupts.o
endif
-obj-y += string.o
+endif
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_X86_32BIT_INIT) += string.o
endif
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c
index 748fa4ee53..42cc3a128d 100644
--- a/arch/x86/lib/coreboot/cb_sysinfo.c
+++ b/arch/x86/lib/coreboot/cb_sysinfo.c
@@ -264,6 +264,13 @@ static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info)
info->mrc_cache = map_sysmem(cbmem->cbmem_tab, 0);
}
+static void cb_parse_acpi_rsdp(void *ptr, struct sysinfo_t *info)
+{
+ struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
+
+ info->rsdp = map_sysmem(cbmem->cbmem_tab, 0);
+}
+
__weak void cb_parse_unhandled(u32 tag, unsigned char *ptr)
{
}
@@ -428,7 +435,12 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_MRC_CACHE:
cb_parse_mrc_cache(rec, info);
break;
+ case CB_TAG_ACPI_RSDP:
+ cb_parse_acpi_rsdp(rec, info);
+ break;
default:
+ if (info->unimpl_count < SYSINFO_MAX_UNIMPL)
+ info->unimpl[info->unimpl_count++] = rec->tag;
cb_parse_unhandled(rec->tag, ptr);
break;
}
@@ -454,6 +466,7 @@ int get_coreboot_info(struct sysinfo_t *info)
if (!ret)
return -ENOENT;
gd->arch.coreboot_table = addr;
+ gd_set_acpi_start(map_to_sysmem(info->rsdp));
gd->flags |= GD_FLG_SKIP_LL_INIT;
return 0;
diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c
index b15926e824..afec7d08d6 100644
--- a/arch/x86/lib/fsp2/fsp_init.c
+++ b/arch/x86/lib/fsp2/fsp_init.c
@@ -42,7 +42,7 @@ int fsp_setup_pinctrl(void *ctx, struct event *event)
return ret;
}
-EVENT_SPY(EVT_DM_POST_INIT, fsp_setup_pinctrl);
+EVENT_SPY(EVT_DM_POST_INIT_F, fsp_setup_pinctrl);
#if !defined(CONFIG_TPL_BUILD)
binman_sym_declare(ulong, intel_fsp_m, image_pos);
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 38632e513f..2f6f688000 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -303,7 +303,7 @@ static int mrccache_save_type(enum mrc_type_t type)
mrc = &gd->arch.mrc[type];
if (!mrc->len)
return 0;
- log_debug("Saving %#x bytes of MRC output data type %d to SPI flash\n",
+ log_debug("Saving %x bytes of MRC output data type %d to SPI flash\n",
mrc->len, type);
ret = mrccache_get_region(type, &sf, &entry);
if (ret)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index bdf57ef7b5..ca1645f9d6 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -117,6 +117,8 @@ static int x86_spl_init(void)
}
#ifndef CONFIG_SYS_COREBOOT
+ debug("BSS clear from %lx to %lx len %lx\n", (ulong)&__bss_start,
+ (ulong)&__bss_end, (ulong)&__bss_end - (ulong)&__bss_start);
memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
# ifndef CONFIG_TPL
@@ -145,7 +147,6 @@ static int x86_spl_init(void)
debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
return ret;
}
- mtrr_commit(true);
# else
ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
if (ret)
@@ -184,7 +185,8 @@ void board_init_f(ulong flags)
void board_init_f_r(void)
{
- init_cache_f_r();
+ mtrr_commit(false);
+ init_cache();
gd->flags &= ~GD_FLG_SERIAL_READY;
debug("cache status %d\n", dcache_status());
board_init_r(gd, 0);
@@ -215,16 +217,9 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
spl_image->name = "U-Boot";
if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) {
- /*
- * Copy U-Boot from ROM
- * TODO(sjg@chromium.org): Figure out a way to get the text base
- * correctly here, and in the device-tree binman definition.
- *
- * Also consider using FIT so we get the correct image length
- * and parameters.
- */
- memcpy((char *)spl_image->load_addr, (char *)0xfff00000,
- 0x100000);
+ /* Copy U-Boot from ROM */
+ memcpy((void *)spl_image->load_addr,
+ (void *)spl_get_image_pos(), spl_get_image_size());
}
debug("Loading to %lx\n", spl_image->load_addr);
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