diff options
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/Kconfig | 6 | ||||
| -rw-r--r-- | arch/x86/cpu/apollolake/Kconfig | 1 | ||||
| -rw-r--r-- | arch/x86/cpu/apollolake/Makefile | 1 | ||||
| -rw-r--r-- | arch/x86/cpu/i386/cpu.c | 10 | ||||
| -rw-r--r-- | arch/x86/cpu/intel_common/Makefile | 1 | ||||
| -rw-r--r-- | arch/x86/cpu/intel_common/itss.c (renamed from arch/x86/cpu/apollolake/itss.c) | 60 | ||||
| -rw-r--r-- | arch/x86/cpu/slimbootloader/serial.c | 13 | ||||
| -rw-r--r-- | arch/x86/cpu/start.S | 2 | ||||
| -rw-r--r-- | arch/x86/cpu/start16.S | 2 | ||||
| -rw-r--r-- | arch/x86/dts/chromebook_coral.dts | 2 | ||||
| -rw-r--r-- | arch/x86/dts/coreboot.dts | 6 | ||||
| -rw-r--r-- | arch/x86/include/asm/coreboot_tables.h | 19 | ||||
| -rw-r--r-- | arch/x86/include/asm/itss.h (renamed from arch/x86/include/asm/arch-apollolake/itss.h) | 2 |
13 files changed, 79 insertions, 46 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 89b93e5de2..b733d2264e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -709,6 +709,12 @@ config ROM_TABLE_SIZE hex default 0x10000 +config HAVE_ITSS + bool "Enable ITSS" + help + Select this to include the driver for the Interrupt Timer + Subsystem (ITSS) which is found on several Intel devices. + menu "System tables" depends on !EFI && !SYS_COREBOOT diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index fcff176c27..a760e0ac68 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -39,6 +39,7 @@ config INTEL_APOLLOLAKE imply HAVE_X86_FIT imply INTEL_GPIO imply SMP + imply HAVE_ITSS if INTEL_APOLLOLAKE diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 1760df54d8..f99f2c6473 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -19,7 +19,6 @@ obj-y += fsp_s.o endif obj-y += hostbridge.o -obj-y += itss.o obj-y += lpc.o obj-y += p2sb.o obj-y += pch.o diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 1592b2c9d3..c8da7f10e9 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -136,10 +136,14 @@ void arch_setup_gd(gd_t *new_gd) /* DS: data, read/write, 4 GB, base 0 */ gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); - /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ + /* + * FS: data, read/write, sizeof (Global Data Pointer), + * base (Global Data Pointer) + */ new_gd->arch.gd_addr = new_gd; - gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, - (ulong)&new_gd->arch.gd_addr, 0xfffff); + gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0x8093, + (ulong)&new_gd->arch.gd_addr, + sizeof(new_gd->arch.gd_addr) - 1); /* 16-bit CS: code, read/execute, 64 kB, base 0 */ gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index cc4e1c962b..e22c70781d 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -27,6 +27,7 @@ obj-y += microcode.o endif endif obj-y += pch.o +obj-$(CONFIG_HAVE_ITSS) += itss.o ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD diff --git a/arch/x86/cpu/apollolake/itss.c b/arch/x86/cpu/intel_common/itss.c index 8789f8e6bb..9df51adecc 100644 --- a/arch/x86/cpu/apollolake/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Something to do with Interrupts, but I don't know what ITSS stands for + * Interrupt Timer Subsystem * * Copyright (C) 2017 Intel Corporation. * Copyright (C) 2017 Siemens AG @@ -15,12 +15,12 @@ #include <irq.h> #include <p2sb.h> #include <spl.h> -#include <asm/arch/itss.h> +#include <asm/itss.h> -struct apl_itss_platdata { +struct itss_platdata { #if CONFIG_IS_ENABLED(OF_PLATDATA) /* Put this first since driver model will copy the data here */ - struct dtd_intel_apl_itss dtplat; + struct dtd_intel_itss dtplat; #endif }; @@ -30,13 +30,13 @@ struct pmc_route { u32 gpio; }; -struct apl_itss_priv { +struct itss_priv { struct pmc_route *route; uint route_count; u32 irq_snapshot[NUM_IPC_REGS]; }; -static int apl_set_polarity(struct udevice *dev, uint irq, bool active_low) +static int set_polarity(struct udevice *dev, uint irq, bool active_low) { u32 mask; uint reg; @@ -53,9 +53,9 @@ static int apl_set_polarity(struct udevice *dev, uint irq, bool active_low) } #ifndef CONFIG_TPL_BUILD -static int apl_snapshot_polarities(struct udevice *dev) +static int snapshot_polarities(struct udevice *dev) { - struct apl_itss_priv *priv = dev_get_priv(dev); + struct itss_priv *priv = dev_get_priv(dev); const int start = GPIO_IRQ_START; const int end = GPIO_IRQ_END; int reg_start; @@ -86,9 +86,9 @@ static void show_polarities(struct udevice *dev, const char *msg) } } -static int apl_restore_polarities(struct udevice *dev) +static int restore_polarities(struct udevice *dev) { - struct apl_itss_priv *priv = dev_get_priv(dev); + struct itss_priv *priv = dev_get_priv(dev); const int start = GPIO_IRQ_START; const int end = GPIO_IRQ_END; int reg_start; @@ -132,9 +132,9 @@ static int apl_restore_polarities(struct udevice *dev) } #endif -static int apl_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num) +static int route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num) { - struct apl_itss_priv *priv = dev_get_priv(dev); + struct itss_priv *priv = dev_get_priv(dev); struct pmc_route *route; int i; @@ -146,14 +146,14 @@ static int apl_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num) return -ENOENT; } -static int apl_itss_ofdata_to_platdata(struct udevice *dev) +static int itss_ofdata_to_platdata(struct udevice *dev) { - struct apl_itss_priv *priv = dev_get_priv(dev); + struct itss_priv *priv = dev_get_priv(dev); int ret; #if CONFIG_IS_ENABLED(OF_PLATDATA) - struct apl_itss_platdata *plat = dev_get_platdata(dev); - struct dtd_intel_apl_itss *dtplat = &plat->dtplat; + struct itss_platdata *plat = dev_get_platdata(dev); + struct dtd_intel_itss *dtplat = &plat->dtplat; /* * It would be nice to do this in the bind() method, but with @@ -189,26 +189,26 @@ static int apl_itss_ofdata_to_platdata(struct udevice *dev) return 0; } -static const struct irq_ops apl_itss_ops = { - .route_pmc_gpio_gpe = apl_route_pmc_gpio_gpe, - .set_polarity = apl_set_polarity, +static const struct irq_ops itss_ops = { + .route_pmc_gpio_gpe = route_pmc_gpio_gpe, + .set_polarity = set_polarity, #ifndef CONFIG_TPL_BUILD - .snapshot_polarities = apl_snapshot_polarities, - .restore_polarities = apl_restore_polarities, + .snapshot_polarities = snapshot_polarities, + .restore_polarities = restore_polarities, #endif }; -static const struct udevice_id apl_itss_ids[] = { - { .compatible = "intel,apl-itss"}, +static const struct udevice_id itss_ids[] = { + { .compatible = "intel,itss"}, { } }; -U_BOOT_DRIVER(apl_itss_drv) = { - .name = "intel_apl_itss", +U_BOOT_DRIVER(itss_drv) = { + .name = "intel_itss", .id = UCLASS_IRQ, - .of_match = apl_itss_ids, - .ops = &apl_itss_ops, - .ofdata_to_platdata = apl_itss_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct apl_itss_platdata), - .priv_auto_alloc_size = sizeof(struct apl_itss_priv), + .of_match = itss_ids, + .ops = &itss_ops, + .ofdata_to_platdata = itss_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct itss_platdata), + .priv_auto_alloc_size = sizeof(struct itss_priv), }; diff --git a/arch/x86/cpu/slimbootloader/serial.c b/arch/x86/cpu/slimbootloader/serial.c index 7b44a59bff..bab54b18df 100644 --- a/arch/x86/cpu/slimbootloader/serial.c +++ b/arch/x86/cpu/slimbootloader/serial.c @@ -34,18 +34,15 @@ static int slimbootloader_serial_ofdata_to_platdata(struct udevice *dev) data->stride, data->clk); - /* - * The data->type provides port io or mmio access type info, - * but the access type will be controlled by - * CONFIG_SYS_NS16550_PORT_MAPPED or CONFIG_SYS_NS16550_MEM32. - * - * TBD: ns16550 access type configuration in runtime. - * ex) plat->access_type = data->type - */ plat->base = data->base; /* ns16550 uses reg_shift, then covert stride to shift */ plat->reg_shift = data->stride >> 1; + plat->reg_width = data->stride; plat->clock = data->clk; + plat->fcr = UART_FCR_DEFVAL; + plat->flags = 0; + if (data->type == 1) + plat->flags |= NS16550_FLAG_IO; return 0; } diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 01524635e9..26cf995db2 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -50,7 +50,7 @@ _x86boot_start: movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 - wbinvd + invd /* * Zero the BIST (Built-In Self Test) value since we don't have it. diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 54f4ff6662..292e750508 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -28,7 +28,7 @@ start16: movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 - wbinvd + invd /* load the temporary Global Descriptor Table */ data32 cs lidt idt_ptr diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 24fcbb5063..a1820fa187 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -171,7 +171,7 @@ itss { u-boot,dm-pre-reloc; - compatible = "intel,apl-itss"; + compatible = "intel,itss"; intel,p2sb-port-id = <PID_ITSS>; intel,pmc-routes = < PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0 diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index a88da6eafd..38ddaafa19 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -8,7 +8,6 @@ /dts-v1/; /include/ "skeleton.dtsi" -/include/ "serial.dtsi" /include/ "keyboard.dtsi" /include/ "pcspkr.dtsi" /include/ "reset.dtsi" @@ -40,6 +39,11 @@ u-boot,dm-pre-reloc; }; + serial: serial { + u-boot,dm-pre-reloc; + compatible = "coreboot-serial"; + }; + coreboot-fb { compatible = "coreboot-fb"; }; diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 2c54e24e02..61de0077d7 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -97,6 +97,25 @@ struct cb_serial { u32 type; u32 baseaddr; u32 baud; + u32 regwidth; + + /* + * Crystal or input frequency to the chip containing the UART. + * Provide the board specific details to allow the payload to + * initialize the chip containing the UART and make independent + * decisions as to which dividers to select and their values + * to eventually arrive at the desired console baud-rate. + */ + u32 input_hertz; + + /* + * UART PCI address: bus, device, function + * 1 << 31 - Valid bit, PCI UART in use + * Bus << 20 + * Device << 15 + * Function << 12 + */ + u32 uart_pci_addr; }; #define CB_TAG_CONSOLE 0x0010 diff --git a/arch/x86/include/asm/arch-apollolake/itss.h b/arch/x86/include/asm/itss.h index 1e29503974..c75d8fe8c2 100644 --- a/arch/x86/include/asm/arch-apollolake/itss.h +++ b/arch/x86/include/asm/itss.h @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* + * Interrupt Timer Subsystem + * * Copyright (C) 2017 Intel Corporation. * Copyright 2019 Google LLC * |