18 files changed, 782 insertions, 103 deletions

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index ca0ca1066b..5cd4587480 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -4,9 +4,11 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 ifndef CONFIG_X86_64
+ifndef CONFIG_TPL_BUILD
 obj-y += bios.o
 obj-y += bios_asm.o
 obj-y += bios_interrupts.o
+endif
 obj-y += string.o
 endif
 ifndef CONFIG_SPL_BUILD
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
index 9e34856473..da6c0a886a 100644
--- a/arch/x86/lib/fsp/Makefile
+++ b/arch/x86/lib/fsp/Makefile
@@ -4,4 +4,7 @@
 
 obj-y += fsp_common.o
 obj-y += fsp_dram.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
+endif
 obj-y += fsp_support.o
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index a5efe35f59..5eff0f99aa 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -58,26 +58,6 @@ void board_final_cleanup(void)
 		debug("OK\n");
 }
 
-void *fsp_prepare_mrc_cache(void)
-{
-	struct mrc_data_container *cache;
-	struct mrc_region entry;
-	int ret;
-
-	ret = mrccache_get_region(NULL, &entry);
-	if (ret)
-		return NULL;
-
-	cache = mrccache_find_current(&entry);
-	if (!cache)
-		return NULL;
-
-	debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
-	      cache->data, cache->data_size, cache->checksum);
-
-	return cache->data;
-}
-
 #ifdef CONFIG_HAVE_ACPI_RESUME
 int fsp_save_s3_stack(void)
 {
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index bc456bb4a9..9ce0ddf0d3 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -9,6 +9,7 @@
 #include <asm/fsp/fsp_support.h>
 #include <asm/e820.h>
 #include <asm/mrccache.h>
+#include <asm/mtrr.h>
 #include <asm/post.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -38,8 +39,40 @@ int fsp_scan_for_ram_size(void)
 
 int dram_init_banksize(void)
 {
+	const struct hob_header *hdr;
+	struct hob_res_desc *res_desc;
+	phys_addr_t low_end;
+	uint bank;
+
+	low_end = 0;
+	for (bank = 1, hdr = gd->arch.hob_list;
+	     bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
+	     hdr = get_next_hob(hdr)) {
+		if (hdr->type != HOB_TYPE_RES_DESC)
+			continue;
+		res_desc = (struct hob_res_desc *)hdr;
+		if (res_desc->type != RES_SYS_MEM &&
+		    res_desc->type != RES_MEM_RESERVED)
+			continue;
+		if (res_desc->phys_start < (1ULL << 32)) {
+			low_end = max(low_end,
+				      res_desc->phys_start + res_desc->len);
+			continue;
+		}
+
+		gd->bd->bi_dram[bank].start = res_desc->phys_start;
+		gd->bd->bi_dram[bank].size = res_desc->len;
+		mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
+				 res_desc->len);
+		log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
+			  gd->bd->bi_dram[bank].size);
+	}
+
+	/* Add the memory below 4GB */
 	gd->bd->bi_dram[0].start = 0;
-	gd->bd->bi_dram[0].size = gd->ram_size;
+	gd->bd->bi_dram[0].size = low_end;
+
+	mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
 
 	return 0;
 }
diff --git a/arch/x86/lib/fsp1/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
index 52e71334f9..226c7e66b3 100644
--- a/arch/x86/lib/fsp1/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -7,7 +7,8 @@
 #include <dm.h>
 #include <vbe.h>
 #include <video.h>
-#include <asm/fsp1/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
+#include <asm/mtrr.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -97,6 +98,9 @@ static int fsp_video_probe(struct udevice *dev)
 	if (ret)
 		goto err;
 
+	mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
+	mtrr_commit(true);
+
 	printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
 	       vesa->bits_per_pixel);
 
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index 983888fd74..ee228117d1 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <asm/fsp1/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
 #include <asm/post.h>
 
 u32 fsp_get_usable_lowmem_top(const void *hob_list)
diff --git a/arch/x86/lib/fsp1/Makefile b/arch/x86/lib/fsp1/Makefile
index 870de71bd7..1cf5e54191 100644
--- a/arch/x86/lib/fsp1/Makefile
+++ b/arch/x86/lib/fsp1/Makefile
@@ -5,5 +5,4 @@
 obj-y += fsp_car.o
 obj-y += fsp_common.o
 obj-y += fsp_dram.o
-obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
 obj-y += fsp_support.o
diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c
index e8066d8de3..ec9c218778 100644
--- a/arch/x86/lib/fsp1/fsp_common.c
+++ b/arch/x86/lib/fsp1/fsp_common.c
@@ -18,6 +18,26 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void *fsp_prepare_mrc_cache(void)
+{
+	struct mrc_data_container *cache;
+	struct mrc_region entry;
+	int ret;
+
+	ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
+	if (ret)
+		return NULL;
+
+	cache = mrccache_find_current(&entry);
+	if (!cache)
+		return NULL;
+
+	debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
+	      cache->data, cache->data_size, cache->checksum);
+
+	return cache->data;
+}
+
 int arch_fsp_init(void)
 {
 	void *nvs;
diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c
index 6a3349b42a..5ef89744b9 100644
--- a/arch/x86/lib/fsp1/fsp_dram.c
+++ b/arch/x86/lib/fsp1/fsp_dram.c
@@ -15,9 +15,11 @@ int dram_init(void)
 	if (ret)
 		return ret;
 
-	if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
-		gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list,
-					       &gd->arch.mrc_output_len);
+	if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
+		struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
+
+		mrc->buf = fsp_get_nvs_data(gd->arch.hob_list, &mrc->len);
+	}
 
 	return 0;
 }
diff --git a/arch/x86/lib/fsp2/Makefile b/arch/x86/lib/fsp2/Makefile
new file mode 100644
index 0000000000..ddbe2d0db2
--- /dev/null
+++ b/arch/x86/lib/fsp2/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Google LLC
+
+obj-y += fsp_common.o
+obj-y += fsp_dram.o
+obj-y += fsp_init.o
+obj-y += fsp_meminit.o
+obj-y += fsp_silicon_init.o
+obj-y += fsp_support.o
diff --git a/arch/x86/lib/fsp2/fsp_common.c b/arch/x86/lib/fsp2/fsp_common.c
new file mode 100644
index 0000000000..f69456e43a
--- /dev/null
+++ b/arch/x86/lib/fsp2/fsp_common.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <init.h>
+
+int arch_fsp_init(void)
+{
+	return 0;
+}
diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c
new file mode 100644
index 0000000000..90a238a224
--- /dev/null
+++ b/arch/x86/lib/fsp2/fsp_dram.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <acpi_s3.h>
+#include <handoff.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/fsp/fsp_support.h>
+#include <asm/fsp2/fsp_api.h>
+#include <asm/fsp2/fsp_internal.h>
+
+int dram_init(void)
+{
+	int ret;
+
+	if (spl_phase() == PHASE_SPL) {
+#ifdef CONFIG_HAVE_ACPI_RESUME
+		bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
+#else
+		bool s3wake = false;
+#endif
+
+		ret = fsp_memory_init(s3wake,
+			      IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH));
+		if (ret) {
+			debug("Memory init failed (err=%x)\n", ret);
+			return ret;
+		}
+
+		/* The FSP has already set up DRAM, so grab the info we need */
+		ret = fsp_scan_for_ram_size();
+		if (ret)
+			return ret;
+
+#ifdef CONFIG_ENABLE_MRC_CACHE
+		gd->arch.mrc[MRC_TYPE_NORMAL].buf =
+			fsp_get_nvs_data(gd->arch.hob_list,
+					 &gd->arch.mrc[MRC_TYPE_NORMAL].len);
+		gd->arch.mrc[MRC_TYPE_VAR].buf =
+			fsp_get_var_nvs_data(gd->arch.hob_list,
+					     &gd->arch.mrc[MRC_TYPE_VAR].len);
+		log_debug("normal %x, var %x\n",
+			  gd->arch.mrc[MRC_TYPE_NORMAL].len,
+			  gd->arch.mrc[MRC_TYPE_VAR].len);
+#endif
+	} else {
+#if CONFIG_IS_ENABLED(HANDOFF)
+		struct spl_handoff *ho = gd->spl_handoff;
+
+		if (!ho) {
+			debug("No SPL handoff found\n");
+			return -ESTRPIPE;
+		}
+		gd->ram_size = ho->ram_size;
+		handoff_load_dram_banks(ho);
+#endif
+		ret = arch_fsps_preinit();
+		if (ret)
+			return log_msg_ret("fsp_s_preinit", ret);
+	}
+
+	return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#if CONFIG_IS_ENABLED(HANDOFF)
+	struct spl_handoff *ho = gd->spl_handoff;
+
+	return ho->arch.usable_ram_top;
+#endif
+
+	return gd->ram_top;
+}
diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c
new file mode 100644
index 0000000000..da9bd6b45c
--- /dev/null
+++ b/arch/x86/lib/fsp2/fsp_init.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include <common.h>
+#include <binman.h>
+#include <binman_sym.h>
+#include <cbfs.h>
+#include <dm.h>
+#include <init.h>
+#include <spi.h>
+#include <spl.h>
+#include <spi_flash.h>
+#include <asm/intel_pinctrl.h>
+#include <dm/uclass-internal.h>
+#include <asm/fsp2/fsp_internal.h>
+
+int arch_cpu_init_dm(void)
+{
+	struct udevice *dev;
+	ofnode node;
+	int ret;
+
+	/* Make sure pads are set up early in U-Boot */
+	if (spl_phase() != PHASE_BOARD_F)
+		return 0;
+
+	/* Probe all pinctrl devices to set up the pads */
+	ret = uclass_first_device_err(UCLASS_PINCTRL, &dev);
+	if (ret)
+		return log_msg_ret("no fsp pinctrl", ret);
+	node = ofnode_path("fsp");
+	if (!ofnode_valid(node))
+		return log_msg_ret("no fsp params", -EINVAL);
+	ret = pinctrl_config_pads_for_node(dev, node);
+	if (ret)
+		return log_msg_ret("pad config", ret);
+
+	return ret;
+}
+
+#if !defined(CONFIG_TPL_BUILD)
+binman_sym_declare(ulong, intel_fsp_m, image_pos);
+binman_sym_declare(ulong, intel_fsp_m, size);
+
+/**
+ * get_cbfs_fsp() - Obtain the FSP by looking up in CBFS
+ *
+ * This looks up an FSP in a CBFS. It is used mostly for testing, when booting
+ * U-Boot from a hybrid image containing coreboot as the first-stage bootloader.
+ *
+ * The typical use for this feature is when building a Chrome OS image which
+ * includes coreboot in it. By adding U-Boot into the 'COREBOOT' CBFS as well,
+ * it is possible to make coreboot chain-load U-Boot. Thus the initial stages of
+ * the SoC init can be done by coreboot and the later stages by U-Boot. This is
+ * a convenient way to start the porting work. The jump to U-Boot can then be
+ * moved progressively earlier and earlier, until U-Boot takes over all the init
+ * and you have a native port.
+ *
+ * This function looks up a CBFS at a known location and reads the FSP-M from it
+ * so that U-Boot can init the memory.
+ *
+ * This function is not used in the normal boot but is kept here for future
+ * development.
+ *
+ * @type; Type to look up (only FSP_M supported at present)
+ * @map_base: Base memory address for mapped SPI
+ * @entry: Returns an entry containing the position of the FSP image
+ */
+static int get_cbfs_fsp(enum fsp_type_t type, ulong map_base,
+			struct binman_entry *entry)
+{
+	/*
+	 * Use a hard-coded position of CBFS in the ROM for now. It would be
+	 * possible to read the position using the FMAP in the ROM, but since
+	 * this code is only used for development, it doesn't seem worth it.
+	 * Use the 'cbfstool <image> layout' command to get these values, e.g.:
+	 * 'COREBOOT' (CBFS, size 1814528, offset 2117632).
+	 */
+	ulong cbfs_base = 0x205000;
+	ulong cbfs_size = 0x1bb000;
+	struct cbfs_priv *cbfs;
+	int ret;
+
+	ret = cbfs_init_mem(map_base + cbfs_base, cbfs_size, &cbfs);
+	if (ret)
+		return ret;
+	if (!ret) {
+		const struct cbfs_cachenode *node;
+
+		node = cbfs_find_file(cbfs, "fspm.bin");
+		if (!node)
+			return log_msg_ret("fspm node", -ENOENT);
+
+		entry->image_pos = (ulong)node->data;
+		entry->size = node->data_length;
+	}
+
+	return 0;
+}
+
+int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry,
+		   bool use_spi_flash, struct udevice **devp,
+		   struct fsp_header **hdrp, ulong *rom_offsetp)
+{
+	ulong mask = CONFIG_ROM_SIZE - 1;
+	struct udevice *dev;
+	ulong rom_offset = 0;
+	uint map_size;
+	ulong map_base;
+	uint offset;
+	int ret;
+
+	/*
+	 * Find the devices but don't probe them, since we don't want to
+	 * auto-config PCI before silicon init runs
+	 */
+	ret = uclass_find_first_device(UCLASS_NORTHBRIDGE, &dev);
+	if (ret)
+		return log_msg_ret("Cannot get northbridge", ret);
+	if (!use_spi_flash) {
+		struct udevice *sf;
+
+		/* Just use the SPI driver to get the memory map */
+		ret = uclass_find_first_device(UCLASS_SPI_FLASH, &sf);
+		if (ret)
+			return log_msg_ret("Cannot get SPI flash", ret);
+		ret = dm_spi_get_mmap(sf, &map_base, &map_size, &offset);
+		if (ret)
+			return log_msg_ret("Could not get flash mmap", ret);
+	}
+
+	if (spl_phase() >= PHASE_BOARD_F) {
+		if (type != FSP_S)
+			return -EPROTONOSUPPORT;
+		ret = binman_entry_find("intel-fsp-s", entry);
+		if (ret)
+			return log_msg_ret("binman entry", ret);
+		if (!use_spi_flash)
+			rom_offset = (map_base & mask) - CONFIG_ROM_SIZE;
+	} else {
+		ret = -ENOENT;
+		if (false)
+			/*
+			 * Support using a hybrid image build by coreboot. See
+			 * the function comments for details
+			 */
+			ret = get_cbfs_fsp(type, map_base, entry);
+		if (ret) {
+			ulong mask = CONFIG_ROM_SIZE - 1;
+
+			if (type != FSP_M)
+				return -EPROTONOSUPPORT;
+			entry->image_pos = binman_sym(ulong, intel_fsp_m,
+						      image_pos);
+			entry->size = binman_sym(ulong, intel_fsp_m, size);
+			if (entry->image_pos != BINMAN_SYM_MISSING) {
+				ret = 0;
+				if (use_spi_flash)
+					entry->image_pos &= mask;
+				else
+					entry->image_pos += (map_base & mask);
+			} else {
+				ret = -ENOENT;
+			}
+		}
+	}
+	if (ret)
+		return log_msg_ret("Cannot find FSP", ret);
+	entry->image_pos += rom_offset;
+
+	/*
+	 * Account for the time taken to read memory-mapped SPI flash since in
+	 * this case we don't use the SPI driver and BOOTSTAGE_ID_ACCUM_SPI.
+	 */
+	if (!use_spi_flash)
+		bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
+	ret = fsp_get_header(entry->image_pos, entry->size, use_spi_flash,
+			     hdrp);
+	if (!use_spi_flash)
+		bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
+	if (ret)
+		return log_msg_ret("fsp_get_header", ret);
+	*devp = dev;
+	if (rom_offsetp)
+		*rom_offsetp = rom_offset;
+
+	return 0;
+}
+#endif
diff --git a/arch/x86/lib/fsp2/fsp_meminit.c b/arch/x86/lib/fsp2/fsp_meminit.c
new file mode 100644
index 0000000000..bf30c47989
--- /dev/null
+++ b/arch/x86/lib/fsp2/fsp_meminit.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: Intel
+/*
+ * Copyright (C) 2015-2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ * Mostly taken from coreboot fsp2_0/memory_init.c
+ */
+
+#include <common.h>
+#include <binman.h>
+#include <asm/mrccache.h>
+#include <asm/fsp/fsp_infoheader.h>
+#include <asm/fsp2/fsp_api.h>
+#include <asm/fsp2/fsp_internal.h>
+#include <asm/arch/fsp/fsp_configs.h>
+#include <asm/arch/fsp/fsp_m_upd.h>
+
+static int prepare_mrc_cache_type(enum mrc_type_t type,
+				  struct mrc_data_container **cachep)
+{
+	struct mrc_data_container *cache;
+	struct mrc_region entry;
+	int ret;
+
+	ret = mrccache_get_region(type, NULL, &entry);
+	if (ret)
+		return ret;
+	cache = mrccache_find_current(&entry);
+	if (!cache)
+		return -ENOENT;
+
+	log_debug("MRC at %x, size %x\n", (uint)cache->data, cache->data_size);
+	*cachep = cache;
+
+	return 0;
+}
+
+int prepare_mrc_cache(struct fspm_upd *upd)
+{
+	struct mrc_data_container *cache;
+	int ret;
+
+	ret = prepare_mrc_cache_type(MRC_TYPE_NORMAL, &cache);
+	if (ret)
+		return log_msg_ret("Cannot get normal cache", ret);
+	upd->arch.nvs_buffer_ptr = cache->data;
+
+	ret = prepare_mrc_cache_type(MRC_TYPE_VAR, &cache);
+	if (ret)
+		return log_msg_ret("Cannot get var cache", ret);
+	upd->config.variable_nvs_buffer_ptr = cache->data;
+
+	return 0;
+}
+
+int fsp_memory_init(bool s3wake, bool use_spi_flash)
+{
+	struct fspm_upd upd, *fsp_upd;
+	fsp_memory_init_func func;
+	struct binman_entry entry;
+	struct fsp_header *hdr;
+	struct hob_header *hob;
+	struct udevice *dev;
+	int ret;
+
+	ret = fsp_locate_fsp(FSP_M, &entry, use_spi_flash, &dev, &hdr, NULL);
+	if (ret)
+		return log_msg_ret("locate FSP", ret);
+	debug("Found FSP_M at %x, size %x\n", hdr->img_base, hdr->img_size);
+
+	/* Copy over the default config */
+	fsp_upd = (struct fspm_upd *)(hdr->img_base + hdr->cfg_region_off);
+	if (fsp_upd->header.signature != FSPM_UPD_SIGNATURE)
+		return log_msg_ret("Bad UPD signature", -EPERM);
+	memcpy(&upd, fsp_upd, sizeof(upd));
+
+	ret = fspm_update_config(dev, &upd);
+	if (ret)
+		return log_msg_ret("Could not setup config", ret);
+
+	debug("SDRAM init...");
+	bootstage_start(BOOTSTATE_ID_ACCUM_FSP_M, "fsp-m");
+	func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init);
+	ret = func(&upd, &hob);
+	bootstage_accum(BOOTSTATE_ID_ACCUM_FSP_M);
+	if (ret)
+		return log_msg_ret("SDRAM init fail\n", ret);
+
+	gd->arch.hob_list = hob;
+	debug("done\n");
+
+	ret = fspm_done(dev);
+	if (ret)
+		return log_msg_ret("fsm_done\n", ret);
+
+	return 0;
+}
diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c
new file mode 100644
index 0000000000..d7ce43e1eb
--- /dev/null
+++ b/arch/x86/lib/fsp2/fsp_silicon_init.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: Intel
+/*
+ * Copyright (C) 2015-2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ *
+ * Mostly taken from coreboot fsp2_0/silicon_init.c
+ */
+
+#define LOG_CATEGORY UCLASS_NORTHBRIDGE
+
+#include <common.h>
+#include <binman.h>
+#include <dm.h>
+#include <asm/arch/fsp/fsp_configs.h>
+#include <asm/arch/fsp/fsp_s_upd.h>
+#include <asm/fsp/fsp_infoheader.h>
+#include <asm/fsp2/fsp_internal.h>
+
+int fsp_silicon_init(bool s3wake, bool use_spi_flash)
+{
+	struct fsps_upd upd, *fsp_upd;
+	fsp_silicon_init_func func;
+	struct fsp_header *hdr;
+	struct binman_entry entry;
+	struct udevice *dev;
+	ulong rom_offset = 0;
+	int ret;
+
+	ret = fsp_locate_fsp(FSP_S, &entry, use_spi_flash, &dev, &hdr,
+			     &rom_offset);
+	if (ret)
+		return log_msg_ret("locate FSP", ret);
+	gd->arch.fsp_s_hdr = hdr;
+
+	/* Copy over the default config */
+	fsp_upd = (struct fsps_upd *)(hdr->img_base + hdr->cfg_region_off);
+	if (fsp_upd->header.signature != FSPS_UPD_SIGNATURE)
+		return log_msg_ret("Bad UPD signature", -EPERM);
+	memcpy(&upd, fsp_upd, sizeof(upd));
+
+	ret = fsps_update_config(dev, rom_offset, &upd);
+	if (ret)
+		return log_msg_ret("Could not setup config", ret);
+	log_debug("Silicon init...");
+	bootstage_start(BOOTSTATE_ID_ACCUM_FSP_S, "fsp-s");
+	func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init);
+	ret = func(&upd);
+	bootstage_accum(BOOTSTATE_ID_ACCUM_FSP_S);
+	if (ret)
+		return log_msg_ret("Silicon init fail\n", ret);
+	log_debug("done\n");
+
+	return 0;
+}
diff --git a/arch/x86/lib/fsp2/fsp_support.c b/arch/x86/lib/fsp2/fsp_support.c
new file mode 100644
index 0000000000..0a04b443f7
--- /dev/null
+++ b/arch/x86/lib/fsp2/fsp_support.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: Intel
+/*
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi_flash.h>
+#include <asm/fsp/fsp_support.h>
+#include <asm/fsp2/fsp_internal.h>
+
+/* The amount of the FSP header to probe to obtain what we need */
+#define PROBE_BUF_SIZE 0x180
+
+int fsp_get_header(ulong offset, ulong size, bool use_spi_flash,
+		   struct fsp_header **fspp)
+{
+	static efi_guid_t guid = FSP_HEADER_GUID;
+	struct fv_ext_header *exhdr;
+	struct fsp_header *fsp;
+	struct ffs_file_header *file_hdr;
+	struct fv_header *fv;
+	struct raw_section *raw;
+	void *ptr, *base;
+	u8 buf[PROBE_BUF_SIZE];
+	struct udevice *dev;
+	int ret;
+
+	/*
+	 * There are quite a very steps to work through all the headers in this
+	 * file and the structs have similar names. Turn on debugging if needed
+	 * to understand what is going wrong.
+	 *
+	 * You are in a maze of twisty little headers all alike.
+	 */
+	debug("offset=%x buf=%x\n", (uint)offset, (uint)buf);
+	if (use_spi_flash) {
+		ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
+		if (ret)
+			return log_msg_ret("Cannot find flash device", ret);
+		ret = spi_flash_read_dm(dev, offset, PROBE_BUF_SIZE, buf);
+		if (ret)
+			return log_msg_ret("Cannot read flash", ret);
+	} else {
+		memcpy(buf, (void *)offset, PROBE_BUF_SIZE);
+	}
+
+	/* Initalise the FSP base */
+	ptr = buf;
+	fv = ptr;
+
+	/* Check the FV signature, _FVH */
+	debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign);
+	if (fv->sign != EFI_FVH_SIGNATURE)
+		return log_msg_ret("Base FV signature", -EINVAL);
+
+	/* Go to the end of the FV header and align the address */
+	debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off);
+	ptr += fv->ext_hdr_off;
+	exhdr = ptr;
+	ptr += ALIGN(exhdr->ext_hdr_size, 8);
+	debug("ptr=%x\n", ptr - (void *)buf);
+
+	/* Check the FFS GUID */
+	file_hdr = ptr;
+	if (memcmp(&file_hdr->name, &guid, sizeof(guid)))
+		return log_msg_ret("Base FFS GUID", -ENXIO);
+	/* Add the FFS header size to find the raw section header */
+	ptr = file_hdr + 1;
+
+	raw = ptr;
+	debug("raw->type = %x\n", raw->type);
+	if (raw->type != EFI_SECTION_RAW)
+		return log_msg_ret("Section type not RAW", -ENOEXEC);
+
+	/* Add the raw section header size to find the FSP header */
+	ptr = raw + 1;
+	fsp = ptr;
+
+	/* Check the FSPH header */
+	debug("fsp %x\n", (uint)fsp);
+	if (fsp->sign != EFI_FSPH_SIGNATURE)
+		return log_msg_ret("Base FSPH signature", -EACCES);
+
+	base = (void *)fsp->img_base;
+	debug("Image base %x\n", (uint)base);
+	debug("Image addr %x\n", (uint)fsp->fsp_mem_init);
+	if (use_spi_flash) {
+		ret = spi_flash_read_dm(dev, offset, size, base);
+		if (ret)
+			return log_msg_ret("Could not read FPS-M", ret);
+	} else {
+		memcpy(base, (void *)offset, size);
+	}
+	ptr = base + (ptr - (void *)buf);
+	*fspp = ptr;
+
+	return 0;
+}
+
+u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)
+{
+	fsp_notify_f notify;
+	struct fsp_notify_params params;
+	struct fsp_notify_params *params_ptr;
+	u32 status;
+
+	if (!fsp_hdr)
+		fsp_hdr = gd->arch.fsp_s_hdr;
+
+	if (!fsp_hdr)
+		return log_msg_ret("no FSP", -ENOENT);
+
+	notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify);
+	params.phase = phase;
+	params_ptr = &params;
+
+	/*
+	 * Use ASM code to ensure correct parameter is on the stack for
+	 * FspNotify as U-Boot is using different ABI from FSP
+	 */
+	asm volatile (
+		"pushl	%1;"		/* push notify phase */
+		"call	*%%eax;"	/* call FspNotify */
+		"addl	$4, %%esp;"	/* clean up the stack */
+		: "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr)
+	);
+
+	return status;
+}
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 33bb52039b..b9420a4cab 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -14,6 +14,8 @@
 #include <spi.h>
 #include <spi_flash.h>
 #include <asm/mrccache.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -80,21 +82,31 @@ struct mrc_data_container *mrccache_find_current(struct mrc_region *entry)
 /**
  * find_next_mrc_cache() - get next cache entry
  *
+ * This moves to the next cache entry in the region, making sure it has enough
+ * space to hold data of size @data_size.
+ *
  * @entry:	MRC cache flash area
  * @cache:	Entry to start from
+ * @data_size:	Required data size of the new entry. Note that we assume that
+ *	all cache entries are the same size
  *
  * @return next cache entry if found, NULL if we got to the end
  */
 static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry,
-		struct mrc_data_container *cache)
+		struct mrc_data_container *prev, int data_size)
 {
+	struct mrc_data_container *cache;
 	ulong base_addr, end_addr;
 
 	base_addr = entry->base + entry->offset;
 	end_addr = base_addr + entry->length;
 
-	cache = next_mrc_block(cache);
-	if ((ulong)cache >= end_addr) {
+	/*
+	 * We assume that all cache entries are the same size, but let's use
+	 * data_size here for clarity.
+	 */
+	cache = next_mrc_block(prev);
+	if ((ulong)cache + mrc_block_size(data_size) > end_addr) {
 		/* Crossed the boundary */
 		cache = NULL;
 		debug("%s: no available entries found\n", __func__);
@@ -106,8 +118,20 @@ static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry,
 	return cache;
 }
 
-int mrccache_update(struct udevice *sf, struct mrc_region *entry,
-		    struct mrc_data_container *cur)
+/**
+ * mrccache_update() - update the MRC cache with a new record
+ *
+ * This writes a new record to the end of the MRC cache region. If the new
+ * record is the same as the latest record then the write is skipped
+ *
+ * @sf:		SPI flash to write to
+ * @entry:	Position and size of MRC cache in SPI flash
+ * @cur:	Record to write
+ * @return 0 if updated, -EEXIST if the record is the same as the latest
+ * record, -EINVAL if the record is not valid, other error if SPI write failed
+ */
+static int mrccache_update(struct udevice *sf, struct mrc_region *entry,
+			   struct mrc_data_container *cur)
 {
 	struct mrc_data_container *cache;
 	ulong offset;
@@ -131,7 +155,7 @@ int mrccache_update(struct udevice *sf, struct mrc_region *entry,
 
 	/* Move to the next block, which will be the first unused block */
 	if (cache)
-		cache = find_next_mrc_cache(entry, cache);
+		cache = find_next_mrc_cache(entry, cache, cur->data_size);
 
 	/*
 	 * If we have got to the end, erase the entire mrc-cache area and start
@@ -156,130 +180,158 @@ int mrccache_update(struct udevice *sf, struct mrc_region *entry,
 				 cur);
 	if (ret) {
 		debug("Failed to write to SPI flash\n");
-		return ret;
+		return log_msg_ret("Cannot update mrccache", ret);
 	}
 
 	return 0;
 }
 
-static void mrccache_setup(void *data)
+static void mrccache_setup(struct mrc_output *mrc, void *data)
 {
 	struct mrc_data_container *cache = data;
 	u16 checksum;
 
 	cache->signature = MRC_DATA_SIGNATURE;
-	cache->data_size = gd->arch.mrc_output_len;
-	checksum = compute_ip_checksum(gd->arch.mrc_output, cache->data_size);
+	cache->data_size = mrc->len;
+	checksum = compute_ip_checksum(mrc->buf, cache->data_size);
 	debug("Saving %d bytes for MRC output data, checksum %04x\n",
 	      cache->data_size, checksum);
 	cache->checksum = checksum;
 	cache->reserved = 0;
-	memcpy(cache->data, gd->arch.mrc_output, cache->data_size);
+	memcpy(cache->data, mrc->buf, cache->data_size);
 
-	/* gd->arch.mrc_output now points to the container */
-	gd->arch.mrc_output = (char *)cache;
+	mrc->cache = cache;
 }
 
 int mrccache_reserve(void)
 {
-	if (!gd->arch.mrc_output_len)
-		return 0;
+	int i;
 
-	/* adjust stack pointer to store pure cache data plus the header */
-	gd->start_addr_sp -= (gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE);
-	mrccache_setup((void *)gd->start_addr_sp);
+	for (i = 0; i < MRC_TYPE_COUNT; i++) {
+		struct mrc_output *mrc = &gd->arch.mrc[i];
 
-	gd->start_addr_sp &= ~0xf;
+		if (!mrc->len)
+			continue;
+
+		/* adjust stack pointer to store pure cache data plus header */
+		gd->start_addr_sp -= (mrc->len + MRC_DATA_HEADER_SIZE);
+		mrccache_setup(mrc, (void *)gd->start_addr_sp);
+
+		gd->start_addr_sp &= ~0xf;
+	}
 
 	return 0;
 }
 
-int mrccache_get_region(struct udevice **devp, struct mrc_region *entry)
+int mrccache_get_region(enum mrc_type_t type, struct udevice **devp,
+			struct mrc_region *entry)
 {
-	const void *blob = gd->fdt_blob;
-	int node, mrc_node;
+	struct udevice *dev;
+	ofnode mrc_node;
+	ulong map_base;
+	uint map_size;
+	uint offset;
 	u32 reg[2];
 	int ret;
 
-	/* Find the flash chip within the SPI controller node */
-	node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
-	if (node < 0) {
-		debug("%s: Cannot find SPI flash\n", __func__);
-		return -ENOENT;
-	}
-
-	if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2)) {
-		debug("%s: Cannot find memory map\n", __func__);
-		return -EINVAL;
+	/*
+	 * Find the flash chip within the SPI controller node. Avoid probing
+	 * the device here since it may put it into a strange state where the
+	 * memory map cannot be read.
+	 */
+	ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
+	if (ret)
+		return log_msg_ret("Cannot find SPI flash\n", ret);
+	ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
+	if (!ret) {
+		entry->base = map_base;
+	} else {
+		ret = dev_read_u32_array(dev, "memory-map", reg, 2);
+		if (ret)
+			return log_msg_ret("Cannot find memory map\n", ret);
+		entry->base = reg[0];
 	}
-	entry->base = reg[0];
 
 	/* Find the place where we put the MRC cache */
-	mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache");
-	if (mrc_node < 0) {
-		debug("%s: Cannot find node\n", __func__);
-		return -EPERM;
-	}
+	mrc_node = dev_read_subnode(dev, type == MRC_TYPE_NORMAL ?
+				    "rw-mrc-cache" : "rw-var-mrc-cache");
+	if (!ofnode_valid(mrc_node))
+		return log_msg_ret("Cannot find node", -EPERM);
 
-	if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2)) {
-		debug("%s: Cannot find address\n", __func__);
-		return -EINVAL;
-	}
+	ret = ofnode_read_u32_array(mrc_node, "reg", reg, 2);
+	if (ret)
+		return log_msg_ret("Cannot find address", ret);
 	entry->offset = reg[0];
 	entry->length = reg[1];
 
-	if (devp) {
-		ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
-						     devp);
-		debug("ret = %d\n", ret);
-		if (ret)
-			return ret;
-	}
+	if (devp)
+		*devp = dev;
+	debug("MRC cache type %d in '%s', offset %x, len %x, base %x\n",
+	      type, dev->name, entry->offset, entry->length, entry->base);
 
 	return 0;
 }
 
-int mrccache_save(void)
+static int mrccache_save_type(enum mrc_type_t type)
 {
-	struct mrc_data_container *data;
+	struct mrc_data_container *cache;
+	struct mrc_output *mrc;
 	struct mrc_region entry;
 	struct udevice *sf;
 	int ret;
 
-	if (!gd->arch.mrc_output_len)
+	mrc = &gd->arch.mrc[type];
+	if (!mrc->len)
 		return 0;
-	debug("Saving %d bytes of MRC output data to SPI flash\n",
-	      gd->arch.mrc_output_len);
-
-	ret = mrccache_get_region(&sf, &entry);
+	log_debug("Saving %#x bytes of MRC output data type %d to SPI flash\n",
+		  mrc->len, type);
+	ret = mrccache_get_region(type, &sf, &entry);
 	if (ret)
-		goto err_entry;
-	data  = (struct mrc_data_container *)gd->arch.mrc_output;
-	ret = mrccache_update(sf, &entry, data);
-	if (!ret) {
-		debug("Saved MRC data with checksum %04x\n", data->checksum);
-	} else if (ret == -EEXIST) {
+		return log_msg_ret("Cannot get region", ret);
+	ret = device_probe(sf);
+	if (ret)
+		return log_msg_ret("Cannot probe device", ret);
+	cache = mrc->cache;
+
+	ret = mrccache_update(sf, &entry, cache);
+	if (!ret)
+		debug("Saved MRC data with checksum %04x\n", cache->checksum);
+	else if (ret == -EEXIST)
 		debug("MRC data is the same as last time, skipping save\n");
-		ret = 0;
+
+	return 0;
+}
+
+int mrccache_save(void)
+{
+	int i;
+
+	for (i = 0; i < MRC_TYPE_COUNT; i++) {
+		int ret;
+
+		ret = mrccache_save_type(i);
+		if (ret)
+			return ret;
 	}
 
-err_entry:
-	if (ret)
-		debug("%s: Failed: %d\n", __func__, ret);
-	return ret;
+	return 0;
 }
 
 int mrccache_spl_save(void)
 {
-	void *data;
-	int size;
-
-	size = gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE;
-	data = malloc(size);
-	if (!data)
-		return log_msg_ret("Allocate MRC cache block", -ENOMEM);
-	mrccache_setup(data);
-	gd->arch.mrc_output = data;
+	int i;
+
+	for (i = 0; i < MRC_TYPE_COUNT; i++) {
+		struct mrc_output *mrc = &gd->arch.mrc[i];
+		void *data;
+		int size;
+
+		size = mrc->len + MRC_DATA_HEADER_SIZE;
+		data = malloc(size);
+		if (!data)
+			return log_msg_ret("Allocate MRC cache block", -ENOMEM);
+		mrccache_setup(mrc, data);
+	}
 
 	return mrccache_save();
 }
diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c
index e5f0e61424..17bd2fcb9b 100644
--- a/arch/x86/lib/pirq_routing.c
+++ b/arch/x86/lib/pirq_routing.c
@@ -10,6 +10,8 @@
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap,
 				 bool irq_already_routed[])
 {
@@ -131,3 +133,11 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt)
 
 	return addr + rt->size;
 }
+
+ulong write_pirq_routing_table(ulong addr)
+{
+	if (!gd->arch.pirq_routing_table)
+		return addr;
+
+	return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table);
+}