diff options
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/Kconfig | 5 | ||||
| -rw-r--r-- | arch/riscv/cpu/fu540/Kconfig | 2 | ||||
| -rw-r--r-- | arch/riscv/cpu/fu540/Makefile | 1 | ||||
| -rw-r--r-- | arch/riscv/cpu/fu540/cache.c | 55 | ||||
| -rw-r--r-- | arch/riscv/cpu/fu740/Kconfig | 2 | ||||
| -rw-r--r-- | arch/riscv/cpu/fu740/Makefile | 1 | ||||
| -rw-r--r-- | arch/riscv/cpu/fu740/cache.c | 55 | ||||
| -rw-r--r-- | arch/riscv/include/asm/arch-fu540/cache.h | 14 | ||||
| -rw-r--r-- | arch/riscv/include/asm/arch-fu740/cache.h | 14 | ||||
| -rw-r--r-- | arch/riscv/include/asm/cache.h | 2 | ||||
| -rw-r--r-- | arch/riscv/lib/Makefile | 1 | ||||
| -rw-r--r-- | arch/riscv/lib/cache.c | 4 | ||||
| -rw-r--r-- | arch/riscv/lib/interrupts.c | 33 | ||||
| -rw-r--r-- | arch/riscv/lib/sifive_cache.c | 27 |
14 files changed, 75 insertions, 141 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4b0c3dffa6..ec651fe0a4 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config SIFIVE_CACHE + bool + help + This enables the operations to configure SiFive cache + config ANDES_PLIC bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index 05463b2625..1604b412b4 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -19,6 +19,8 @@ config SIFIVE_FU540 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI + imply SIFIVE_CACHE + imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB imply MII diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 088205ef57..043fb961a5 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -8,5 +8,4 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o -obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c deleted file mode 100644 index 0fc4ef6c00..0000000000 --- a/arch/riscv/cpu/fu540/cache.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 SiFive, Inc - * - * Authors: - * Pragnesh Patel <pragnesh.patel@sifive.com> - */ - -#include <common.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <linux/bitops.h> - -/* Register offsets */ -#define L2_CACHE_CONFIG 0x000 -#define L2_CACHE_ENABLE 0x008 - -#define MASK_NUM_WAYS GENMASK(15, 8) -#define NUM_WAYS_SHIFT 8 - -DECLARE_GLOBAL_DATA_PTR; - -int cache_enable_ways(void) -{ - const void *blob = gd->fdt_blob; - int node; - fdt_addr_t base; - u32 config; - u32 ways; - - volatile u32 *enable; - - node = fdt_node_offset_by_compatible(blob, -1, - "sifive,fu540-c000-ccache"); - - if (node < 0) - return node; - - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, - NULL, false); - if (base == FDT_ADDR_T_NONE) - return FDT_ADDR_T_NONE; - - config = readl((volatile u32 *)base + L2_CACHE_CONFIG); - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; - - enable = (volatile u32 *)(base + L2_CACHE_ENABLE); - - /* memory barrier */ - mb(); - (*enable) = ways - 1; - /* memory barrier */ - mb(); - return 0; -} diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index 408195f149..049a0a0584 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -19,6 +19,8 @@ config SIFIVE_FU740 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI + imply SIFIVE_CACHE + imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB imply MII diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile index 5ef8ac18a7..1d1ad98ba7 100644 --- a/arch/riscv/cpu/fu740/Makefile +++ b/arch/riscv/cpu/fu740/Makefile @@ -8,5 +8,4 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o -obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c deleted file mode 100644 index 680955c9e3..0000000000 --- a/arch/riscv/cpu/fu740/cache.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020-2021 SiFive, Inc - * - * Authors: - * Pragnesh Patel <pragnesh.patel@sifive.com> - */ - -#include <common.h> -#include <asm/io.h> -#include <linux/bitops.h> -#include <asm/global_data.h> - -/* Register offsets */ -#define L2_CACHE_CONFIG 0x000 -#define L2_CACHE_ENABLE 0x008 - -#define MASK_NUM_WAYS GENMASK(15, 8) -#define NUM_WAYS_SHIFT 8 - -DECLARE_GLOBAL_DATA_PTR; - -int cache_enable_ways(void) -{ - const void *blob = gd->fdt_blob; - int node; - fdt_addr_t base; - u32 config; - u32 ways; - - volatile u32 *enable; - - node = fdt_node_offset_by_compatible(blob, -1, - "sifive,fu740-c000-ccache"); - - if (node < 0) - return node; - - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, - NULL, false); - if (base == FDT_ADDR_T_NONE) - return FDT_ADDR_T_NONE; - - config = readl((volatile u32 *)base + L2_CACHE_CONFIG); - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; - - enable = (volatile u32 *)(base + L2_CACHE_ENABLE); - - /* memory barrier */ - mb(); - (*enable) = ways - 1; - /* memory barrier */ - mb(); - return 0; -} diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h deleted file mode 100644 index 135a17c679..0000000000 --- a/arch/riscv/include/asm/arch-fu540/cache.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020 SiFive, Inc. - * - * Authors: - * Pragnesh Patel <pragnesh.patel@sifve.com> - */ - -#ifndef _CACHE_SIFIVE_H -#define _CACHE_SIFIVE_H - -int cache_enable_ways(void); - -#endif /* _CACHE_SIFIVE_H */ diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h deleted file mode 100644 index 7d4fe9942b..0000000000 --- a/arch/riscv/include/asm/arch-fu740/cache.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * - * Authors: - * Pragnesh Patel <pragnesh.patel@sifve.com> - */ - -#ifndef _CACHE_SIFIVE_H -#define _CACHE_SIFIVE_H - -int cache_enable_ways(void); - -#endif /* _CACHE_SIFIVE_H */ diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index ec8fe201d3..874963d731 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -8,7 +8,7 @@ #define _ASM_RISCV_CACHE_H /* cache */ -void cache_flush(void); +void cache_flush(void); /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index c4cc41434b..06020fcc2a 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index b1d42bcc2b..686e699efb 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -70,3 +70,7 @@ __weak int dcache_status(void) { return 0; } + +__weak void enable_caches(void) +{ +} diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 7525c152b8..100be2e966 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -51,6 +51,38 @@ static void show_regs(struct pt_regs *regs) #endif } +/** + * instr_len() - get instruction length + * + * @i: low 16 bits of the instruction + * Return: number of u16 in instruction + */ +static int instr_len(u16 i) +{ + if ((i & 0x03) != 0x03) + return 1; + /* Instructions with more than 32 bits are not yet specified */ + return 2; +} + +/** + * show_code() - display code leading to exception + * + * @epc: program counter + */ +static void show_code(ulong epc) +{ + u16 *pos = (u16 *)(epc & ~1UL); + int i, len = instr_len(*pos); + + printf("\nCode: "); + for (i = -8; i; ++i) + printf("%04x ", pos[i]); + printf("("); + for (i = 0; i < len; ++i) + printf("%04x%s", pos[i], i + 1 == len ? ")\n" : " "); +} + static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) { static const char * const exception_code[] = { @@ -85,6 +117,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) epc - gd->reloc_off, regs->ra - gd->reloc_off); show_regs(regs); + show_code(epc); show_efi_loaded_images(epc); panic("\n"); } diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c new file mode 100644 index 0000000000..28154878fc --- /dev/null +++ b/arch/riscv/lib/sifive_cache.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 SiFive, Inc + */ + +#include <common.h> +#include <cache.h> +#include <cpu_func.h> +#include <dm.h> + +void enable_caches(void) +{ + struct udevice *dev; + int ret; + + /* Enable ways of ccache */ + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(sifive_ccache), + &dev); + if (ret) { + log_debug("Cannot enable cache ways"); + } else { + ret = cache_enable(dev); + if (ret) + log_debug("ccache enable failed"); + } +} |