diff options
Diffstat (limited to 'arch/powerpc/dts/p2020-post.dtsi')
| -rw-r--r-- | arch/powerpc/dts/p2020-post.dtsi | 77 |
1 files changed, 51 insertions, 26 deletions
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 1c3f78798e..ea215ab075 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -13,35 +13,28 @@ compatible = "fsl,p2020-immr", "simple-bus"; bus-frequency = <0x0>; - usb@22000 { - compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; - reg = <0x22000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <28 0x2 0 0>; - phy_type = "ulpi"; + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; }; - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <4>; - reg = <0x40000 0x40000>; - compatible = "fsl,mpic"; - device_type = "open-pic"; - big-endian; - single-cpu-affinity; - last-interrupt-source = <255>; + ecm@1000 { + compatible = "fsl,p2020-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2 0 0>; }; - esdhc: sdhc@2e000 { - compatible = "fsl,p2020-esdhc", "fsl,esdhc"; - reg = <0x2e000 0x1000>; - interrupts = <72 0x2 0 0>; - /* Filled in by U-Boot */ - clock-frequency = <0>; + memory-controller@2000 { + compatible = "fsl,p2020-memory-controller"; + reg = <0x2000 0x1000>; + interrupts = <18 2 0 0>; }; +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" +/include/ "pq3-duart-0.dtsi" + espi0: spi@7000 { compatible = "fsl,mpc8536-espi"; #address-cells = <1>; @@ -51,9 +44,7 @@ fsl,espi-num-chipselects = <4>; }; -/include/ "pq3-i2c-0.dtsi" -/include/ "pq3-i2c-1.dtsi" -/include/ "pq3-duart-0.dtsi" +/include/ "pq3-dma-1.dtsi" /include/ "pq3-gpio-0.dtsi" L2: l2-cache-controller@20000 { @@ -64,6 +55,17 @@ interrupts = <16 2 0 0>; }; +/include/ "pq3-dma-0.dtsi" + + usb@22000 { + compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; + reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <28 0x2 0 0>; + phy_type = "ulpi"; + }; + /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-timer-0.dtsi" @@ -73,6 +75,29 @@ /include/ "pq3-etsec1-1.dtsi" /include/ "pq3-etsec1-2.dtsi" + + esdhc: sdhc@2e000 { + compatible = "fsl,p2020-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2 0 0>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; + +/include/ "pq3-sec3.1-0.dtsi" +/include/ "pq3-mpic.dtsi" +/include/ "pq3-mpic-timer-B.dtsi" + + global-utilities@e0000 { + compatible = "fsl,p2020-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + pmc: power@e0070 { + compatible = "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + }; }; /* PCIe controller base address 0x8000 */ |