diff options
Diffstat (limited to 'arch/arm/mach-rockchip')
| -rw-r--r-- | arch/arm/mach-rockchip/misc.c | 13 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/px30/Kconfig | 6 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/px30/px30.c | 81 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3308/rk3308.c | 37 |
4 files changed, 130 insertions, 7 deletions
diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c index f697e937c6..6dbb9bde48 100644 --- a/arch/arm/mach-rockchip/misc.c +++ b/arch/arm/mach-rockchip/misc.c @@ -30,7 +30,7 @@ int rockchip_setup_macaddr(void) /* Only generate a MAC address, if none is set in the environment */ if (env_get("ethaddr")) - return -1; + return 0; if (!cpuid) { debug("%s: could not retrieve 'cpuid#'\n", __func__); @@ -92,6 +92,7 @@ int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) char cpuid_str[cpuid_length * 2 + 1]; u64 serialno; char serialno_str[17]; + const char *oldid; int i; memset(cpuid_str, 0, sizeof(cpuid_str)); @@ -113,8 +114,16 @@ int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); + oldid = env_get("cpuid#"); + if (oldid && strcmp(oldid, cpuid_str) != 0) + printf("cpuid: value %s present in env does not match hardware %s\n", + oldid, cpuid_str); + env_set("cpuid#", cpuid_str); - env_set("serial#", serialno_str); + + /* Only generate serial# when none is set yet */ + if (!env_get("serial#")) + env_set("serial#", serialno_str); return 0; } diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 109a37be15..9f3ad4f623 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -27,12 +27,12 @@ config TPL_MAX_SIZE config TPL_STACK default 0xff0e4fff -config DEBUG_UART2_CHANNEL - int "Mux channel to use for debug UART2" +config DEBUG_UART_CHANNEL + int "Mux channel to use for debug UART2/UART3" depends on DEBUG_UART_BOARD_INIT default 0 help - UART2 can use two different set of pins to route the output. + UART2 and UART3 can use two different set of pins to route the output. For using the UART for early debugging the route to use needs to be declared (0 or 1). diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index bacdcc0b93..5014ee83d7 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -37,6 +37,7 @@ static struct mm_region px30_mem_map[] = { struct mm_region *mem_map = px30_mem_map; #define PMU_PWRDN_CON 0xff000018 +#define PMUGRF_BASE 0xff010000 #define GRF_BASE 0xff140000 #define CRU_BASE 0xff2b0000 #define VIDEO_PHY_BASE 0xff2e0000 @@ -49,6 +50,23 @@ struct mm_region *mem_map = px30_mem_map; #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) +/* GRF_GPIO1BH_IOMUX */ +enum { + GPIO1B7_SHIFT = 12, + GPIO1B7_MASK = 0xf << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_FLASH_RDN, + GPIO1B7_UART3_RXM1, + GPIO1B7_SPI0_CLK, + + GPIO1B6_SHIFT = 8, + GPIO1B6_MASK = 0xf << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_FLASH_CS1, + GPIO1B6_UART3_TXM1, + GPIO1B6_SPI0_CSN, +}; + /* GRF_GPIO1CL_IOMUX */ enum { GPIO1C1_SHIFT = 4, @@ -128,6 +146,23 @@ enum { GPIO3A1_UART5_RX = 4, }; +/* PMUGRF_GPIO0CL_IOMUX */ +enum { + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 0x3 << GPIO0C1_SHIFT, + GPIO0C1_GPIO = 0, + GPIO0C1_PWM_3, + GPIO0C1_UART3_RXM0, + GPIO0C1_PMU_DEBUG4, + + GPIO0C0_SHIFT = 0, + GPIO0C0_MASK = 0x3 << GPIO0C0_SHIFT, + GPIO0C0_GPIO = 0, + GPIO0C0_PWM_1, + GPIO0C0_UART3_TXM0, + GPIO0C0_PMU_DEBUG3, +}; + int arch_cpu_init(void) { static struct px30_grf * const grf = (void *)GRF_BASE; @@ -175,6 +210,11 @@ int arch_cpu_init(void) #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { +#if defined(CONFIG_DEBUG_UART_BASE) && \ + (CONFIG_DEBUG_UART_BASE == 0xff168000) && \ + (CONFIG_DEBUG_UART_CHANNEL != 1) + static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE; +#endif static struct px30_grf * const grf = (void *)GRF_BASE; static struct px30_cru * const cru = (void *)CRU_BASE; @@ -191,6 +231,43 @@ void board_debug_uart_init(void) GPIO1C1_MASK | GPIO1C0_MASK, GPIO1C1_UART1_TX << GPIO1C1_SHIFT | GPIO1C0_UART1_RX << GPIO1C0_SHIFT); +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff168000) + /* GRF_IOFUNC_CON0 */ + enum { + CON_IOMUX_UART3SEL_SHIFT = 9, + CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT, + CON_IOMUX_UART3SEL_M0 = 0, + CON_IOMUX_UART3SEL_M1, + }; + + /* uart_sel_clk default select 24MHz */ + rk_clrsetreg(&cru->clksel_con[40], + UART3_PLL_SEL_MASK | UART3_DIV_CON_MASK, + UART3_PLL_SEL_24M << UART3_PLL_SEL_SHIFT | 0); + rk_clrsetreg(&cru->clksel_con[41], + UART3_CLK_SEL_MASK, + UART3_CLK_SEL_UART3 << UART3_CLK_SEL_SHIFT); + +#if (CONFIG_DEBUG_UART_CHANNEL == 1) + rk_clrsetreg(&grf->iofunc_con0, + CON_IOMUX_UART3SEL_MASK, + CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1bh_iomux, + GPIO1B7_MASK | GPIO1B6_MASK, + GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT | + GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT); +#else + rk_clrsetreg(&grf->iofunc_con0, + CON_IOMUX_UART3SEL_MASK, + CON_IOMUX_UART3SEL_M0 << CON_IOMUX_UART3SEL_SHIFT); + + rk_clrsetreg(&pmugrf->gpio0cl_iomux, + GPIO0C1_MASK | GPIO0C0_MASK, + GPIO0C1_UART3_RXM0 << GPIO0C1_SHIFT | + GPIO0C0_UART3_TXM0 << GPIO0C0_SHIFT); +#endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */ + #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000) /* uart_sel_clk default select 24MHz */ rk_clrsetreg(&cru->clksel_con[46], @@ -222,7 +299,7 @@ void board_debug_uart_init(void) UART2_CLK_SEL_MASK, UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT); -#if (CONFIG_DEBUG_UART2_CHANNEL == 1) +#if (CONFIG_DEBUG_UART_CHANNEL == 1) /* Enable early UART2 */ rk_clrsetreg(&grf->iofunc_con0, CON_IOMUX_UART2SEL_MASK, @@ -241,7 +318,7 @@ void board_debug_uart_init(void) GPIO1D3_MASK | GPIO1D2_MASK, GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT | GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT); -#endif /* CONFIG_DEBUG_UART2_CHANNEL == 1 */ +#endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */ #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ } diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index f27f9e8c0b..b6815ddc55 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -72,6 +72,11 @@ enum { UART2_IO_SEL_M1, UART2_IO_SEL_USB, + GPIO2C0_SEL_SRC_CTRL_SHIFT = 11, + GPIO2C0_SEL_SRC_CTRL_MASK = BIT(11), + GPIO2C0_SEL_SRC_CTRL_IOMUX = 0, + GPIO2C0_SEL_SRC_CTRL_SEL_PLUS, + GPIO3B3_SEL_SRC_CTRL_SHIFT = 7, GPIO3B3_SEL_SRC_CTRL_MASK = BIT(7), GPIO3B3_SEL_SRC_CTRL_IOMUX = 0, @@ -97,6 +102,18 @@ enum { GPIO3B2_SEL_PLUS_EMMC_RSTN, GPIO3B2_SEL_PLUS_SPI1_MISO, GPIO3B2_SEL_PLUS_LCDC_D22_M1, + + I2C3_IOFUNC_SRC_CTRL_SHIFT = 10, + I2C3_IOFUNC_SRC_CTRL_MASK = BIT(10), + I2C3_IOFUNC_SRC_CTRL_SEL_PLUS = 1, + + GPIO2A3_SEL_SRC_CTRL_SHIFT = 7, + GPIO2A3_SEL_SRC_CTRL_MASK = BIT(7), + GPIO2A3_SEL_SRC_CTRL_SEL_PLUS = 1, + + GPIO2A2_SEL_SRC_CTRL_SHIFT = 3, + GPIO2A2_SEL_SRC_CTRL_MASK = BIT(3), + GPIO2A2_SEL_SRC_CTRL_SEL_PLUS = 1, }; enum { @@ -166,10 +183,30 @@ __weak void board_debug_uart_init(void) int arch_cpu_init(void) { static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE; + static struct rk3308_grf * const grf = (void *)GRF_BASE; /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */ rk_clrreg(&sgrf->con_secure0, 0x2b83); + /* + * Enable plus options to use more pinctrl functions, including + * GPIO2A2_PLUS, GPIO2A3_PLUS and I2C3_MULTI_SRC_PLUS. + */ + rk_clrsetreg(&grf->soc_con13, + I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK | + GPIO2A2_SEL_SRC_CTRL_MASK, + I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT | + GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT | + GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT); + + /* Plus options about GPIO3B2_PLUS, GPIO3B3_PLUS and GPIO2C0_PLUS. */ + rk_clrsetreg(&grf->soc_con15, + GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK | + GPIO3B2_SEL_SRC_CTRL_MASK, + GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT | + GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT | + GPIO3B2_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT); + return 0; } #endif |