diff options
Diffstat (limited to 'arch/arm/mach-k3/arm64-mmu.c')
| -rw-r--r-- | arch/arm/mach-k3/arm64-mmu.c | 59 |
1 files changed, 58 insertions, 1 deletions
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 95f830b7ff..a0da3df593 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -2,8 +2,9 @@ /* * K3: ARM64 MMU setup * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> + * Suman Anna <s-anna@ti.com> * (This file is derived from arch/arm/mach-zynqmp/cpu.c) * */ @@ -66,6 +67,8 @@ struct mm_region *mem_map = am654_mem_map; #endif /* CONFIG_SOC_K3_AM6 */ #ifdef CONFIG_SOC_K3_J721E + +#ifdef CONFIG_TARGET_J721E_A72_EVM /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6) @@ -122,4 +125,58 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = { }; struct mm_region *mem_map = j721e_mem_map; +#endif /* CONFIG_TARGET_J721E_A72_EVM */ + +#ifdef CONFIG_TARGET_J7200_A72_EVM +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) + +/* ToDo: Add 64bit IO */ +struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xa0000000UL, + .phys = 0xa0000000UL, + .size = 0x04800000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_NON_SHARE + }, { + .virt = 0xa4800000UL, + .phys = 0xa4800000UL, + .size = 0x5b800000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x500000000UL, + .phys = 0x500000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = j7200_mem_map; +#endif /* CONFIG_TARGET_J7200_A72_EVM */ + #endif /* CONFIG_SOC_K3_J721E */ |