diff options
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/ppa.h | 7 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 63 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h (renamed from arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h) | 15 | ||||
| -rw-r--r-- | arch/arm/include/asm/armv8/sec_firmware.h | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/fsl_secure_boot.h | 8 |
7 files changed, 92 insertions, 22 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index d9d948e2ab..70181c5077 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -48,10 +48,10 @@ enum srds_prtcl { SGMII14, SGMII15, SGMII16, - QSGMII_A, /* A indicates MACs 1-4 */ - QSGMII_B, /* B indicates MACs 5-8 */ - QSGMII_C, /* C indicates MACs 9-12 */ - QSGMII_D, /* D indicates MACs 12-16 */ + QSGMII_A, + QSGMII_B, + QSGMII_C, + QSGMII_D, SERDES_PRCTL_COUNT }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 08ea8fb8ef..80c421f710 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -230,10 +230,19 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +#if defined(CONFIG_ARCH_LS2080A) #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#endif #define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_MASK 0x00000400 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h index 1f1442b6f0..da4098ebd3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h @@ -7,10 +7,7 @@ #ifndef __FSL_PPA_H_ #define __FSL_PPA_H_ -#define SEC_FIRMWARE_FIT_IMAGE "firmware" -#define SEC_FIRMEWARE_FIT_CNF_NAME "config@1" -#define SEC_FIRMWARE_TARGET_EL 2 - +#ifdef CONFIG_FSL_LS_PPA int ppa_init(void); - +#endif #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h new file mode 100644 index 0000000000..b326fe5c40 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -0,0 +1,63 @@ +/* + * Copyright 2017 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices + * are not hardwired and are programmed by sw. There are a limited number + * of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, PCI, + * and DPAA1 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * -set a iommu-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt + * for more info on the iommu-map definition) + * + * -DPAA1 + * - Stream ids for DPAA1 use are reserved for future usecase. + * + */ + + +#define FSL_INVALID_STREAM_ID 0 + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9 + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 11 +#define FSL_PEX_STREAM_ID_END 26 + +/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END 63 + +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index ee28323f8c..d7d527d8f4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -8,11 +8,11 @@ #define __FSL_STREAM_ID_H /* - * Stream IDs on ls2080a devices are not hardwired and are - * programmed by sw. There are a limited number of stream IDs - * available, and the partitioning of them is scenario dependent. - * This header defines the partitioning between legacy, PCI, - * and DPAA2 devices. + * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a) + * devices are not hardwired and are programmed by sw. There are a limited + * number of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, + * PCI, and DPAA2 devices. * * This partitioning can be customized in this file depending * on the specific hardware config: @@ -29,6 +29,9 @@ * -set a msi-map entry in the PEXn controller node in the * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt * for more info on the msi-map definition) + * -set a iommu-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt + * for more info on the iommu-map definition) * * -DPAA2 * -u-boot will allocate a range of stream IDs to be used by the Management @@ -36,7 +39,7 @@ * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * - * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for + * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bit streamID bit diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h index 5ae00fa8d2..bcdb1b0072 100644 --- a/arch/arm/include/asm/armv8/sec_firmware.h +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -7,10 +7,6 @@ #ifndef __SEC_FIRMWARE_H_ #define __SEC_FIRMWARE_H_ -#ifdef CONFIG_FSL_LS_PPA -#include <asm/arch/ppa.h> -#endif - int sec_firmware_init(const void *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *); bool sec_firmware_is_valid(const void *); diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index fd627c0874..d98a1e8f89 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -38,11 +38,11 @@ * in boot ROM of the SoC. * The feature is only applicable in case of NOR boot and is * not applicable in case of RAMBOOT (NAND, SD, SPI). + * For LS, this feature is available for all device if IE Table + * is copied to XIP memory + * Also, for LS, ISBC doesn't verify this table. */ -#ifndef CONFIG_ESBC_HDR_LS -/* Current Key EXT feature not available in LS ESBC Header */ #define CONFIG_FSL_ISBC_KEY_EXT -#endif #endif @@ -112,6 +112,8 @@ #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP #ifdef CONFIG_LS1043A #define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000 +#elif defined(CONFIG_FSL_LSCH3) +#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x580c40000 #endif #else #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined" |