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-rw-r--r--arch/arm/include/asm/arch-imxrt/imx-regs.h6
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6-ddr.h19
-rw-r--r--arch/arm/include/asm/mach-imx/regs-lcdif.h6
3 files changed, 28 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h
index 4f1d439f6f..44c95dcd11 100644
--- a/arch/arm/include/asm/arch-imxrt/imx-regs.h
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -17,4 +17,10 @@
#define ANATOP_BASE_ADDR 0x400d8000
+#define MXS_LCDIF_BASE 0x402b8000
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/mach-imx/regs-lcdif.h>
+#endif
+
#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index e0fadb9b1c..dbc97b25df 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -306,6 +306,25 @@ struct mx6dq_iomux_grp_regs {
u32 grp_b6ds;
};
+/*
+ * NoC scheduler registers - only on IMX6DQP
+ */
+#define MX6DQP_NOC_SCHED_BASE 0x00bb0000
+struct mx6dqp_noc_sched_regs {
+ u32 coreid;
+ u32 revid;
+ u32 ddrconf;
+ u32 ddrtiming;
+ u32 ddrmode;
+ u32 rlat;
+ u32 res1[4];
+ u32 ipu1;
+ u32 ipu2;
+ u32 res2[2];
+ u32 activate;
+ u32 res3[16];
+};
+
#define MX6SDL_IOM_DDR_BASE 0x020e0400
struct mx6sdl_iomux_ddr_regs {
u32 res1[25];
diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h
index b4c430a35c..5874638796 100644
--- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
+++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
@@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
- defined(CONFIG_IMX8M)
+ defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -49,7 +49,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
- mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
+ mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
#if defined(CONFIG_MX23)
@@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
- defined(CONFIG_IMX8M)
+ defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */