diff options
Diffstat (limited to 'arch/arm/dts/sun50i-h5.dtsi')
| -rw-r--r-- | arch/arm/dts/sun50i-h5.dtsi | 38 |
1 files changed, 30 insertions, 8 deletions
diff --git a/arch/arm/dts/sun50i-h5.dtsi b/arch/arm/dts/sun50i-h5.dtsi index c052f31131..4e4738cab0 100644 --- a/arch/arm/dts/sun50i-h5.dtsi +++ b/arch/arm/dts/sun50i-h5.dtsi @@ -1,17 +1,17 @@ /* - * Copyright (c) 2016 ARM Ltd. + * Copyright (C) 2016 ARM Ltd. * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * - * a) This library is free software; you can redistribute it and/or + * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * - * This library is distributed in the hope that it will be useful, + * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. @@ -40,24 +40,38 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "sun8i-h3.dtsi" +#include <sunxi-h3-h5.dtsi> / { cpus { - cpu@0 { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0>; enable-method = "psci"; }; + cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <1>; enable-method = "psci"; }; + cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <2>; enable-method = "psci"; }; + cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <3>; enable-method = "psci"; }; }; @@ -69,6 +83,14 @@ timer { compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; }; @@ -76,8 +98,8 @@ compatible = "allwinner,sun50i-h5-ccu"; }; -&gic { - compatible = "arm,gic-400"; +&display_clocks { + compatible = "allwinner,sun50i-h5-de2-clk"; }; &mmc0 { @@ -104,6 +126,6 @@ &pio { interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; compatible = "allwinner,sun50i-h5-pinctrl"; }; |