diff options
Diffstat (limited to 'arch/arm/dts/k3-j721e.dtsi')
| -rw-r--r-- | arch/arm/dts/k3-j721e.dtsi | 29 |
1 files changed, 12 insertions, 17 deletions
diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi index b2670752dc..84693fce65 100644 --- a/arch/arm/dts/k3-j721e.dtsi +++ b/arch/arm/dts/k3-j721e.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J721E SoC Family * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/interrupt-controller/irq.h> @@ -30,18 +30,7 @@ serial9 = &main_uart7; serial10 = &main_uart8; serial11 = &main_uart9; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &mcu_i2c1; - i2c3 = &main_i2c0; - i2c4 = &main_i2c1; - i2c5 = &main_i2c2; - i2c6 = &main_i2c3; - i2c7 = &main_i2c4; - i2c8 = &main_i2c5; - i2c9 = &main_i2c6; - spi0 = &ospi0; - spi1 = &ospi1; + ethernet0 = &cpsw_port1; }; chosen { }; @@ -139,15 +128,22 @@ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ + <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ + <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ - <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ + /* MCUSS_WKUP Range */ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, @@ -160,7 +156,6 @@ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; |