diff options
Diffstat (limited to 'arch/arm/dts/bcm6856.dtsi')
| -rw-r--r-- | arch/arm/dts/bcm6856.dtsi | 150 |
1 files changed, 150 insertions, 0 deletions
diff --git a/arch/arm/dts/bcm6856.dtsi b/arch/arm/dts/bcm6856.dtsi index 0bce649721..99185ab0bc 100644 --- a/arch/arm/dts/bcm6856.dtsi +++ b/arch/arm/dts/bcm6856.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* + * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com> * Copyright 2022 Broadcom Ltd. */ @@ -54,11 +55,29 @@ }; clocks: clocks { + u-boot,dm-pre-reloc; + periph_clk:periph-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-mult = <2>; + clock-div = <1>; + }; + + wdt_clk: wdt-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; }; psci { @@ -90,6 +109,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>; + u-boot,dm-pre-reloc; uart0: serial@640 { compatible = "brcm,bcm6345-uart"; @@ -99,5 +119,135 @@ clock-names = "refclk"; status = "disabled"; }; + + wdt1: watchdog@480 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x480 0x14>; + clocks = <&wdt_clk>; + }; + + wdt2: watchdog@4c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x4c0 0x14>; + clocks = <&wdt_clk>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt1>; + }; + + leds: led-controller@800 { + compatible = "brcm,bcm6858-leds"; + reg = <0x800 0xe4>; + + status = "disabled"; + }; + + gpio0: gpio-controller@500 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x500 0x4>, + <0x520 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio1: gpio-controller@504 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x504 0x4>, + <0x524 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio2: gpio-controller@508 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x508 0x4>, + <0x528 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio3: gpio-controller@50c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x50c 0x4>, + <0x52c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio4: gpio-controller@510 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x510 0x4>, + <0x530 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio5: gpio-controller@514 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x514 0x4>, + <0x534 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio6: gpio-controller@518 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x518 0x4>, + <0x538 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio7: gpio-controller@51c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x51c 0x4>, + <0x53c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + hsspi: spi-controller@1000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + spi-max-frequency = <100000000>; + num-cs = <8>; + + status = "disabled"; + }; + + nand: nand-controller@1800 { + compatible = "brcm,nand-bcm68360", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x1800 0x180>, + <0x2000 0x10>, + <0x1c00 0x200>; + parameter-page-big-endian = <0>; + + status = "disabled"; + }; }; }; |