diff options
70 files changed, 1293 insertions, 79 deletions
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 67edf94520..19c771dba3 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -53,6 +53,11 @@ _bss_end_ofs: .quad __bss_end - _start reset: + /* Allow the board to save important registers */ + b save_boot_params +.globl save_boot_params_ret +save_boot_params_ret: + #ifdef CONFIG_SYS_RESET_SCTRL bl reset_sctrl #endif @@ -282,3 +287,7 @@ ENTRY(c_runtime_cpu_setup) ret ENDPROC(c_runtime_cpu_setup) + +WEAK(save_boot_params) + b save_boot_params_ret /* back to my caller */ +ENDPROC(save_boot_params) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index acecb7c359..ca8712a7a7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -53,7 +53,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \ - tegra186-p2771-0000.dtb \ + tegra186-p2771-0000-a02.dtb \ + tegra186-p2771-0000-b00.dtb \ tegra210-e2220-1170.dtb \ tegra210-p2371-0000.dtb \ tegra210-p2371-2180.dtb \ diff --git a/arch/arm/dts/tegra186-p2771-0000-a02.dts b/arch/arm/dts/tegra186-p2771-0000-a02.dts new file mode 100644 index 0000000000..70f4326c09 --- /dev/null +++ b/arch/arm/dts/tegra186-p2771-0000-a02.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "tegra186-p2771-0000.dtsi" + +/ { + model = "NVIDIA P2771-0000 A02"; + compatible = "nvidia,p2771-0000-a02", "nvidia,p2771-0000", "nvidia,tegra186"; +}; diff --git a/arch/arm/dts/tegra186-p2771-0000-b00.dts b/arch/arm/dts/tegra186-p2771-0000-b00.dts new file mode 100644 index 0000000000..2384a65e87 --- /dev/null +++ b/arch/arm/dts/tegra186-p2771-0000-b00.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "tegra186-p2771-0000.dtsi" + +/ { + model = "NVIDIA P2771-0000 B00"; + compatible = "nvidia,p2771-0000-b00", "nvidia,p2771-0000", "nvidia,tegra186"; +}; diff --git a/arch/arm/dts/tegra186-p2771-0000.dts b/arch/arm/dts/tegra186-p2771-0000.dtsi index 5f29ee4501..87f0427e80 100644 --- a/arch/arm/dts/tegra186-p2771-0000.dts +++ b/arch/arm/dts/tegra186-p2771-0000.dtsi @@ -1,5 +1,3 @@ -/dts-v1/; - #include "tegra186.dtsi" / { diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index fce34fa650..99d49254b3 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -1,5 +1,5 @@ #include "skeleton.dtsi" -#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/gpio/tegra186-gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/tegra-hsp.h> diff --git a/arch/arm/include/asm/arch-tegra/ivc.h b/arch/arm/include/asm/arch-tegra/ivc.h new file mode 100644 index 0000000000..7f2287ae28 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/ivc.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_TEGRA_IVC_H +#define _ASM_ARCH_TEGRA_IVC_H + +#include <common.h> + +/* + * Tegra IVC is a communication protocol that transfers fixed-size frames + * bi-directionally and in-order between the local CPU and some remote entity. + * Communication is via a statically sized and allocated buffer in shared + * memory and a notification mechanism. + * + * This API handles all aspects of the shared memory buffer's metadata, and + * leaves all aspects of the frame content to the calling code; frames + * typically contain some higher-level protocol. The notification mechanism is + * also handled externally to this API, since it can vary from instance to + * instance. + * + * The client model is to first find some free (for TX) or filled (for RX) + * frame, process that frame's memory buffer (fill or read it), and then + * inform the protocol that the frame has been filled/read, i.e. advance the + * write/read pointer. If the channel is full, there may be no available frames + * to fill/read. In this case, client code may either poll for an available + * frame, or wait for the remote entity to send a notification to the local + * CPU. + */ + +/** + * struct tegra_ivc - In-memory shared memory layout. + * + * This is described in detail in ivc.c. + */ +struct tegra_ivc_channel_header; + +/** + * struct tegra_ivc - Software state of an IVC channel. + * + * This state is internal to the IVC code and should not be accessed directly + * by clients. It is public solely so clients can allocate storage for the + * structure. + */ +struct tegra_ivc { + /** + * rx_channel - Pointer to the shared memory region used to receive + * messages from the remote entity. + */ + struct tegra_ivc_channel_header *rx_channel; + /** + * tx_channel - Pointer to the shared memory region used to send + * messages to the remote entity. + */ + struct tegra_ivc_channel_header *tx_channel; + /** + * r_pos - The position in list of frames in rx_channel that we are + * reading from. + */ + uint32_t r_pos; + /** + * w_pos - The position in list of frames in tx_channel that we are + * writing to. + */ + uint32_t w_pos; + /** + * nframes - The number of frames allocated (in each direction) in + * shared memory. + */ + uint32_t nframes; + /** + * frame_size - The size of each frame in shared memory. + */ + uint32_t frame_size; + /** + * notify - Function to call to notify the remote processor of a + * change in channel state. + */ + void (*notify)(struct tegra_ivc *); +}; + +/** + * tegra_ivc_read_get_next_frame - Locate the next frame to receive. + * + * Locate the next frame to be received/processed, return the address of the + * frame, and do not remove it from the queue. Repeated calls to this function + * will return the same address until tegra_ivc_read_advance() is called. + * + * @ivc The IVC channel. + * @frame Pointer to be filled with the address of the frame to receive. + * + * @return 0 if a frame is available, else a negative error code. + */ +int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame); + +/** + * tegra_ivc_read_advance - Advance the read queue. + * + * Inform the protocol and remote entity that the frame returned by + * tegra_ivc_read_get_next_frame() has been processed. The remote end may then + * re-use it to transmit further data. Subsequent to this function returning, + * tegra_ivc_read_get_next_frame() will return a different frame. + * + * @ivc The IVC channel. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_read_advance(struct tegra_ivc *ivc); + +/** + * tegra_ivc_write_get_next_frame - Locate the next frame to fill for transmit. + * + * Locate the next frame to be filled for transmit, return the address of the + * frame, and do not add it to the queue. Repeated calls to this function + * will return the same address until tegra_ivc_read_advance() is called. + * + * @ivc The IVC channel. + * @frame Pointer to be filled with the address of the frame to fill. + * + * @return 0 if a frame is available, else a negative error code. + */ +int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame); + +/** + * tegra_ivc_write_advance - Advance the write queue. + * + * Inform the protocol and remote entity that the frame returned by + * tegra_ivc_write_get_next_frame() has been filled and should be transmitted. + * The remote end may then read data from it. Subsequent to this function + * returning, tegra_ivc_write_get_next_frame() will return a different frame. + * + * @ivc The IVC channel. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_write_advance(struct tegra_ivc *ivc); + +/** + * tegra_ivc_channel_notified - handle internal messages + * + * This function must be called following every notification. + * + * @ivc The IVC channel. + * + * @return 0 if the channel is ready for communication, or -EAGAIN if a + * channel reset is in progress. + */ +int tegra_ivc_channel_notified(struct tegra_ivc *ivc); + +/** + * tegra_ivc_channel_reset - initiates a reset of the shared memory state + * + * This function must be called after a channel is initialized but before it + * is used for communication. The channel will be ready for use when a + * subsequent call to notify the remote of the channel reset indicates the + * reset operation is complete. + * + * @ivc The IVC channel. + */ +void tegra_ivc_channel_reset(struct tegra_ivc *ivc); + +/** + * tegra_ivc_init - Initialize a channel's software state. + * + * @ivc The IVC channel. + * @rx_base Address of the the RX shared memory buffer. + * @tx_base Address of the the TX shared memory buffer. + * @nframes Number of frames in each shared memory buffer. + * @frame_size Size of each frame. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base, + uint32_t nframes, uint32_t frame_size, + void (*notify)(struct tegra_ivc *)); + +#endif diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index f4affa5512..85ae3b7f42 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,5 +1,13 @@ if TEGRA +config TEGRA_IVC + bool "Tegra IVC protocol" + help + IVC (Inter-VM Communication) protocol is a Tegra-specific IPC + (Inter Processor Communication) framework. Within the context of + U-Boot, it is typically used for communication between the main CPU + and various auxiliary processors. + config TEGRA_COMMON bool "Tegra common options" select DM @@ -60,6 +68,7 @@ config TEGRA186 select TEGRA186_GPIO select TEGRA_ARMV8_COMMON select TEGRA_HSP + select TEGRA_IVC endchoice diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 12ee1cd749..d0bf5a6e75 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -15,23 +15,24 @@ else obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o endif -obj-$(CONFIG_ARM64) += arm64-mmu.o obj-y += ap.o obj-y += board.o board2.o obj-y += cache.o obj-y += clock.o -obj-y += lowlevel_init.o obj-y += pinmux-common.o obj-y += powergate.o obj-y += xusb-padctl-dummy.o -obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o -obj-$(CONFIG_TEGRA_GPU) += gpu.o -obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +endif +obj-$(CONFIG_ARM64) += arm64-mmu.o +obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +obj-$(CONFIG_TEGRA_GPU) += gpu.o +obj-$(CONFIG_TEGRA_IVC) += ivc.o +obj-y += lowlevel_init.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif -endif +obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_TEGRA30) += tegra30/ diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c index f4b6152a79..876ccba5e5 100644 --- a/arch/arm/mach-tegra/board186.c +++ b/arch/arm/mach-tegra/board186.c @@ -11,12 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int dram_init(void) -{ - gd->ram_size = (1.5 * 1024 * 1024 * 1024); - return 0; -} - int board_early_init_f(void) { return 0; @@ -32,12 +26,6 @@ int board_late_init(void) return 0; } -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; -} - void pad_init_mmc(struct mmc_host *host) { } diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c new file mode 100644 index 0000000000..cf6626fb12 --- /dev/null +++ b/arch/arm/mach-tegra/ivc.c @@ -0,0 +1,553 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-tegra/ivc.h> + +#define TEGRA_IVC_ALIGN 64 + +/* + * IVC channel reset protocol. + * + * Each end uses its tx_channel.state to indicate its synchronization state. + */ +enum ivc_state { + /* + * This value is zero for backwards compatibility with services that + * assume channels to be initially zeroed. Such channels are in an + * initially valid state, but cannot be asynchronously reset, and must + * maintain a valid state at all times. + * + * The transmitting end can enter the established state from the sync or + * ack state when it observes the receiving endpoint in the ack or + * established state, indicating that has cleared the counters in our + * rx_channel. + */ + ivc_state_established = 0, + + /* + * If an endpoint is observed in the sync state, the remote endpoint is + * allowed to clear the counters it owns asynchronously with respect to + * the current endpoint. Therefore, the current endpoint is no longer + * allowed to communicate. + */ + ivc_state_sync, + + /* + * When the transmitting end observes the receiving end in the sync + * state, it can clear the w_count and r_count and transition to the ack + * state. If the remote endpoint observes us in the ack state, it can + * return to the established state once it has cleared its counters. + */ + ivc_state_ack +}; + +/* + * This structure is divided into two-cache aligned parts, the first is only + * written through the tx_channel pointer, while the second is only written + * through the rx_channel pointer. This delineates ownership of the cache lines, + * which is critical to performance and necessary in non-cache coherent + * implementations. + */ +struct tegra_ivc_channel_header { + union { + /* fields owned by the transmitting end */ + struct { + uint32_t w_count; + uint32_t state; + }; + uint8_t w_align[TEGRA_IVC_ALIGN]; + }; + union { + /* fields owned by the receiving end */ + uint32_t r_count; + uint8_t r_align[TEGRA_IVC_ALIGN]; + }; +}; + +static inline void tegra_ivc_invalidate_counter(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + ulong offset) +{ + ulong base = ((ulong)h) + offset; + invalidate_dcache_range(base, base + TEGRA_IVC_ALIGN); +} + +static inline void tegra_ivc_flush_counter(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + ulong offset) +{ + ulong base = ((ulong)h) + offset; + flush_dcache_range(base, base + TEGRA_IVC_ALIGN); +} + +static inline ulong tegra_ivc_frame_addr(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + uint32_t frame) +{ + BUG_ON(frame >= ivc->nframes); + + return ((ulong)h) + sizeof(struct tegra_ivc_channel_header) + + (ivc->frame_size * frame); +} + +static inline void *tegra_ivc_frame_pointer(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch, + uint32_t frame) +{ + return (void *)tegra_ivc_frame_addr(ivc, ch, frame); +} + +static inline void tegra_ivc_invalidate_frame(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + unsigned frame) +{ + ulong base = tegra_ivc_frame_addr(ivc, h, frame); + invalidate_dcache_range(base, base + ivc->frame_size); +} + +static inline void tegra_ivc_flush_frame(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + unsigned frame) +{ + ulong base = tegra_ivc_frame_addr(ivc, h, frame); + flush_dcache_range(base, base + ivc->frame_size); +} + +static inline int tegra_ivc_channel_empty(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch) +{ + /* + * This function performs multiple checks on the same values with + * security implications, so create snapshots with ACCESS_ONCE() to + * ensure that these checks use the same values. + */ + uint32_t w_count = ACCESS_ONCE(ch->w_count); + uint32_t r_count = ACCESS_ONCE(ch->r_count); + + /* + * Perform an over-full check to prevent denial of service attacks where + * a server could be easily fooled into believing that there's an + * extremely large number of frames ready, since receivers are not + * expected to check for full or over-full conditions. + * + * Although the channel isn't empty, this is an invalid case caused by + * a potentially malicious peer, so returning empty is safer, because it + * gives the impression that the channel has gone silent. + */ + if (w_count - r_count > ivc->nframes) + return 1; + + return w_count == r_count; +} + +static inline int tegra_ivc_channel_full(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch) +{ + /* + * Invalid cases where the counters indicate that the queue is over + * capacity also appear full. + */ + return (ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count)) >= + ivc->nframes; +} + +static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc) +{ + ACCESS_ONCE(ivc->rx_channel->r_count) = + ACCESS_ONCE(ivc->rx_channel->r_count) + 1; + + if (ivc->r_pos == ivc->nframes - 1) + ivc->r_pos = 0; + else + ivc->r_pos++; +} + +static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc) +{ + ACCESS_ONCE(ivc->tx_channel->w_count) = + ACCESS_ONCE(ivc->tx_channel->w_count) + 1; + + if (ivc->w_pos == ivc->nframes - 1) + ivc->w_pos = 0; + else + ivc->w_pos++; +} + +static inline int tegra_ivc_check_read(struct tegra_ivc *ivc) +{ + ulong offset; + + /* + * tx_channel->state is set locally, so it is not synchronized with + * state from the remote peer. The remote peer cannot reset its + * transmit counters until we've acknowledged its synchronization + * request, so no additional synchronization is required because an + * asynchronous transition of rx_channel->state to ivc_state_ack is not + * allowed. + */ + if (ivc->tx_channel->state != ivc_state_established) + return -ECONNRESET; + + /* + * Avoid unnecessary invalidations when performing repeated accesses to + * an IVC channel by checking the old queue pointers first. + * Synchronization is only necessary when these pointers indicate empty + * or full. + */ + if (!tegra_ivc_channel_empty(ivc, ivc->rx_channel)) + return 0; + + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset); + return tegra_ivc_channel_empty(ivc, ivc->rx_channel) ? -ENOMEM : 0; +} + +static inline int tegra_ivc_check_write(struct tegra_ivc *ivc) +{ + ulong offset; + + if (ivc->tx_channel->state != ivc_state_established) + return -ECONNRESET; + + if (!tegra_ivc_channel_full(ivc, ivc->tx_channel)) + return 0; + + offset = offsetof(struct tegra_ivc_channel_header, r_count); + tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset); + return tegra_ivc_channel_full(ivc, ivc->tx_channel) ? -ENOMEM : 0; +} + +static inline uint32_t tegra_ivc_channel_avail_count(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch) +{ + /* + * This function isn't expected to be used in scenarios where an + * over-full situation can lead to denial of service attacks. See the + * comment in tegra_ivc_channel_empty() for an explanation about + * special over-full considerations. + */ + return ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count); +} + +int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame) +{ + int result = tegra_ivc_check_read(ivc); + if (result < 0) + return result; + + /* + * Order observation of w_pos potentially indicating new data before + * data read. + */ + mb(); + + tegra_ivc_invalidate_frame(ivc, ivc->rx_channel, ivc->r_pos); + *frame = tegra_ivc_frame_pointer(ivc, ivc->rx_channel, ivc->r_pos); + + return 0; +} + +int tegra_ivc_read_advance(struct tegra_ivc *ivc) +{ + ulong offset; + int result; + + /* + * No read barriers or synchronization here: the caller is expected to + * have already observed the channel non-empty. This check is just to + * catch programming errors. + */ + result = tegra_ivc_check_read(ivc); + if (result) + return result; + + tegra_ivc_advance_rx(ivc); + offset = offsetof(struct tegra_ivc_channel_header, r_count); + tegra_ivc_flush_counter(ivc, ivc->rx_channel, offset); + + /* + * Ensure our write to r_pos occurs before our read from w_pos. + */ + mb(); + + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset); + + if (tegra_ivc_channel_avail_count(ivc, ivc->rx_channel) == + ivc->nframes - 1) + ivc->notify(ivc); + + return 0; +} + +int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame) +{ + int result = tegra_ivc_check_write(ivc); + if (result) + return result; + + *frame = tegra_ivc_frame_pointer(ivc, ivc->tx_channel, ivc->w_pos); + + return 0; +} + +int tegra_ivc_write_advance(struct tegra_ivc *ivc) +{ + ulong offset; + int result; + + result = tegra_ivc_check_write(ivc); + if (result) + return result; + + tegra_ivc_flush_frame(ivc, ivc->tx_channel, ivc->w_pos); + + /* + * Order any possible stores to the frame before update of w_pos. + */ + mb(); + + tegra_ivc_advance_tx(ivc); + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Ensure our write to w_pos occurs before our read from r_pos. + */ + mb(); + + offset = offsetof(struct tegra_ivc_channel_header, r_count); + tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset); + + if (tegra_ivc_channel_avail_count(ivc, ivc->tx_channel) == 1) + ivc->notify(ivc); + + return 0; +} + +/* + * =============================================================== + * IVC State Transition Table - see tegra_ivc_channel_notified() + * =============================================================== + * + * local remote action + * ----- ------ ----------------------------------- + * SYNC EST <none> + * SYNC ACK reset counters; move to EST; notify + * SYNC SYNC reset counters; move to ACK; notify + * ACK EST move to EST; notify + * ACK ACK move to EST; notify + * ACK SYNC reset counters; move to ACK; notify + * EST EST <none> + * EST ACK <none> + * EST SYNC reset counters; move to ACK; notify + * + * =============================================================== + */ +int tegra_ivc_channel_notified(struct tegra_ivc *ivc) +{ + ulong offset; + enum ivc_state peer_state; + + /* Copy the receiver's state out of shared memory. */ + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset); + peer_state = ACCESS_ONCE(ivc->rx_channel->state); + + if (peer_state == ivc_state_sync) { + /* + * Order observation of ivc_state_sync before stores clearing + * tx_channel. + */ + mb(); + + /* + * Reset tx_channel counters. The remote end is in the SYNC + * state and won't make progress until we change our state, + * so the counters are not in use at this time. + */ + ivc->tx_channel->w_count = 0; + ivc->rx_channel->r_count = 0; + + ivc->w_pos = 0; + ivc->r_pos = 0; + + /* + * Ensure that counters appear cleared before new state can be + * observed. + */ + mb(); + + /* + * Move to ACK state. We have just cleared our counters, so it + * is now safe for the remote end to start using these values. + */ + ivc->tx_channel->state = ivc_state_ack; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Notify remote end to observe state transition. + */ + ivc->notify(ivc); + } else if (ivc->tx_channel->state == ivc_state_sync && + peer_state == ivc_state_ack) { + /* + * Order observation of ivc_state_sync before stores clearing + * tx_channel. + */ + mb(); + + /* + * Reset tx_channel counters. The remote end is in the ACK + * state and won't make progress until we change our state, + * so the counters are not in use at this time. + */ + ivc->tx_channel->w_count = 0; + ivc->rx_channel->r_count = 0; + + ivc->w_pos = 0; + ivc->r_pos = 0; + + /* + * Ensure that counters appear cleared before new state can be + * observed. + */ + mb(); + + /* + * Move to ESTABLISHED state. We know that the remote end has + * already cleared its counters, so it is safe to start + * writing/reading on this channel. + */ + ivc->tx_channel->state = ivc_state_established; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Notify remote end to observe state transition. + */ + ivc->notify(ivc); + } else if (ivc->tx_channel->state == ivc_state_ack) { + /* + * At this point, we have observed the peer to be in either + * the ACK or ESTABLISHED state. Next, order observation of + * peer state before storing to tx_channel. + */ + mb(); + + /* + * Move to ESTABLISHED state. We know that we have previously + * cleared our counters, and we know that the remote end has + * cleared its counters, so it is safe to start writing/reading + * on this channel. + */ + ivc->tx_channel->state = ivc_state_established; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Notify remote end to observe state transition. + */ + ivc->notify(ivc); + } else { + /* + * There is no need to handle any further action. Either the + * channel is already fully established, or we are waiting for + * the remote end to catch up with our current state. Refer + * to the diagram in "IVC State Transition Table" above. + */ + } + + if (ivc->tx_channel->state != ivc_state_established) + return -EAGAIN; + + return 0; +} + +void tegra_ivc_channel_reset(struct tegra_ivc *ivc) +{ + ulong offset; + + ivc->tx_channel->state = ivc_state_sync; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + ivc->notify(ivc); +} + +static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes, + uint32_t frame_size) +{ + int ret = 0; + + BUG_ON(offsetof(struct tegra_ivc_channel_header, w_count) & + (TEGRA_IVC_ALIGN - 1)); + BUG_ON(offsetof(struct tegra_ivc_channel_header, r_count) & + (TEGRA_IVC_ALIGN - 1)); + BUG_ON(sizeof(struct tegra_ivc_channel_header) & + (TEGRA_IVC_ALIGN - 1)); + + if ((uint64_t)nframes * (uint64_t)frame_size >= 0x100000000) { + error("tegra_ivc: nframes * frame_size overflows\n"); + return -EINVAL; + } + + /* + * The headers must at least be aligned enough for counters + * to be accessed atomically. + */ + if ((qbase1 & (TEGRA_IVC_ALIGN - 1)) || + (qbase2 & (TEGRA_IVC_ALIGN - 1))) { + error("tegra_ivc: channel start not aligned\n"); + return -EINVAL; + } + + if (frame_size & (TEGRA_IVC_ALIGN - 1)) { + error("tegra_ivc: frame size not adequately aligned\n"); + return -EINVAL; + } + + if (qbase1 < qbase2) { + if (qbase1 + frame_size * nframes > qbase2) + ret = -EINVAL; + } else { + if (qbase2 + frame_size * nframes > qbase1) + ret = -EINVAL; + } + + if (ret) { + error("tegra_ivc: queue regions overlap\n"); + return ret; + } + + return 0; +} + +int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base, + uint32_t nframes, uint32_t frame_size, + void (*notify)(struct tegra_ivc *)) +{ + int ret; + + if (!ivc) + return -EINVAL; + + ret = check_ivc_params(rx_base, tx_base, nframes, frame_size); + if (ret) + return ret; + + ivc->rx_channel = (struct tegra_ivc_channel_header *)rx_base; + ivc->tx_channel = (struct tegra_ivc_channel_header *)tx_base; + ivc->w_pos = 0; + ivc->r_pos = 0; + ivc->nframes = nframes; + ivc->frame_size = frame_size; + ivc->notify = notify; + + return 0; +} diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile index ce4610d8f8..033d6005fb 100644 --- a/arch/arm/mach-tegra/tegra186/Makefile +++ b/arch/arm/mach-tegra/tegra186/Makefile @@ -2,7 +2,6 @@ # # SPDX-License-Identifier: GPL-2.0 -obj-y += ../arm64-mmu.o obj-y += ../board186.o -obj-y += ../lowlevel_init.o -obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o +obj-y += nvtboot_ll.o +obj-y += nvtboot_mem.o diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S new file mode 100644 index 0000000000..1eab890958 --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S @@ -0,0 +1,20 @@ +/* + * Save nvtboot-related boot-time CPU state + * + * (C) Copyright 2015-2016 NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +.globl nvtboot_boot_x0 +nvtboot_boot_x0: + .dword 0 + +ENTRY(save_boot_params) + adr x8, nvtboot_boot_x0 + str x0, [x8] + b save_boot_params_ret +ENDPROC(save_boot_params) diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c new file mode 100644 index 0000000000..37dd8d4334 --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdt_support.h> +#include <fdtdec.h> +#include <asm/arch/tegra.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern unsigned long nvtboot_boot_x0; + +/* + * A parsed version of /memory/reg from the DTB that is passed to U-Boot in x0. + * + * We only support up to two banks since that's all the binary bootloader + * ever sets. We assume bank 0 is RAM below 4G and bank 1 is RAM above 4G. + * This is all a fairly safe assumption, since the L4T kernel makes the same + * assumptions, so the bootloader is unlikely to change. + * + * This is written to before relocation, and hence cannot be in .bss, since + * .bss overlaps the DTB that's appended to the U-Boot binary. The initializer + * forces this into .data and avoids this issue. This also has the nice side- + * effect of the content being valid after relocation. + */ +static struct { + u64 start; + u64 size; +} ram_banks[2] = {{1}}; + +int dram_init(void) +{ + unsigned int na, ns; + const void *nvtboot_blob = (void *)nvtboot_boot_x0; + int node, len, i; + const u32 *prop; + + memset(ram_banks, 0, sizeof(ram_banks)); + + na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2); + ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2); + + node = fdt_path_offset(nvtboot_blob, "/memory"); + if (node < 0) { + error("Can't find /memory node in nvtboot DTB"); + hang(); + } + prop = fdt_getprop(nvtboot_blob, node, "reg", &len); + if (!prop) { + error("Can't find /memory/reg property in nvtboot DTB"); + hang(); + } + + len /= (na + ns); + if (len > ARRAY_SIZE(ram_banks)) + len = ARRAY_SIZE(ram_banks); + + gd->ram_size = 0; + for (i = 0; i < len; i++) { + ram_banks[i].start = of_read_number(prop, na); + prop += na; + ram_banks[i].size = of_read_number(prop, ns); + prop += ns; + gd->ram_size += ram_banks[i].size; + } + + return 0; +} + +extern unsigned long nvtboot_boot_x0; + +void dram_init_banksize(void) +{ + int i; + + for (i = 0; i < 2; i++) { + gd->bd->bi_dram[i].start = ram_banks[i].start; + gd->bd->bi_dram[i].size = ram_banks[i].size; + } +} + +ulong board_get_usable_ram_top(ulong total_size) +{ + return ram_banks[0].start + ram_banks[0].size; +} diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 61f5639e0d..ace42799f7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -439,7 +439,7 @@ ulong cpu_init_f(void) #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) struct law_entry law; #endif #ifdef CONFIG_MPC8548 @@ -459,7 +459,7 @@ ulong cpu_init_f(void) disable_tlb(14); disable_tlb(15); -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) /* Disable the LAW created for NOR flash by the PBI commands */ law = find_law(CONFIG_SYS_PBI_FLASH_BASE); if (law.index != -1) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 4c51225868..c3e12349f7 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1069,17 +1069,23 @@ create_init_ram_area: #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) /* create a temp mapping in AS = 1 for Flash mapping * created by PBL for ISBC code - */ + */ create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 -#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) +/* + * For Targets without CONFIG_SPL like P3, P5 + * and for targets with CONFIG_SPL like T1, T2, T4, only for + * u-boot-spl i.e. CONFIG_SPL_BUILD + */ +#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \ + (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE * to L3 Address configured by PBL for ISBC code - */ + */ create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 9421f1ebf6..ede8e66210 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -239,15 +239,23 @@ int pamu_init(void) spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES; /* Allocate space for Primary PAACT Table */ +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_PPAACT_ADDR)) + ppaact = (void *)CONFIG_SPL_PPAACT_ADDR; +#else ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size); if (!ppaact) return -1; +#endif memset(ppaact, 0, ppaact_size); /* Allocate space for Secondary PAACT Table */ +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SPAACT_ADDR)) + sec = (void *)CONFIG_SPL_SPAACT_ADDR; +#else sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size); if (!sec) return -1; +#endif memset(sec, 0, spaact_size); ppaact_phys = virt_to_phys((void *)ppaact); diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index 26c5ea4fd7..a8e6f51777 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -28,6 +28,14 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) i++; #endif +#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR)) + tbl->start_addr[i] = + (uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR); + tbl->size[i] = 256 * 1024; /* 256K CPC flash */ + tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; + + i++; +#endif debug("PAMU address\t\t\tsize\n"); for (j = 0; j < i ; j++) debug("%llx \t\t\t%llx\n", tbl->start_addr[j], tbl->size[j]); diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 826f9c960e..2e2d565ba4 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -35,7 +35,9 @@ defined(CONFIG_T104xD4RDB) || \ defined(CONFIG_PPC_T1023) || \ defined(CONFIG_PPC_T1024) +#ifndef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CPC_REINIT_F +#endif #define CONFIG_KEY_REVOCATION #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 @@ -43,7 +45,13 @@ #if defined(CONFIG_RAMBOOT_PBL) #undef CONFIG_SYS_INIT_L3_ADDR -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#ifdef CONFIG_SYS_INIT_L3_VADDR +#define CONFIG_SYS_INIT_L3_ADDR \ + (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ + 0xbff00000 +#else +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif #endif #if defined(CONFIG_C29XPCIE) @@ -72,6 +80,32 @@ #ifdef CONFIG_CHAIN_OF_TRUST +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_DM 1 +#define CONFIG_SPL_CRYPTO_SUPPORT +#define CONFIG_SPL_HASH_SUPPORT +#define CONFIG_SPL_RSA +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +/* + * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init + * due to space crunch on CPC and thus malloc will not work. + */ +#define CONFIG_SPL_PPAACT_ADDR 0x2e000000 +#define CONFIG_SPL_SPAACT_ADDR 0x2f000000 +#define CONFIG_SPL_JR0_LIODN_S 454 +#define CONFIG_SPL_JR0_LIODN_NS 458 +/* + * Define the key hash for U-Boot here if public/private key pair used to + * sign U-boot are different from the SRK hash put in the fuse + * Example of defining KEY_HASH is + * #define CONFIG_SPL_UBOOT_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + * else leave it defined as NULL + */ + +#define CONFIG_SPL_UBOOT_KEY_HASH NULL +#endif /* ifdef CONFIG_SPL_BUILD */ + #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON @@ -82,7 +116,9 @@ #define CONFIG_FSL_CAAM #endif -/* fsl_setenv_chain_of_trust() must be called from +#ifndef CONFIG_SPL_BUILD +/* + * fsl_setenv_chain_of_trust() must be called from * board_late_init() */ #ifndef CONFIG_BOARD_LATE_INIT @@ -119,5 +155,6 @@ #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ #include <config_fsl_chain_trust.h> +#endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index ecfcc8253a..290536db15 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -6,7 +6,17 @@ #include <common.h> #include <fsl_validate.h> +#include <fsl_secboot_err.h> #include <fsl_sfp.h> +#include <dm/root.h> + +#ifdef CONFIG_ADDR_MAP +#include <asm/mmu.h> +#endif + +#ifdef CONFIG_FSL_CORENET +#include <asm/fsl_pamu.h> +#endif #ifdef CONFIG_LS102XA #include <asm/arch/immap_ls102xa.h> @@ -52,6 +62,7 @@ int fsl_check_boot_mode_secure(void) return 0; } +#ifndef CONFIG_SPL_BUILD int fsl_setenv_chain_of_trust(void) { /* Check Boot Mode @@ -68,3 +79,48 @@ int fsl_setenv_chain_of_trust(void) setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); return 0; } +#endif + +#ifdef CONFIG_SPL_BUILD +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) +{ + int res; + + /* + * Check Boot Mode + * If Boot Mode is Non-Secure, skip validation + */ + if (fsl_check_boot_mode_secure() == 0) + return; + + printf("SPL: Validating U-Boot image\n"); + +#ifdef CONFIG_ADDR_MAP + init_addr_map(); +#endif + +#ifdef CONFIG_FSL_CORENET + if (pamu_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#endif + +#ifdef CONFIG_FSL_CAAM + if (sec_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT); +#endif + +/* + * dm_init_and_scan() is called as part of common SPL framework, so no + * need to call it again but in case of powerpc platforms which currently + * do not use common SPL framework, so need to call this function here. + */ +#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK)) + dm_init_and_scan(false); +#endif + res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH, + &img_addr); + + if (res == 0) + printf("SPL: Validation of U-boot successful\n"); +} +#endif /* ifdef CONFIG_SPL_BUILD */ diff --git a/board/freescale/t104xrdb/t104x_pbi_sb.cfg b/board/freescale/t104xrdb/t104x_pbi_sb.cfg new file mode 100644 index 0000000000..98dc8e4c24 --- /dev/null +++ b/board/freescale/t104xrdb/t104x_pbi_sb.cfg @@ -0,0 +1,38 @@ +#PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 bffc0007 +09010f00 081e000d +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 bffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 bf000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF +090e0200 bffd0000 +091380c0 000FFFFF diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 95c15aa596..7c0511e268 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -28,7 +28,8 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. @@ -36,6 +37,18 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), + +#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot + * the physical address of the SRAM is at 0xbffc0000, + * and virtual address is 0xfffc0000 + */ + + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, + CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 0f587eaaa7..dbdc1b65e6 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -30,6 +30,28 @@ void pin_mux_mmc(void) ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); + + /* Disable LDO4 discharge */ + ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) { + printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret); + } else { + val &= ~BIT(1); /* ADE */ + ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret); + } + + /* Set MBLPD */ + ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } else { + val |= BIT(6); /* MBLPD */ + ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } } /* diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h index 92c3719112..39e550149a 100644 --- a/board/nvidia/p2571/max77620_init.h +++ b/board/nvidia/p2571/max77620_init.h @@ -13,6 +13,8 @@ #define MAX77620_I2C_ADDR 0x78 #define MAX77620_I2C_ADDR_7BIT 0x3C +#define MAX77620_CNFGGLBL1_REG 0x00 + #define MAX77620_SD0_REG 0x16 #define MAX77620_SD1_REG 0x17 #define MAX77620_SD2_REG 0x18 diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..2e162554c6 --- /dev/null +++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,30 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND,SECURE_BOOT" +CONFIG_BOOTDELAY=0 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_ESPI=y +CONFIG_OF_LIBFDT=y +CONFIG_RSA=y +CONFIG_DM=y diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000-a02_defconfig index 9f2c418f9f..1fe25f58f1 100644 --- a/configs/p2771-0000_defconfig +++ b/configs/p2771-0000-a02_defconfig @@ -2,10 +2,10 @@ CONFIG_ARM=y CONFIG_TEGRA=y CONFIG_TEGRA186=y CONFIG_TARGET_P2771_0000=y -CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000" +CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-a02" CONFIG_OF_SYSTEM_SETUP=y CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Tegra186 (P2771-0000) # " +CONFIG_SYS_PROMPT="Tegra186 (P2771-0000 A02) # " # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/p2771-0000-b00_defconfig b/configs/p2771-0000-b00_defconfig new file mode 100644 index 0000000000..552fb6cec7 --- /dev/null +++ b/configs/p2771-0000-b00_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA186=y +CONFIG_TARGET_P2771_0000=y +CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-b00" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Tegra186 (P2771-0000 B00) # " +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/doc/SPL/README.spl-secure-boot b/doc/SPL/README.spl-secure-boot new file mode 100644 index 0000000000..f2f8d78883 --- /dev/null +++ b/doc/SPL/README.spl-secure-boot @@ -0,0 +1,18 @@ +Overview of SPL verified boot on powerpc/mpc85xx & arm/layerscape platforms +=========================================================================== + +Introduction +------------ + +This document provides an overview of how SPL verified boot works on powerpc/ +mpc85xx & arm/layerscape platforms. + +Methodology +----------- + +The SPL image is responsible for loading the next stage boot loader, which is +the main u-boot image. For secure boot process on these platforms ROM verifies +SPL image, so to continue chain of trust SPL image verifies U-boot image using +spl_validate_uboot(). This function uses QorIQ Trust Architecture header +(appended to U-boot image) to validate the U-boot binary just before passing +control to it. diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 510fa4e376..4a8cc3295a 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -599,10 +599,27 @@ int sec_init_idx(uint8_t sec_idx) sec_out32(&sec->mcfgr, mcr); #ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SPL_BUILD + /* + * For SPL Build, Set the Liodns in SEC JR0 for + * creating PAMU entries corresponding to these. + * For normal build, these are set in set_liodns(). + */ + liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK; + liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK; + + liodnr = sec_in32(&sec->jrliodnr[0].ls) & + ~(JRNSLIODN_MASK | JRSLIODN_MASK); + liodnr = liodnr | + (liodn_ns << JRNSLIODN_SHIFT) | + (liodn_s << JRSLIODN_SHIFT); + sec_out32(&sec->jrliodnr[0].ls, liodnr); +#else liodnr = sec_in32(&sec->jrliodnr[0].ls); liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT; liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; #endif +#endif ret = jr_init(sec_idx); if (ret < 0) { diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index cbeb74a5bb..4e49a4e154 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -11,6 +11,9 @@ #include <asm/io.h> #include <fsl_ifc.h> #include <linux/mtd/nand.h> +#ifdef CONFIG_CHAIN_OF_TRUST +#include <fsl_validate.h> +#endif static inline int is_blank(uchar *addr, int page_size) { @@ -268,6 +271,27 @@ void nand_boot(void) */ flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); #endif + +#ifdef CONFIG_CHAIN_OF_TRUST + /* + * U-Boot header is appended at end of U-boot image, so + * calculate U-boot header address using U-boot header size. + */ +#define CONFIG_U_BOOT_HDR_ADDR \ + ((CONFIG_SYS_NAND_U_BOOT_START + \ + CONFIG_SYS_NAND_U_BOOT_SIZE) - \ + CONFIG_U_BOOT_HDR_SIZE) + spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR, + CONFIG_SYS_NAND_U_BOOT_START); + /* + * In case of failure in validation, spl_validate_uboot would + * not return back in case of Production environment with ITS=1. + * Thus U-Boot will not start. + * In Development environment (ITS=0 and SB_EN=1), the function + * may return back in case of non-fatal failures. + */ +#endif + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); } diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 2c3c4ac093..5de9bb72cf 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -830,7 +830,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=b4860qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=b4860qds/b4860qds.dtb\0" \ "bdev=sda3\0" @@ -868,7 +868,7 @@ unsigned long get_board_ddr_clk(void); "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ + "setenv fdtaddr 0x01e00000;" \ "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 0a9d8a64af..f2a7c69ad2 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -403,7 +403,7 @@ extern unsigned long get_sdram_size(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=bsc9131rdb.dtb\0" \ "bdev=sda1\0" \ "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 756beec61b..4744f08c9a 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -647,7 +647,7 @@ combinations. this should be removed later "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=bsc9132qds.dtb\0" \ "bdev=sda1\0" \ CONFIG_DEF_HWCONFIG\ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 69a9798540..cc5359fe44 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -530,7 +530,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=name/of/device-tree.dtb\0" \ "othbootargs=ramdisk_size=600000\0" \ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 578325cd05..5b804648ed 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -203,7 +203,7 @@ */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -452,6 +452,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 5613a4a0cd..1c4e082d4e 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -241,7 +241,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -268,7 +268,7 @@ #define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nand0=e2800000.flash" #define MTDPARTS_DEFAULT \ - "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND 1 @@ -502,6 +502,7 @@ */ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 7ce5f59937..23a2e34ce7 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -169,7 +169,7 @@ /* * The reserved memory */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -241,7 +241,7 @@ #define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nand0=e0600000.flash" #define MTDPARTS_DEFAULT \ - "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + "mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND 1 @@ -489,6 +489,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 13f954d00e..095c0d8dca 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -156,7 +156,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -359,6 +359,7 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index fd482606ad..18418e398e 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -168,7 +168,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -441,6 +441,7 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 288b126d02..a2fa783a77 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -225,7 +225,7 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -508,6 +508,7 @@ */ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 2721255254..c11c0cf825 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -330,7 +330,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -544,6 +544,7 @@ boards, we say we have two, but don't display a message if we find only one. */ */ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 921d5f399d..b2dc1890c7 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -200,7 +200,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -522,6 +522,7 @@ extern int board_pci_host_broken(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index bb06e89b4e..8eb87ebde5 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -225,7 +225,7 @@ #undef CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -533,6 +533,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 7c19ff84bc..874261a146 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -727,7 +727,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8536ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=8536ds/mpc8536ds.dtb\0" \ "bdev=sda3\0" \ "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index b9d97c1006..cd1043204f 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -209,7 +209,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 @@ -462,7 +462,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8544ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=8544ds/mpc8544ds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index e73be48d51..b81a4eddd7 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -562,7 +562,7 @@ extern unsigned long get_clock_freq(void); "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=mpc8548cds.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2e6989f816..390b1ef61b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -668,7 +668,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8572ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=8572ds/mpc8572ds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 5384584c18..5b6b4bd5d8 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -862,7 +862,7 @@ extern unsigned long get_sdram_size(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1010rdb.dtb\0" \ "bdev=sda1\0" \ "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index bdf0323bfc..fe19957c39 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -731,7 +731,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1022ds.dtb\0" \ "bdev=sda3\0" \ "hwconfig=esdhc;audclk:12\0" diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 07a594d15d..d044c7bc2e 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -375,7 +375,7 @@ extern unsigned long get_clock_freq(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1023rdb.dtb\0" \ "othbootargs=ramdisk_size=600000\0" \ "bdev=sda1\0" \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 24e5431845..8479410ee7 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -698,7 +698,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "usb_dr_mode=host\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p2041rdb/p2041rdb.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 06d1d0fc49..25a0652b5b 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -897,7 +897,7 @@ unsigned long get_board_ddr_clk(void); "cmp.b $loadaddr $ubootaddr $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "bdev=sda3\0" #define CONFIG_LINUX \ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 9f5063c333..7ce6420d48 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -770,7 +770,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t1040qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t1040qds/t1040qds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index a8f4f742e6..ae1acbdd04 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -18,7 +18,14 @@ #include <asm/config_mpc85xx.h> #ifdef CONFIG_RAMBOOT_PBL + +#ifndef CONFIG_SECURE_BOOT #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg +#else +#define CONFIG_SYS_FSL_PBL_PBI \ + $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg +#endif + #ifdef CONFIG_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg #endif @@ -62,7 +69,17 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. + */ +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ + CONFIG_U_BOOT_HDR_SIZE) +#else #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) @@ -161,6 +178,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_RAMBOOT_NAND +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 @@ -202,8 +223,14 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +/* + * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence + * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address + * (CONFIG_SYS_INIT_L3_VADDR) will be different. + */ +#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE 256 << 10 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) #endif @@ -873,7 +900,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=" __stringify(FDTFILE) "\0" \ "bdev=sda3\0" diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 1f07a83a1a..621755526a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -840,7 +840,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t2080qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t2080qds/t2080qds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 0ded41e0dd..7a7de9703f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -792,7 +792,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t2080rdb/t2080rdb.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index f075dfb5f0..85aab183ff 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -577,7 +577,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t4240qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t4240qds/t4240qds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9ba69a1d12..4133165ea8 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -770,7 +770,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t4240rdb/t4240rdb.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 30c283185b..44e115da6d 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -447,7 +447,7 @@ "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=controlcenterd.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 4a770b0546..0c99e9f5e6 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -708,7 +708,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p4080ds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p4080ds/p4080ds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 708d5f730d..da38709fbf 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -520,7 +520,7 @@ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "bdev=sda3\0" #define CONFIG_HDBOOT \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 4f22d12a3f..3d3342141d 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -989,7 +989,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "bdev=sda1\0" \ "jffs2nor=mtdblock3\0" \ "norbootaddr=ef080000\0" \ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 30bfbf44f5..79e4991563 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -513,7 +513,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "bdev=sda1\0" \ "norbootaddr=ef080000\0" \ "norfdtaddr=ef040000\0" \ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 46766a6779..ec9ad45567 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -595,7 +595,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=uRamdisk\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=sbc8548.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index 73c8d5b6fd..bc91714cf7 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -304,7 +304,7 @@ extern void out32(unsigned int, unsigned long); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot="CONFIG_PROG_UBOOT"\0" \ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 9f3158d056..eaea33babf 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -699,7 +699,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index a418fc5c9e..f7cfc9ea86 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -483,7 +483,7 @@ "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 36df6682b2..3306e44a6d 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -554,7 +554,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 1794ba10a3..276dde7d3e 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -538,7 +538,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/fsl_validate.h b/include/fsl_validate.h index a71e1ce2b0..c350938d1f 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -254,4 +254,11 @@ int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, int fsl_check_boot_mode_secure(void); int fsl_setenv_chain_of_trust(void); + +/* + * This function is used to validate the main U-boot binary from + * SPL just before passing control to it using QorIQ Trust + * Architecture header (appended to U-boot image). + */ +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); #endif |