diff options
30 files changed, 209 insertions, 300 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 8a4c5d4eab..f9ee4281d9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -439,6 +439,11 @@ DFU M: Lukasz Majewski <lukma@denx.de> S: Maintained T: git git://git.denx.de/u-boot-dfu.git +F: cmd/dfu.c +F: cmd/usb_*.c +F: common/dfu.c +F: common/update.c +F: common/usb_storage.c F: drivers/dfu/ F: drivers/usb/gadget/ @@ -454,7 +459,7 @@ EFI PAYLOAD M: Heinrich Schuchardt <xypron.glpk@gmx.de> R: Alexander Graf <agraf@csgraf.de> S: Maintained -T: git git://github.com/agraf/u-boot.git +T: git git://git.denx.de/u-boot-efi.git F: doc/README.uefi F: doc/README.iscsi F: Documentation/efi.rst diff --git a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts index ebbd234d78..3de640724d 100644 --- a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts +++ b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts @@ -19,6 +19,10 @@ }; }; +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; + &sdhi2_pins { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; power-source = <1800>; diff --git a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts index 8be5e41a51..a22028bb31 100644 --- a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts @@ -8,6 +8,14 @@ #include "r8a7795-salvator-x.dts" #include "r8a7795-u-boot.dtsi" +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; + +&vcc_sdhi3 { + u-boot,off-on-delay-us = <20000>; +}; + &sdhi2_pins { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; power-source = <1800>; diff --git a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts index 4e960081f9..612cc87c71 100644 --- a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts +++ b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts @@ -19,6 +19,10 @@ }; }; +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; + &sdhi2_pins { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; power-source = <1800>; diff --git a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts index 44b2f9fb37..c730b90a42 100644 --- a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts @@ -8,6 +8,14 @@ #include "r8a7796-salvator-x.dts" #include "r8a7796-u-boot.dtsi" +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; + +&vcc_sdhi3 { + u-boot,off-on-delay-us = <20000>; +}; + &sdhi2_pins { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; power-source = <1800>; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts index 9e0cd26f40..cfc0f74081 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts @@ -8,6 +8,14 @@ #include "r8a77965-salvator-x.dts" #include "r8a77965-u-boot.dtsi" +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; + +&vcc_sdhi3 { + u-boot,off-on-delay-us = <20000>; +}; + &sdhi2_pins { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; power-source = <1800>; diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts index b030d5c649..4c1669e022 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -36,6 +36,7 @@ gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; enable-active-high; + u-boot,off-on-delay-us = <20000>; }; vccq_sdhi0: regulator-vccq-sdhi0 { @@ -60,6 +61,7 @@ gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; enable-active-high; + u-boot,off-on-delay-us = <20000>; }; vccq_sdhi1: regulator-vccq-sdhi1 { diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index d7997d71e3..f32b3c4ce5 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -61,13 +61,7 @@ int setup_boot_mode(void) void *reg = (void *)CONFIG_ROCKCHIP_BOOT_MODE_REG; int boot_mode = readl(reg); - /* - * This should be handled using a driver-tree property and a suitable - * driver which can read the appropriate settings. As it is, this - * breaks chromebook_minnie.\ - * - * rockchip_dnl_mode_check(); - */ + rockchip_dnl_mode_check(); boot_mode = readl(reg); debug("%s: boot mode 0x%08x\n", __func__, boot_mode); diff --git a/board/raspberrypi/rpi/MAINTAINERS b/board/raspberrypi/rpi/MAINTAINERS index cce1a7ad76..4f1b23efc8 100644 --- a/board/raspberrypi/rpi/MAINTAINERS +++ b/board/raspberrypi/rpi/MAINTAINERS @@ -1,5 +1,5 @@ RPI BOARD -M: Alexander Graf <agraf@suse.de> +M: Matthias Brugger <mbrugger@suse.com> S: Maintained F: board/raspberrypi/rpi/ F: include/configs/rpi.h diff --git a/board/synopsys/axs10x/Makefile b/board/synopsys/axs10x/Makefile index 340e12c443..dd5ee680e7 100644 --- a/board/synopsys/axs10x/Makefile +++ b/board/synopsys/axs10x/Makefile @@ -3,4 +3,3 @@ # Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved. obj-y += axs10x.o -obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/synopsys/axs10x/nand.c b/board/synopsys/axs10x/nand.c deleted file mode 100644 index 8108460f58..0000000000 --- a/board/synopsys/axs10x/nand.c +++ /dev/null @@ -1,242 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. - */ - -#include <bouncebuf.h> -#include <common.h> -#include <malloc.h> -#include <nand.h> -#include <asm/io.h> -#include "axs10x.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define BUS_WIDTH 8 /* AXI data bus width in bytes */ - -/* DMA buffer descriptor bits & masks */ -#define BD_STAT_OWN (1 << 31) -#define BD_STAT_BD_FIRST (1 << 3) -#define BD_STAT_BD_LAST (1 << 2) -#define BD_SIZES_BUFFER1_MASK 0xfff - -#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST) - -/* Controller command flags */ -#define B_WFR (1 << 19) /* 1b - Wait for ready */ -#define B_LC (1 << 18) /* 1b - Last cycle */ -#define B_IWC (1 << 13) /* 1b - Interrupt when complete */ - -/* NAND cycle types */ -#define B_CT_ADDRESS (0x0 << 16) /* Address operation */ -#define B_CT_COMMAND (0x1 << 16) /* Command operation */ -#define B_CT_WRITE (0x2 << 16) /* Write operation */ -#define B_CT_READ (0x3 << 16) /* Write operation */ - -enum nand_isr_t { - NAND_ISR_DATAREQUIRED = 0, - NAND_ISR_TXUNDERFLOW, - NAND_ISR_TXOVERFLOW, - NAND_ISR_DATAAVAILABLE, - NAND_ISR_RXUNDERFLOW, - NAND_ISR_RXOVERFLOW, - NAND_ISR_TXDMACOMPLETE, - NAND_ISR_RXDMACOMPLETE, - NAND_ISR_DESCRIPTORUNAVAILABLE, - NAND_ISR_CMDDONE, - NAND_ISR_CMDAVAILABLE, - NAND_ISR_CMDERROR, - NAND_ISR_DATATRANSFEROVER, - NAND_ISR_NONE -}; - -enum nand_regs_t { - AC_FIFO = 0, /* address and command fifo */ - IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */ - INT_STATUS = 0x118, /* interrupt status register */ - INT_CLR_STATUS = 0x120, /* interrupt clear status register */ -}; - -struct nand_bd { - uint32_t status; /* DES0 */ - uint32_t sizes; /* DES1 */ - uint32_t buffer_ptr0; /* DES2 */ - uint32_t buffer_ptr1; /* DES3 */ -}; - -#define NAND_REG_WRITE(r, v) \ - writel(v, (volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r)) -#define NAND_REG_READ(r) \ - readl((const volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r)) - -static struct nand_bd *bd; /* DMA buffer descriptors */ - -/** - * axs101_nand_write_buf - write buffer to chip - * @mtd: MTD device structure - * @buf: data buffer - * @len: number of bytes to write - */ -static uint32_t nand_flag_is_set(uint32_t flag) -{ - uint32_t reg = NAND_REG_READ(INT_STATUS); - - if (reg & (1 << NAND_ISR_CMDERROR)) - return 0; - - if (reg & (1 << flag)) { - NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag); - return 1; - } - - return 0; -} - -/** - * axs101_nand_write_buf - write buffer to chip - * @mtd: MTD device structure - * @buf: data buffer - * @len: number of bytes to write - */ -static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf, - int len) -{ - struct bounce_buffer bbstate; - - bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ); - - /* Setup buffer descriptor */ - writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); - writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); - writel(bbstate.bounce_buffer, &bd->buffer_ptr0); - writel(0, &bd->buffer_ptr1); - - /* Flush modified buffer descriptor */ - flush_dcache_range((unsigned long)bd, - (unsigned long)bd + sizeof(struct nand_bd)); - - /* Issue "write" command */ - NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1)); - - /* Wait for NAND command and DMA to complete */ - while (!nand_flag_is_set(NAND_ISR_CMDDONE)) - ; - while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE)) - ; - - bounce_buffer_stop(&bbstate); -} - -/** - * axs101_nand_read_buf - read chip data into buffer - * @mtd: MTD device structure - * @buf: buffer to store data - * @len: number of bytes to read - */ -static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct bounce_buffer bbstate; - - bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE); - - /* Setup buffer descriptor */ - writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); - writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); - writel(bbstate.bounce_buffer, &bd->buffer_ptr0); - writel(0, &bd->buffer_ptr1); - - /* Flush modified buffer descriptor */ - flush_dcache_range((unsigned long)bd, - (unsigned long)bd + sizeof(struct nand_bd)); - - /* Issue "read" command */ - NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1)); - - /* Wait for NAND command and DMA to complete */ - while (!nand_flag_is_set(NAND_ISR_CMDDONE)) - ; - while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE)) - ; - - bounce_buffer_stop(&bbstate); -} - -/** - * axs101_nand_read_byte - read one byte from the chip - * @mtd: MTD device structure - */ -static u_char axs101_nand_read_byte(struct mtd_info *mtd) -{ - u8 byte; - - axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); - return byte; -} - -/** - * axs101_nand_read_word - read one word from the chip - * @mtd: MTD device structure - */ -static u16 axs101_nand_read_word(struct mtd_info *mtd) -{ - u16 word; - - axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word)); - return word; -} - -/** - * axs101_nand_hwcontrol - NAND control functions wrapper. - * @mtd: MTD device structure - * @cmd: Command - */ -static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, - unsigned int ctrl) -{ - if (cmd == NAND_CMD_NONE) - return; - - cmd = cmd & 0xff; - - switch (ctrl & (NAND_ALE | NAND_CLE)) { - /* Address */ - case NAND_ALE: - cmd |= B_CT_ADDRESS; - break; - - /* Command */ - case NAND_CLE: - cmd |= B_CT_COMMAND | B_WFR; - - break; - - default: - debug("%s: unknown ctrl %#x\n", __func__, ctrl); - } - - NAND_REG_WRITE(AC_FIFO, cmd | B_LC); - while (!nand_flag_is_set(NAND_ISR_CMDDONE)) - ; -} - -int board_nand_init(struct nand_chip *nand) -{ - bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN, - sizeof(struct nand_bd)); - - /* Set buffer descriptor address in IDMAC */ - NAND_REG_WRITE(IDMAC_BDADDR, bd); - - nand->ecc.mode = NAND_ECC_SOFT; - nand->cmd_ctrl = axs101_nand_hwcontrol; - nand->read_byte = axs101_nand_read_byte; - nand->read_word = axs101_nand_read_word; - nand->write_buf = axs101_nand_write_buf; - nand->read_buf = axs101_nand_read_buf; - - /* MBv3 has NAND IC with 16-bit data bus */ - if (gd->board_type == AXS_MB_V3) - nand->options |= NAND_BUSWIDTH_16; - - return 0; -} diff --git a/board/synopsys/hsdk/README b/board/synopsys/hsdk/README index e29a6a1727..9155f17c6e 100644 --- a/board/synopsys/hsdk/README +++ b/board/synopsys/hsdk/README @@ -83,10 +83,11 @@ Useful notes on bulding and using of U-Boot on ARC HS Development Kit (AKA HSDK) HSDK board. Note that Python3 script is used for generation of a header, thus - to get that done it's required to have Python3 with elftools installed. - On CentOS/RHEL/Fedora this could be installed with: + to get that done it's required to have Python3 with "pyelftools" installed. + + "pyelftools" could be installed with help of "pip" even w/o root rights: ------------------------->8---------------------- - sudo dnf install python3-pyelftools + python3 -m pip install --user pyelftools ------------------------->8---------------------- EXECUTING U-BOOT diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 6ef6616554..0bfb532fc7 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -14,7 +14,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 2208bdb9be..0c8af405a9 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -14,7 +14,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index f0671dd8a1..995290ca5f 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -56,4 +56,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y -CONFIG_USE_TINY_PRINTF=y diff --git a/doc/README.uefi b/doc/README.uefi index 0982fad92e..66b6abece5 100644 --- a/doc/README.uefi +++ b/doc/README.uefi @@ -12,6 +12,15 @@ the interaction of drivers and applications with the firmware. The API comprises access to block storage, network, and console to name a few. The Linux kernel and boot loaders like GRUB or the FreeBSD loader can be executed. +## Development target + +The implementation of UEFI in U-Boot strives to reach the minimum requirements +described in "Server Base Boot Requirements System Software on ARM Platforms - +Version 1.1" [4]. + +A full blown UEFI implementation would contradict the U-Boot design principle +"keep it small". + ## Building for UEFI The UEFI standard supports only little-endian systems. The UEFI support can be @@ -299,7 +308,7 @@ This driver is only available if U-Boot is configured with CONFIG_BLK=y CONFIG_PARTITIONS=y -## TODOs as of U-Boot 2018.07 +## TODOs as of U-Boot 2019.04 * unimplemented or incompletely implemented boot services * Exit - call unload function, unload applications only @@ -308,16 +317,13 @@ This driver is only available if U-Boot is configured with * unimplemented or incompletely implemented runtime services * SetVariable() ignores attribute EFI_VARIABLE_APPEND_WRITE - * GetNextVariableName is not implemented * QueryVariableInfo is not implemented * unimplemented events * EVT_RUNTIME * EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE - * event groups * data model - * manage events in a linked list * manage configuration tables in a linked list * UEFI drivers @@ -329,9 +335,14 @@ This driver is only available if U-Boot is configured with * persistence * runtime support +* incompletely implemented protocols + * support version 0x00020000 of the EFI file protocol + ## Links * [1](http://uefi.org/specifications) http://uefi.org/specifications - UEFI specifications * [2](./driver-model/README.txt) doc/driver-model/README.txt - Driver model * [3](./README.iscsi) doc/README.iscsi - iSCSI booting with U-Boot and iPXE +* [4](https://developer.arm.com/docs/den0044/latest/server-base-boot-requirements-system-software-on-arm-platforms-version-11) + Server Base Boot Requirements System Software on ARM Platforms - Version 1.1 diff --git a/doc/git-mailrc b/doc/git-mailrc index c2eee8c7d8..b75ebab02b 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -15,7 +15,7 @@ alias abiessmann Andreas Bießmann <andreas@biessmann.org> alias abrodkin Alexey Brodkin <alexey.brodkin@synopsys.com> alias afleming Andy Fleming <afleming@gmail.com> alias ag Anatolij Gustschin <agust@denx.de> -alias agraf Alexander Graf <agraf@suse.de> +alias agraf Alexander Graf <agraf@csgraf.de> alias alisonwang Alison Wang <alison.wang@nxp.com> alias angelo_ts Angelo Dureghello <angelo@sysam.it> alias bmeng Bin Meng <bmeng.cn@gmail.com> diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 6dfd02f2eb..13111b341a 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -44,13 +44,17 @@ static const struct clk_div_table cpg_sd01_div_table[] = { { 0, 0 }, }; -static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 div) +static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val) { - while ((*table++).val) { - if ((*table).div == div) - return div; + for (;;) { + if (!(*table).div) + return 0xff; + + if ((*table).val == val) + return (*table).div; + + table++; } - return 0xff; } static int gen2_clk_enable(struct clk *clk) @@ -117,7 +121,7 @@ static ulong gen2_clk_get_rate(struct clk *clk) case CLK_TYPE_FF: rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div; - debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n", + debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n", __func__, __LINE__, core->parent, core->mult, core->div, rate); return rate; @@ -202,8 +206,50 @@ static ulong gen2_clk_get_rate(struct clk *clk) return -ENOENT; } +static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate) +{ + struct gen2_clk_priv *priv = dev_get_priv(clk->dev); + struct cpg_mssr_info *info = priv->info; + const struct cpg_core_clk *core; + struct clk parent, pparent; + u32 val; + int ret; + + ret = renesas_clk_get_parent(clk, info, &parent); + if (ret) { + debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); + return ret; + } + + if (renesas_clk_is_mod(&parent)) + return 0; + + ret = renesas_clk_get_core(&parent, info, &core); + if (ret) + return ret; + + if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1")) + return 0; + + ret = renesas_clk_get_parent(&parent, info, &pparent); + if (ret) { + debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); + return ret; + } + + val = (gen2_clk_get_rate(&pparent) / rate) - 1; + + debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset); + + writel(val, priv->base + core->offset); + + return 0; +} + static ulong gen2_clk_set_rate(struct clk *clk, ulong rate) { + /* Force correct MMC-IF divider configuration if applicable */ + gen2_clk_setup_mmcif_div(clk, rate); return gen2_clk_get_rate(clk); } diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 89b255daf4..456c1b4cc9 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1892,8 +1892,7 @@ static int mmc_select_hs400(struct mmc *mmc) } /* Set back to HS */ - mmc_set_card_speed(mmc, MMC_HS, false); - mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); + mmc_set_card_speed(mmc, MMC_HS, true); err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG); diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 306daf1415..c8875ce8f8 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -696,7 +696,7 @@ static int sh_mmcif_dm_probe(struct udevice *dev) return ret; } - host->clk = clk_get_rate(&sh_mmcif_clk); + host->clk = clk_set_rate(&sh_mmcif_clk, 97500000); plat->cfg.name = dev->name; plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 01d8c2b925..812205a21f 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -783,7 +783,10 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) plat->cfg.f_min = mclk / (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512); plat->cfg.f_max = mclk; - plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ + if (quirks & TMIO_SD_CAP_16BIT) + plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */ + else + plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ upriv->mmc = &plat->mmc; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 60585f3208..8b6ce11a63 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -92,10 +92,19 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } static struct rockchip_pin_bank rk3288_pin_banks[] = { - PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, - IOMUX_SOURCE_PMU, - IOMUX_SOURCE_PMU, - IOMUX_UNROUTED + PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", + IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, + IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, + IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, + IOMUX_UNROUTED, + DRV_TYPE_WRITABLE_32BIT, + DRV_TYPE_WRITABLE_32BIT, + DRV_TYPE_WRITABLE_32BIT, + 0, + PULL_TYPE_WRITABLE_32BIT, + PULL_TYPE_WRITABLE_32BIT, + PULL_TYPE_WRITABLE_32BIT, + 0 ), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, IOMUX_UNROUTED, diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index b84b079064..ce935656f0 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -228,7 +228,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) } } - data = (mask << (bit + 16)); + if (mux_type & IOMUX_WRITABLE_32BIT) { + regmap_read(regmap, reg, &data); + data &= ~(mask << bit); + } else { + data = (mask << (bit + 16)); + } + data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); @@ -252,7 +258,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, int reg, ret, i; u32 data, rmask_bits, temp; u8 bit; - int drv_type = bank->drv[pin_num / 8].drv_type; + /* Where need to clean the special mask for rockchip_perpin_drv_list */ + int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, pin_num, strength); @@ -324,10 +331,15 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, return -EINVAL; } - /* enable the write to the equivalent lower bits */ - data = ((1 << rmask_bits) - 1) << (bit + 16); - data |= (ret << bit); + if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { + regmap_read(regmap, reg, &data); + data &= ~(((1 << rmask_bits) - 1) << bit); + } else { + /* enable the write to the equivalent lower bits */ + data = ((1 << rmask_bits) - 1) << (bit + 16); + } + data |= (ret << bit); ret = regmap_write(regmap, reg, data); return ret; } @@ -375,7 +387,11 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3288: case RK3368: case RK3399: - pull_type = bank->pull_type[pin_num / 8]; + /* + * Where need to clean the special mask for + * rockchip_pull_list. + */ + pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); ret = -EINVAL; for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); i++) { @@ -390,10 +406,15 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, return ret; } - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); - data |= (ret << bit); + if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { + regmap_read(regmap, reg, &data); + data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit); + } else { + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + } + data |= (ret << bit); ret = regmap_write(regmap, reg, data); break; default: diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index bc809630c1..5a6849c996 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -26,6 +26,7 @@ enum rockchip_pinctrl_type { #define IOMUX_SOURCE_PMU BIT(2) #define IOMUX_UNROUTED BIT(3) #define IOMUX_WIDTH_3BIT BIT(4) +#define IOMUX_WRITABLE_32BIT BIT(5) /** * Defined some common pins constants @@ -49,6 +50,9 @@ struct rockchip_iomux { int offset; }; +#define DRV_TYPE_IO_MASK GENMASK(31, 16) +#define DRV_TYPE_WRITABLE_32BIT BIT(31) + /** * enum type index corresponding to rockchip_perpin_drv_list arrays index. */ @@ -61,6 +65,9 @@ enum rockchip_pin_drv_type { DRV_TYPE_MAX }; +#define PULL_TYPE_IO_MASK GENMASK(31, 16) +#define PULL_TYPE_WRITABLE_32BIT BIT(31) + /** * enum type index corresponding to rockchip_pull_list arrays index. */ @@ -200,6 +207,32 @@ struct rockchip_pin_bank { }, \ } +#define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ + iom2, iom3, drv0, drv1, drv2, \ + drv3, pull0, pull1, pull2, \ + pull3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = -1 }, \ + { .type = iom1, .offset = -1 }, \ + { .type = iom2, .offset = -1 }, \ + { .type = iom3, .offset = -1 }, \ + }, \ + .drv = { \ + { .drv_type = drv0, .offset = -1 }, \ + { .drv_type = drv1, .offset = -1 }, \ + { .drv_type = drv2, .offset = -1 }, \ + { .drv_type = drv3, .offset = -1 }, \ + }, \ + .pull_type[0] = pull0, \ + .pull_type[1] = pull1, \ + .pull_type[2] = pull2, \ + .pull_type[3] = pull3, \ + } + #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ label, iom0, iom1, iom2, \ iom3, drv0, drv1, drv2, \ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 0f4d78a594..0c5a3af4cc 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -32,12 +32,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x82000000 /* - * NAND Flash configuration - */ -#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* * UART configuration */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 1e2a62dd6f..828fb1b2a5 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -52,7 +52,7 @@ #define DEFAULT_FIT_TI_ARGS \ "boot_fit=0\0" \ - "fit_loadaddr=0x87000000\0" \ + "fit_loadaddr=0x90000000\0" \ "fit_bootfile=fitImage\0" \ "update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \ "loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \ diff --git a/include/efi_api.h b/include/efi_api.h index ccf608653d..8647bfa662 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -1322,7 +1322,9 @@ struct efi_pxe { #define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID \ EFI_GUID(0x964e5b22, 0x6459, 0x11d2, \ 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b) -#define EFI_FILE_PROTOCOL_REVISION 0x00010000 +#define EFI_FILE_PROTOCOL_REVISION 0x00010000 +#define EFI_FILE_PROTOCOL_REVISION2 0x00020000 +#define EFI_FILE_PROTOCOL_LATEST_REVISION EFI_FILE_PROTOCOL_REVISION2 struct efi_file_handle { u64 rev; @@ -1346,6 +1348,10 @@ struct efi_file_handle { const efi_guid_t *info_type, efi_uintn_t buffer_size, void *buffer); efi_status_t (EFIAPI *flush)(struct efi_file_handle *file); + /* + * TODO: We currently only support EFI file protocol revision 0x00010000 + * while UEFI specs 2.4 - 2.7 prescribe revision 0x00020000. + */ }; #define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION 0x00010000 diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index bc715218a1..0483403be0 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -628,6 +628,10 @@ static efi_status_t EFIAPI efi_file_flush(struct efi_file_handle *file) } static const struct efi_file_handle efi_file_handle_protocol = { + /* + * TODO: We currently only support EFI file protocol revision 0x00010000 + * while UEFI specs 2.4 - 2.7 prescribe revision 0x00020000. + */ .rev = EFI_FILE_PROTOCOL_REVISION, .open = efi_file_open, .close = efi_file_close, diff --git a/lib/efi_selftest/efi_selftest_devicepath_util.c b/lib/efi_selftest/efi_selftest_devicepath_util.c index 5fef5cfccd..c846e057d3 100644 --- a/lib/efi_selftest/efi_selftest_devicepath_util.c +++ b/lib/efi_selftest/efi_selftest_devicepath_util.c @@ -256,11 +256,6 @@ static int execute(void) efi_st_error("GetNextDevicePathInstance did not signal end\n"); return EFI_ST_FAILURE; } - ret = boottime->free_pool(dp2); - if (ret != EFI_ST_SUCCESS) { - efi_st_error("FreePool failed\n"); - return EFI_ST_FAILURE; - } /* Clean up */ ret = boottime->free_pool(dp2); diff --git a/lib/time.c b/lib/time.c index 3bf678a232..9c55da6f1b 100644 --- a/lib/time.c +++ b/lib/time.c @@ -56,7 +56,7 @@ ulong timer_get_boot_us(void) extern unsigned long __weak timer_read_counter(void); #endif -#ifdef CONFIG_TIMER +#if CONFIG_IS_ENABLED(TIMER) ulong notrace get_tbclk(void) { if (!gd->timer) { |