diff options
| -rw-r--r-- | arch/arm/mach-sunxi/dram_sun50i_h6.c | 6 | ||||
| -rw-r--r-- | configs/da850evm_nand_defconfig | 3 |
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 6b94cf38c5..5da90a2835 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -299,6 +299,8 @@ static void mctl_sys_init(struct dram_para *para) /* Put all DRAM-related blocks to reset state */ clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET); + clrbits_le32(&ccm->dram_gate_reset, BIT(0)); + udelay(5); writel(0, &ccm->dram_gate_reset); clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); @@ -313,7 +315,9 @@ static void mctl_sys_init(struct dram_para *para) /* Configure DRAM mod clock */ writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE); - writel(BIT(0) | BIT(RESET_SHIFT), &ccm->dram_gate_reset); + writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset); + udelay(5); + setbits_le32(&ccm->dram_gate_reset, BIT(0)); /* Disable all channels */ writel(0, &mctl_com->maer0); diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index d13d832e81..20f8e0ae31 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -7,9 +7,12 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y +CONFIG_SPL_DM=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="da850-evm" +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_OF_PLATDATA=y CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y |