diff options
| -rw-r--r-- | board/freescale/mx6slevk/mx6slevk.c | 244 | ||||
| -rw-r--r-- | configs/mx6slevk_defconfig | 13 | ||||
| -rw-r--r-- | configs/mx6slevk_spinor_defconfig | 13 | ||||
| -rw-r--r-- | configs/mx6slevk_spl_defconfig | 2 | ||||
| -rw-r--r-- | include/configs/mx6slevk.h | 7 |
5 files changed, 130 insertions, 149 deletions
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 96c0e8cfc7..d49543315b 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -47,11 +47,6 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ @@ -155,157 +150,55 @@ static void setup_iomux_fec(void) imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); /* Power up LAN8720 PHY */ + gpio_request(ETH_PHY_POWER, "eth_pwr"); gpio_direction_output(ETH_PHY_POWER , 1); udelay(15000); } -#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) -#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) -#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) - -static struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC1_BASE_ADDR}, - {USDHC2_BASE_ADDR, 0, 4}, - {USDHC3_BASE_ADDR, 0, 4}, -}; - int board_mmc_get_env_dev(int devno) { return devno; } -int board_mmc_getcd(struct mmc *mmc) +#ifdef CONFIG_DM_PMIC_PFUZE100 +int power_init_board(void) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; + struct udevice *dev; + int ret; + u32 dev_id, rev_id, i; + u32 switch_num = 6; + u32 offset = PFUZE100_SW1CMODE; - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - } - - return ret; -} + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return 0; -int board_mmc_init(bd_t *bis) -{ -#ifndef CONFIG_SPL_BUILD - int i, ret; - - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - * mmc2 USDHC3 - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) { - printf("Warning: failed to initialize " - "mmc dev %d\n", i); - return ret; - } - } + if (ret != 0) + return ret; - return 0; -#else - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - u32 val; - u32 port; + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - val = readl(&src_regs->sbmr1); + /* set SW1AB staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); - /* Boot from USDHC */ - port = (val >> 11) & 0x3; - switch (port) { - case 0: - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[0].max_bus_width = 4; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, - ARRAY_SIZE(usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].max_bus_width = 4; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - } + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif -} + /* set SW1C staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -struct i2c_pads_info i2c_pad_info1 = { - .sda = { - .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC, - .gp = IMX_GPIO_NR(3, 13), - }, - .scl = { - .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC, - .gp = IMX_GPIO_NR(3, 12), - }, -}; + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); -int power_init_board(void) -{ - struct pmic *p; + /* Init mode to APS_PFM */ + pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); - p = pfuze_common_init(I2C_PMIC); - if (!p) - return -ENODEV; + for (i = 0; i < switch_num - 1; i++) + pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); - return pfuze_mode_init(p, APS_PFM); + return 0; } #endif @@ -374,9 +267,7 @@ int board_ehci_hcd_init(int port) int board_early_init_f(void) { setup_iomux_uart(); -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif + return 0; } @@ -385,8 +276,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#ifdef CONFIG_MXC_SPI + gpio_request(IMX_GPIO_NR(4, 11), "spi_cs"); + setup_spi(); #endif #ifdef CONFIG_FEC_MXC @@ -411,6 +303,76 @@ int checkboard(void) #include <spl.h> #include <libfdt.h> +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) +#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + /* Boot from USDHC */ + port = (val >> 11) & 0x3; + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, + ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = { .dram_sdqs0 = 0x00003030, .dram_sdqs1 = 0x00003030, diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 42402c0935..fcacd21680 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -26,8 +26,21 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index e03e0a7b9b..f9eba0c1f6 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -27,8 +27,21 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index dcdc747f2e..7d3de1f943 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL,SYS_I2C" CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 19dcc5cfb7..f5af65d761 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -27,19 +27,12 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR /* I2C Configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - #define CONFIG_FEC_MXC #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR |