diff options
647 files changed, 14713 insertions, 2228 deletions
@@ -144,6 +144,7 @@ menu "Boot images" config FIT bool "Support Flattened Image Tree" + select MD5 help This option allows you to boot the new uImage structure, Flattened Image Tree. FIT is formally a FDT, which can include @@ -624,8 +624,9 @@ KBUILD_CFLAGS += $(KCFLAGS) UBOOTINCLUDE := \ -Iinclude \ $(if $(KBUILD_SRC), -I$(srctree)/include) \ - $(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \ - -I$(srctree)/arch/$(ARCH)/thumb1/include),) \ + $(if $(CONFIG_$(SPL_)SYS_THUMB_BUILD), \ + $(if $(CONFIG_HAS_THUMB2),, \ + -I$(srctree)/arch/$(ARCH)/thumb1/include),) \ -I$(srctree)/arch/$(ARCH)/include \ -include $(srctree)/include/linux/kconfig.h @@ -592,14 +592,6 @@ The following options need to be configured: Select high exception vectors of the ARM core, e.g., do not clear the V bit of the c1 register of CP15. - CONFIG_SYS_THUMB_BUILD - - Use this flag to build U-Boot using the Thumb instruction - set for ARM architectures. Thumb instruction set provides - better code density. For ARM architectures that support - Thumb2 this flag will result in Thumb2 code generated by - GCC. - COUNTER_FREQUENCY Generic timer clock source frequency. @@ -3255,10 +3247,6 @@ FIT uImage format: consider that a completely unreadable NAND block is bad, and thus should be skipped silently. - CONFIG_SPL_ABORT_ON_RAW_IMAGE - When defined, SPL will proceed to another boot method - if the image it has loaded does not have a signature. - CONFIG_SPL_RELOC_STACK Adress of the start of the stack SPL will use after relocation. If unspecified, this is equal to diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b1f78520d0..b758745f4a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -181,6 +181,25 @@ config SEMIHOSTING the hosted environment to call out to the emulator to retrieve files from the host machine. +config SYS_THUMB_BUILD + bool "Build U-Boot using the Thumb instruction set" + depends on !ARM64 + help + Use this flag to build U-Boot using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. + +config SPL_SYS_THUMB_BUILD + bool "Build SPL using the Thumb instruction set" + default y if SYS_THUMB_BUILD + depends on !ARM64 + help + Use this flag to build SPL using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. + config SYS_L2CACHE_OFF bool "L2cache off" help @@ -571,6 +590,7 @@ config ARCH_KEYSTONE bool "TI Keystone" select CPU_V7 select SUPPORT_SPL + select SYS_THUMB_BUILD select CMD_POWEROFF config ARCH_MESON @@ -600,6 +620,7 @@ config ARCH_MX6 select SYS_FSL_HAS_SEC if SECURE_BOOT select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE + select SYS_THUMB_BUILD if SPL config ARCH_MX5 bool "Freescale MX5" @@ -659,6 +680,7 @@ config OMAP34XX imply SPL_NAND_SUPPORT imply SPL_POWER_SUPPORT imply SPL_SERIAL_SUPPORT + imply SYS_THUMB_BUILD config OMAP44XX bool "OMAP44XX SoC" @@ -676,11 +698,13 @@ config OMAP44XX imply SPL_NAND_SUPPORT imply SPL_POWER_SUPPORT imply SPL_SERIAL_SUPPORT + imply SYS_THUMB_BUILD config OMAP54XX bool "OMAP54XX SoC" select ARCH_OMAP2 select ARM_ERRATA_798870 + select SYS_THUMB_BUILD imply SPL_DISPLAY_PRINT imply SPL_ENV_SUPPORT imply SPL_EXT_SUPPORT @@ -698,6 +722,7 @@ config OMAP54XX config AM43XX bool "AM43XX SoC" select ARCH_OMAP2 + imply SYS_THUMB_BUILD help Support for AM43xx SOC from Texas Instruments. The AM43xx high performance SOC features a Cortex-A9 @@ -708,6 +733,7 @@ config AM43XX config AM33XX bool "AM33XX SoC" select ARCH_OMAP2 + imply SYS_THUMB_BUILD help Support for AM335x SOC from Texas Instruments. The AM335x high performance SOC features a Cortex-A8 @@ -720,6 +746,7 @@ config ARCH_RMOBILE select DM select DM_SERIAL select BOARD_EARLY_INIT_F + imply SYS_THUMB_BUILD config TARGET_S32V234EVB bool "Support s32v234evb" @@ -749,6 +776,7 @@ config ARCH_SOCFPGA select ARCH_EARLY_INIT_R select ARCH_MISC_INIT select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + select SYS_THUMB_BUILD config TARGET_CM_T43 bool "Support cm_t43" @@ -771,6 +799,7 @@ config ARCH_SUNXI select SPL_STACK_R if SUPPORT_SPL select SPL_SYS_MALLOC_SIMPLE if SUPPORT_SPL select SYS_NS16550 + select SPL_SYS_THUMB_BUILD if !ARM64 select USB if DISTRO_DEFAULTS select USB_STORAGE if DISTRO_DEFAULTS select USB_KEYBOARD if DISTRO_DEFAULTS @@ -810,6 +839,9 @@ config ARCH_ZYNQ select SPL_SEPARATE_BSS if SPL select DM_USB if USB select BLK + select CLK + select SPL_CLK + select CLK_ZYNQ config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" @@ -1077,6 +1109,7 @@ config STM32 select CPU_V7M select DM select DM_SERIAL + select SYS_THUMB_BUILD config ARCH_STI bool "Support STMicrolectronics SoCs" @@ -1096,6 +1129,7 @@ config ARCH_ROCKCHIP select DM select SPL_DM if SPL select SYS_MALLOC_F + select SYS_THUMB_BUILD if !ARM64 select SPL_SYS_MALLOC_SIMPLE if SPL select DM_GPIO select DM_I2C diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 3a81f131e2..08d7d1bc69 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -31,7 +31,7 @@ PLATFORM_RELFLAGS += $(LLVM_RELFLAGS) PLATFORM_CPPFLAGS += -D__ARM__ # Choose between ARM/Thumb instruction sets -ifeq ($(CONFIG_SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always) PF_CPPFLAGS_ARM := $(AFLAGS_IMPLICIT_IT) \ $(call cc-option, -mthumb -mthumb-interwork,\ @@ -44,8 +44,7 @@ PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \ endif # Only test once -ifneq ($(CONFIG_SPL_BUILD),y) -ifeq ($(CONFIG_SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) archprepare: checkthumb checkthumb: @@ -57,7 +56,6 @@ checkthumb: false; \ fi endif -endif # Try if EABI is supported, else fall back to old API, # i. e. for example: @@ -99,7 +97,7 @@ LDFLAGS_u-boot += -pie # # http://sourceware.org/bugzilla/show_bug.cgi?id=12532 # -ifeq ($(CONFIG_SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) ifeq ($(GAS_BUG_12532),) export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \ then echo y; else echo n; fi) diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index 1832b9d148..7aa432a6fc 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -16,6 +16,6 @@ obj-$(CONFIG_S3C24X0) += s3c24x0/ # some files can only build in ARM mode -ifdef CONFIG_SYS_THUMB_BUILD +ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD CFLAGS_cpu.o := -marm endif diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index fe78922170..0f730117c0 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -23,7 +23,7 @@ obj-$(if $(filter spear,$(SOC)),y) += spear/ # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_SYS_THUMB_BUILD +ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cpu.o := -marm diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 02cb24c24f..d56e594af2 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -63,6 +63,6 @@ void flush_dcache_all(void) __weak void l2_cache_disable(void) {} -#if defined CONFIG_SYS_THUMB_BUILD +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) __weak void invalidate_l2_cache(void) {} #endif diff --git a/arch/arm/cpu/armv7/cache_v7_asm.S b/arch/arm/cpu/armv7/cache_v7_asm.S index a433628bf5..bd27ab219c 100644 --- a/arch/arm/cpu/armv7/cache_v7_asm.S +++ b/arch/arm/cpu/armv7/cache_v7_asm.S @@ -7,7 +7,7 @@ #include <linux/sizes.h> #include <asm/system.h> -#ifdef CONFIG_SYS_THUMB_BUILD +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) #define ARM(x...) #define THUMB(x...) x #else diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6c5630c0a8..bd1c3e0335 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -501,7 +501,8 @@ static bool is_aligned(u64 addr, u64 size, u64 align) return !(addr & (align - 1)) && !(size & (align - 1)); } -static u64 set_one_region(u64 start, u64 size, u64 attrs, int level) +/* Use flag to indicate if attrs has more than d-cache attributes */ +static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level) { int levelshift = level2shift(level); u64 levelsize = 1ULL << levelshift; @@ -509,8 +510,13 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, int level) /* Can we can just modify the current level block PTE? */ if (is_aligned(start, size, levelsize)) { - *pte &= ~PMD_ATTRINDX_MASK; - *pte |= attrs; + if (flag) { + *pte &= ~PMD_ATTRMASK; + *pte |= attrs & PMD_ATTRMASK; + } else { + *pte &= ~PMD_ATTRINDX_MASK; + *pte |= attrs & PMD_ATTRINDX_MASK; + } debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level); return levelsize; @@ -560,7 +566,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, u64 r; for (level = 1; level < 4; level++) { - r = set_one_region(start, size, attrs, level); + /* Set d-cache attributes only */ + r = set_one_region(start, size, attrs, false, level); if (r) { /* PTE successfully replaced */ size -= r; @@ -581,6 +588,63 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, flush_dcache_range(real_start, real_start + real_size); } +/* + * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits. + * The procecess is break-before-make. The target region will be marked as + * invalid during the process of changing. + */ +void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) +{ + int level; + u64 r, size, start; + + start = addr; + size = siz; + /* + * Loop through the address range until we find a page granule that fits + * our alignment constraints, then set it to "invalid". + */ + while (size > 0) { + for (level = 1; level < 4; level++) { + /* Set PTE to fault */ + r = set_one_region(start, size, PTE_TYPE_FAULT, true, + level); + if (r) { + /* PTE successfully invalidated */ + size -= r; + start += r; + break; + } + } + } + + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + __asm_invalidate_tlb_all(); + + /* + * Loop through the address range until we find a page granule that fits + * our alignment constraints, then set it to the new cache attributes + */ + start = addr; + size = siz; + while (size > 0) { + for (level = 1; level < 4; level++) { + /* Set PTE to new attributes */ + r = set_one_region(start, size, attrs, true, level); + if (r) { + /* PTE successfully updated */ + size -= r; + start += r; + break; + } + } + } + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + __asm_invalidate_tlb_all(); +} + #else /* CONFIG_SYS_DCACHE_OFF */ /* diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index b5609ff7a6..a99b1c6a99 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -89,6 +89,14 @@ config FSL_LSCH3 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES +config FSL_MC_ENET + bool "Management Complex network" + depends on ARCH_LS2080A + default y + select RESV_RAM + help + Enable Management Complex (MC) network + menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3 @@ -277,6 +285,16 @@ config SYS_FSL_SDHC_CLK_DIV clock, in another word SDHC_clk = Platform_clk / this_divider. endmenu +config RESV_RAM + bool + help + Reserve memory from the top, tracked by gd->arch.resv_ram. This + reserved RAM can be used by special driver that resides in memory + after U-Boot exits. It's up to implementation to allocate and allow + access to this reserved memory. For example, the reserved RAM can + be at the high end of physical memory. The reserve RAM may be + excluded from memory bank(s) passed to OS, or marked as reserved. + config SYS_FSL_ERRATUM_A008336 bool @@ -297,3 +315,11 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool + +config SYS_MC_RSV_MEM_ALIGN + hex "Management Complex reserved memory alignment" + depends on RESV_RAM + default 0x20000000 + help + Reserved memory needs to be aligned for MC to use. Default value + is 512MB. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 335f225181..7e66ee08b5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -101,12 +101,50 @@ static inline void final_mmu_setup(void) { u64 tlb_addr_save = gd->arch.tlb_addr; unsigned int el = current_el(); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE int index; -#endif mem_map = final_map; + /* Update mapping for DDR to actual size */ + for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) { + /* + * Find the entry for DDR mapping and update the address and + * size. Zero-sized mapping will be skipped when creating MMU + * table. + */ + switch (final_map[index].virt) { + case CONFIG_SYS_FSL_DRAM_BASE1: + final_map[index].virt = gd->bd->bi_dram[0].start; + final_map[index].phys = gd->bd->bi_dram[0].start; + final_map[index].size = gd->bd->bi_dram[0].size; + break; +#ifdef CONFIG_SYS_FSL_DRAM_BASE2 + case CONFIG_SYS_FSL_DRAM_BASE2: +#if (CONFIG_NR_DRAM_BANKS >= 2) + final_map[index].virt = gd->bd->bi_dram[1].start; + final_map[index].phys = gd->bd->bi_dram[1].start; + final_map[index].size = gd->bd->bi_dram[1].size; +#else + final_map[index].size = 0; +#endif + break; +#endif +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + case CONFIG_SYS_FSL_DRAM_BASE3: +#if (CONFIG_NR_DRAM_BANKS >= 3) + final_map[index].virt = gd->bd->bi_dram[2].start; + final_map[index].phys = gd->bd->bi_dram[2].start; + final_map[index].size = gd->bd->bi_dram[2].size; +#else + final_map[index].size = 0; +#endif + break; +#endif + default: + break; + } + } + #ifdef CONFIG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { if (el == 3) { @@ -143,21 +181,14 @@ static inline void final_mmu_setup(void) setup_pgtables(); gd->arch.tlb_addr = tlb_addr_save; - /* flush new MMU table */ - flush_dcache_range(gd->arch.tlb_addr, - gd->arch.tlb_addr + gd->arch.tlb_size); + /* Disable cache and MMU */ + dcache_disable(); /* TLBs are invalidated */ + invalidate_icache_all(); /* point TTBR to the new table */ set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), MEMORY_ATTRIBUTES); - /* - * EL3 MMU is already enabled, just need to invalidate TLB to load the - * new table. The new table is compatible with the current table, if - * MMU somehow walks through the new table before invalidation TLB, - * it still works. So we don't need to turn off MMU here. - * When EL2 MMU table is created by calling this function, MMU needs - * to be enabled. - */ + set_sctlr(get_sctlr() | CR_M); } @@ -524,15 +555,277 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size) { phys_size_t ram_top = ram_size; -#ifdef CONFIG_SYS_MEM_TOP_HIDE -#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ #ifdef CONFIG_FSL_MC_ENET + /* The start address of MC reserved memory needs to be aligned. */ ram_top -= mc_get_dram_block_size(); ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); #endif - return ram_top; + return ram_size - ram_top; +} + +phys_size_t get_effective_memsize(void) +{ + phys_size_t ea_size, rem = 0; + + /* + * For ARMv8 SoCs, DDR memory is split into two or three regions. The + * first region is 2GB space at 0x8000_0000. If the memory extends to + * the second region (or the third region if applicable), the secure + * memory and Management Complex (MC) memory should be put into the + * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED + * is set to the size of first region so U-Boot doesn't relocate itself + * into higher address. Should DDR be configured to skip the first + * region, this function needs to be adjusted. + */ + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + ea_size = CONFIG_MAX_MEM_MAPPED; + rem = gd->ram_size - ea_size; + } else { + ea_size = gd->ram_size; + } + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + /* Check if we have enough space for secure memory */ + if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) { + rem -= CONFIG_SYS_MEM_RESERVE_SECURE; + } else { + if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) { + ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + rem = 0; /* Presume MC requires more memory */ + } else { + printf("Error: No enough space for secure memory.\n"); + } + } +#endif + /* Check if we have enough memory for MC */ + if (rem < board_reserve_ram_top(rem)) { + /* Not enough memory in high region to reserve */ + if (ea_size > board_reserve_ram_top(rem)) + ea_size -= board_reserve_ram_top(rem); + else + printf("Error: No enough space for reserved memory.\n"); + } + + return ea_size; +} + +void dram_init_banksize(void) +{ +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY + phys_size_t dp_ddr_size; +#endif + + /* + * gd->ram_size has the total size of DDR memory, less reserved secure + * memory. The DDR extends from low region to high region(s) presuming + * no hole is created with DDR configuration. gd->arch.secure_ram tracks + * the location of secure memory. gd->arch.resv_ram tracks the location + * of reserved memory for Management Complex (MC). + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; + gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - + CONFIG_SYS_DDR_BLOCK2_SIZE; + gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; + } +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; + } +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { + gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE; + gd->arch.secure_ram = gd->bd->bi_dram[2].start + + gd->bd->bi_dram[2].size; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + } else +#endif + { + if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { + gd->bd->bi_dram[1].size -= + CONFIG_SYS_MEM_RESERVE_SECURE; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + } else if (gd->bd->bi_dram[0].size > + CONFIG_SYS_MEM_RESERVE_SECURE) { + gd->bd->bi_dram[0].size -= + CONFIG_SYS_MEM_RESERVE_SECURE; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + } + } +#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ + +#ifdef CONFIG_FSL_MC_ENET + /* Assign memory for MC */ +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bd->bi_dram[2].size >= + board_reserve_ram_top(gd->bd->bi_dram[2].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[2].start + + gd->bd->bi_dram[2].size - + board_reserve_ram_top(gd->bd->bi_dram[2].size); + } else +#endif + { + if (gd->bd->bi_dram[1].size >= + board_reserve_ram_top(gd->bd->bi_dram[1].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size - + board_reserve_ram_top(gd->bd->bi_dram[1].size); + } else if (gd->bd->bi_dram[0].size > + board_reserve_ram_top(gd->bd->bi_dram[0].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - + board_reserve_ram_top(gd->bd->bi_dram[0].size); + } + } +#endif /* CONFIG_FSL_MC_ENET */ + +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE +#error "This SoC shouldn't have DP DDR" +#endif + if (soc_has_dp_ddr()) { + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + CONFIG_DP_DDR_CTRL, + CONFIG_DP_DDR_NUM_CTRLS, + CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, + NULL, NULL, NULL); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } + } +#endif +} + +#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) +void efi_add_known_memory(void) +{ + int i; + phys_addr_t ram_start, start; + phys_size_t ram_size; + u64 pages; + + /* Add RAM */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE +#error "This SoC shouldn't have DP DDR" +#endif + if (i == 2) + continue; /* skip DP-DDR */ +#endif + ram_start = gd->bd->bi_dram[i].start; + ram_size = gd->bd->bi_dram[i].size; +#ifdef CONFIG_RESV_RAM + if (gd->arch.resv_ram >= ram_start && + gd->arch.resv_ram < ram_start + ram_size) + ram_size = gd->arch.resv_ram - ram_start; +#endif + start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; + pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; + + efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, + false); + } +} +#endif + +/* + * Before DDR size is known, early MMU table have DDR mapped as device memory + * to avoid speculative access. To relocate U-Boot to DDR, "normal memory" + * needs to be set for these mappings. + * If a special case configures DDR with holes in the mapping, the holes need + * to be marked as invalid. This is not implemented in this function. + */ +void update_early_mmu_table(void) +{ + if (!gd->arch.tlb_addr) + return; + + if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { + mmu_change_region_attr( + CONFIG_SYS_SDRAM_BASE, + gd->ram_size, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_NS | + PTE_TYPE_VALID); + } else { + mmu_change_region_attr( + CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_DDR_BLOCK1_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_NS | + PTE_TYPE_VALID); +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE +#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE +#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" +#endif + if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > + CONFIG_SYS_DDR_BLOCK2_SIZE) { + mmu_change_region_attr( + CONFIG_SYS_DDR_BLOCK2_BASE, + CONFIG_SYS_DDR_BLOCK2_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_NS | + PTE_TYPE_VALID); + mmu_change_region_attr( + CONFIG_SYS_DDR_BLOCK3_BASE, + gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE - + CONFIG_SYS_DDR_BLOCK2_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_NS | + PTE_TYPE_VALID); + } else +#endif + { + mmu_change_region_attr( + CONFIG_SYS_DDR_BLOCK2_BASE, + gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_NS | + PTE_TYPE_VALID); + } + } +} + +__weak int dram_init(void) +{ + gd->ram_size = initdram(0); +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 9489f85c64..b54a937971 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -233,10 +233,8 @@ int sata_init(void) { struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; -#ifdef CONFIG_ARCH_LS1046A /* Disable SATA ECC */ out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); -#endif out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 1dabdbb305..73a8680741 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -45,9 +45,6 @@ void board_init_f(ulong dummy) { /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#ifdef CONFIG_LS2080A - arch_cpu_init(); -#endif board_early_init_f(); timer_init(); #ifdef CONFIG_LS2080A diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c index d26354e1aa..30e1e34707 100644 --- a/arch/arm/cpu/pxa/cache.c +++ b/arch/arm/cpu/pxa/cache.c @@ -52,6 +52,6 @@ void flush_dcache_all(void) __weak void l2_cache_disable(void) {} -#if defined CONFIG_SYS_THUMB_BUILD +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) __weak void invalidate_l2_cache(void) {} #endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 372e05ecff..afeb43ff66 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-fennec.dtb \ rk3288-tinker.dtb \ rk3288-popmetal.dtb \ + rk3328-evb.dtb \ rk3399-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb diff --git a/arch/arm/dts/imx6ul-isiot.dtsi b/arch/arm/dts/imx6ul-isiot.dtsi index 346079ac32..9a3c35c56a 100644 --- a/arch/arm/dts/imx6ul-isiot.dtsi +++ b/arch/arm/dts/imx6ul-isiot.dtsi @@ -40,8 +40,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/dts-v1/; - #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include "imx6ul.dtsi" diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts index bdc7b980b0..6754625f00 100644 --- a/arch/arm/dts/rk3036-sdk.dts +++ b/arch/arm/dts/rk3036-sdk.dts @@ -51,10 +51,12 @@ }; &usb_host { + vbus-supply = <&vcc5v0_host>; status = "okay"; }; &usb_otg { + vbus-supply = <&vcc5v0_otg>; status = "okay"; }; diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi index ecf5416318..4f4421768d 100644 --- a/arch/arm/dts/rk3036.dtsi +++ b/arch/arm/dts/rk3036.dtsi @@ -23,6 +23,7 @@ serial1 = &uart1; serial2 = &uart2; mmc0 = &emmc; + mmc1 = &sdmmc; }; memory { @@ -265,6 +266,18 @@ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; }; + sdmmc: dwmmc@10214000 { + compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x10214000 0x4000>; + clock-frequency = <37500000>; + max-frequency = <37500000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3036-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi new file mode 100644 index 0000000000..f4d438eb66 --- /dev/null +++ b/arch/arm/dts/rk3188.dtsi @@ -0,0 +1,601 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3188-cru.h> +#include "rk3xxx.dtsi" + +/ { + compatible = "rockchip,rk3188"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + operating-points = < + /* kHz uV */ + 1608000 1350000 + 1416000 1250000 + 1200000 1150000 + 1008000 1075000 + 816000 975000 + 600000 950000 + 504000 925000 + 312000 875000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x3>; + }; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x8000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + + i2s0: i2s@1011a000 { + compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "disabled"; + }; + + spdif: sound@1011e000 { + compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; + reg = <0x1011e000 0x2000>; + #sound-dai-cells = <0>; + clock-names = "hclk", "mclk"; + clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>; + dmas = <&dmac1_s 8>; + dma-names = "tx"; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + status = "disabled"; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + u-boot,dm-spl; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + efuse: efuse@20010000 { + compatible = "rockchip,rockchip-efuse"; + reg = <0x20010000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + + usbphy: phy { + compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@10c { + #phy-cells = <0>; + reg = <0x10c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy1: usb-phy@11c { + #phy-cells = <0>; + reg = <0x11c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3188-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-spl; + + gpio0: gpio0@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg_pull_up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg_pull_down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_rst: emmc-rst { + rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + + emac { + emac_xfer: emac-xfer { + rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */ + <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */ + <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */ + <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */ + <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */ + <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */ + <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */ + <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */ + }; + + emac_mdio: emac-mdio { + rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>, + <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>, + <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, + <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>, + <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>, + <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>, + <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd0_cd: sd0-cd { + rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd0_wp: sd0-wp { + rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd0_pwr: sd0-pwr { + rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd1_cd: sd1-cd { + rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd1_wp: sd1-wp { + rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; + +&emac { + compatible = "rockchip,rk3188-emac"; +}; + +&global_timer { + interrupts = <GIC_PPI 11 0xf04>; +}; + +&grf { + compatible = "rockchip,rk3188-grf", "syscon"; +}; + +&local_timer { + interrupts = <GIC_PPI 13 0xf04>; +}; + +&i2c0 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + compatible = "rockchip,rk3188-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + +&pmu { + compatible = "rockchip,rk3188-pmu", "syscon"; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + +&spi0 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + +&uart0 { + compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; + +&wdt { + compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; +}; diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi index cb7d03e558..4960f3367c 100644 --- a/arch/arm/dts/rk3288-evb.dtsi +++ b/arch/arm/dts/rk3288-evb.dtsi @@ -11,6 +11,13 @@ reg = <0 0x80000000>; }; + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + keys: gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -98,6 +105,21 @@ status = "okay"; }; +&gmac { + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio4 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi index e5be4cb471..dd6ce8b69e 100644 --- a/arch/arm/dts/rk3288-popmetal.dtsi +++ b/arch/arm/dts/rk3288-popmetal.dtsi @@ -203,7 +203,7 @@ pinctrl-0 = <&rgmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts index c0550970ea..22881cb785 100644 --- a/arch/arm/dts/rk3288-tinker.dts +++ b/arch/arm/dts/rk3288-tinker.dts @@ -30,6 +30,12 @@ &pinctrl { u-boot,dm-pre-reloc; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm1 { @@ -41,6 +47,11 @@ reg-shift = <2>; }; +&usb_host1 { + vbus-supply = <&vcc5v0_host>; + status = "okay"; +}; + &sdmmc { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-tinker.dtsi b/arch/arm/dts/rk3288-tinker.dtsi index ceb4e2bdb1..a752458663 100644 --- a/arch/arm/dts/rk3288-tinker.dtsi +++ b/arch/arm/dts/rk3288-tinker.dtsi @@ -110,6 +110,18 @@ startup-delay-us = <100000>; vin-supply = <&vcc_io>; }; + + vcc5v0_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; }; &cpu0 { @@ -149,7 +161,7 @@ pinctrl-0 = <&rgmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts new file mode 100644 index 0000000000..01794edd5c --- /dev/null +++ b/arch/arm/dts/rk3328-evb.dts @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Rockchip RK3328 EVB"; + compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; + + chosen { + stdout-path = &uart2; + }; +}; + +&uart2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + supports-emmc; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi new file mode 100644 index 0000000000..8a98ee3a4f --- /dev/null +++ b/arch/arm/dts/rk3328.dtsi @@ -0,0 +1,1477 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/rk3328-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> + +/ { + compatible = "rockchip,rk3328"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; +// clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + }; + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <40000>; + }; + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <40000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1225000>; + clock-latency-ns = <40000>; + }; + opp@1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1300000>; + clock-latency-ns = <40000>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + i2s0: i2s@ff000000 { + compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff000000 0x0 0x1000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 11>, <&dmac 12>; + #dma-cells = <2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s1: i2s@ff010000 { + compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff010000 0x0 0x1000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 14>, <&dmac 15>; + #dma-cells = <2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s2: i2s@ff020000 { + compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff020000 0x0 0x1000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 0>, <&dmac 1>; + #dma-cells = <2>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2m0_mclk + &i2s2m0_sclk + &i2s2m0_lrcktx + &i2s2m0_lrckrx + &i2s2m0_sdo + &i2s2m0_sdi>; + pinctrl-1 = <&i2s2m0_sleep>; + status = "disabled"; + }; + + spdif: spdif@ff030000 { + compatible = "rockchip,rk3328-spdif"; + reg = <0x0 0xff030000 0x0 0x1000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 10>; + #dma-cells = <1>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm2_tx>; + status = "disabled"; + }; + + grf: syscon@ff100000 { + compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff100000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + io_domains: io-domains { + compatible = "rockchip,rk3328-io-voltage-domain"; + status = "disabled"; + }; + }; + + uart0: serial@ff110000 { + compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff110000 0x0 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 2>, <&dmac 3>; + #dma-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + uart1: serial@ff120000 { + compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff120000 0x0 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "sclk_uart", "pclk_uart"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 4>, <&dmac 5>; + #dma-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; + status = "disabled"; + }; + + uart2: serial@ff130000 { + compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff130000 0x0 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 6>, <&dmac 7>; + #dma-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "disabled"; + }; + + pmu: power-management@ff140000 { + compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff140000 0x0 0x1000>; + }; + + i2c0: i2c@ff150000 { + compatible = "rockchip,rk3328-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + i2c1: i2c@ff160000 { + compatible = "rockchip,rk3328-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c2: i2c@ff170000 { + compatible = "rockchip,rk3328-i2c"; + reg = <0x0 0xff170000 0x0 0x1000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + i2c3: i2c@ff180000 { + compatible = "rockchip,rk3328-i2c"; + reg = <0x0 0xff180000 0x0 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + spi0: spi@ff190000 { + compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff190000 0x0 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 8>, <&dmac 9>; + #dma-cells = <2>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; + status = "disabled"; + }; + + wdt: watchdog@ff1a0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xff1a0000 0x0 0x100>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac: dmac@ff1f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff1f0000 0x0 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + }; + + saradc: saradc@ff280000 { + compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + cru: clock-controller@ff440000 { + compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; + reg = <0x0 0xff440000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = + <&cru DCLK_LCDC>, <&cru SCLK_PDM>, + <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, + <&cru SCLK_UART1>, <&cru SCLK_UART2>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, + <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, + <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, + <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, + <&cru SCLK_SDIO>, <&cru SCLK_TSP>, + <&cru SCLK_WIFI>, <&cru ARMCLK>, + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, + <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, + <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, + <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, + <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, + <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, + <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, + <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; + assigned-clock-parents = + <&cru HDMIPHY>, <&cru PLL_APLL>, + <&cru PLL_GPLL>, <&xin24m>, + <&xin24m>, <&xin24m>; + assigned-clock-rates = + <0>, <61440000>, + <0>, <24000000>, + <24000000>, <24000000>, + <15000000>, <15000000>, + <100000000>, <100000000>, + <100000000>, <100000000>, + <50000000>, <100000000>, + <100000000>, <100000000>, + <50000000>, <50000000>, + <50000000>, <50000000>, + <24000000>, <600000000>, + <491520000>, <1200000000>, + <150000000>, <75000000>, + <75000000>, <150000000>, + <75000000>, <75000000>, + <300000000>, <100000000>, + <300000000>, <200000000>, + <400000000>, <500000000>, + <200000000>, <300000000>, + <300000000>, <250000000>, + <200000000>, <100000000>, + <24000000>, <100000000>, + <150000000>, <50000000>, + <32768>, <32768>; + }; + + sdmmc: rksdmmc@ff500000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff500000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdio: dwmmc@ff510000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff510000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + emmc: rksdmmc@ff520000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff520000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdmmc_ext: rksdmmc@ff5f0000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff5f0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + gic: interrupt-controller@ffb70000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xff811000 0 0x1000>, + <0x0 0xff812000 0 0x2000>, + <0x0 0xff814000 0 0x2000>, + <0x0 0xff816000 0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3328-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@ff210000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff210000 0x0 0x100>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@ff220000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff220000 0x0 0x100>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@ff230000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff230000 0x0 0x100>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@ff240000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff240000 0x0 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_2ma: pcfg-pull-none-2ma { + bias-disable; + drive-strength = <2>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_up_4ma: pcfg-pull-up-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_pull_none_4ma: pcfg-pull-none-4ma { + bias-disable; + drive-strength = <4>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_none_8ma: pcfg-pull-none-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + pcfg_pull_up_12ma: pcfg-pull-up-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + pcfg_input: pcfg-input { + input-enable; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + <2 24 RK_FUNC_1 &pcfg_pull_none>, + <2 25 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + <2 4 RK_FUNC_2 &pcfg_pull_none>, + <2 5 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = + <2 13 RK_FUNC_1 &pcfg_pull_none>, + <2 14 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = + <0 5 RK_FUNC_2 &pcfg_pull_none>, + <0 6 RK_FUNC_2 &pcfg_pull_none>; + }; + i2c3_gpio: i2c3-gpio { + rockchip,pins = + <0 5 RK_FUNC_GPIO &pcfg_pull_none>, + <0 6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi_i2c { + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = + <0 5 RK_FUNC_1 &pcfg_pull_none>, + <0 6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = + <1 9 RK_FUNC_1 &pcfg_pull_up>, + <1 8 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = + <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = + <1 10 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = + <1 10 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = + <3 4 RK_FUNC_4 &pcfg_pull_up>, + <3 6 RK_FUNC_4 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = + <3 7 RK_FUNC_4 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = + <3 5 RK_FUNC_4 &pcfg_pull_none>; + }; + + uart1_rts_gpio: uart1-rts-gpio { + rockchip,pins = + <3 5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart2-0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + <1 0 RK_FUNC_2 &pcfg_pull_up>, + <1 1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2-1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + <2 0 RK_FUNC_1 &pcfg_pull_up>, + <2 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spi0-0 { + spi0m0_clk: spi0m0-clk { + rockchip,pins = + <2 8 RK_FUNC_1 &pcfg_pull_up>; + }; + + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + <2 11 RK_FUNC_1 &pcfg_pull_up>; + }; + + spi0m0_tx: spi0m0-tx { + rockchip,pins = + <2 9 RK_FUNC_1 &pcfg_pull_up>; + }; + + spi0m0_rx: spi0m0-rx { + rockchip,pins = + <2 10 RK_FUNC_1 &pcfg_pull_up>; + }; + + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + <2 12 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi0-1 { + spi0m1_clk: spi0m1-clk { + rockchip,pins = + <3 23 RK_FUNC_2 &pcfg_pull_up>; + }; + + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + <3 26 RK_FUNC_2 &pcfg_pull_up>; + }; + + spi0m1_tx: spi0m1-tx { + rockchip,pins = + <3 25 RK_FUNC_2 &pcfg_pull_up>; + }; + + spi0m1_rx: spi0m1-rx { + rockchip,pins = + <3 24 RK_FUNC_2 &pcfg_pull_up>; + }; + + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins = + <3 27 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi0-2 { + spi0m2_clk: spi0m2-clk { + rockchip,pins = + <3 0 RK_FUNC_4 &pcfg_pull_up>; + }; + + spi0m2_cs0: spi0m2-cs0 { + rockchip,pins = + <3 8 RK_FUNC_3 &pcfg_pull_up>; + }; + + spi0m2_tx: spi0m2-tx { + rockchip,pins = + <3 1 RK_FUNC_4 &pcfg_pull_up>; + }; + + spi0m2_rx: spi0m2-rx { + rockchip,pins = + <3 2 RK_FUNC_4 &pcfg_pull_up>; + }; + }; + + i2s1 { + i2s1_mclk: i2s1-mclk { + rockchip,pins = + <2 15 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sclk: i2s1-sclk { + rockchip,pins = + <2 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_lrckrx: i2s1-lrckrx { + rockchip,pins = + <2 16 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_lrcktx: i2s1-lrcktx { + rockchip,pins = + <2 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sdi: i2s1-sdi { + rockchip,pins = + <2 19 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sdo: i2s1-sdo { + rockchip,pins = + <2 23 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sdio1: i2s1-sdio1 { + rockchip,pins = + <2 20 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sdio2: i2s1-sdio2 { + rockchip,pins = + <2 21 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sdio3: i2s1-sdio3 { + rockchip,pins = + <2 22 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sleep: i2s1-sleep { + rockchip,pins = + <2 15 RK_FUNC_GPIO &pcfg_input_high>, + <2 16 RK_FUNC_GPIO &pcfg_input_high>, + <2 17 RK_FUNC_GPIO &pcfg_input_high>, + <2 18 RK_FUNC_GPIO &pcfg_input_high>, + <2 19 RK_FUNC_GPIO &pcfg_input_high>, + <2 20 RK_FUNC_GPIO &pcfg_input_high>, + <2 21 RK_FUNC_GPIO &pcfg_input_high>, + <2 22 RK_FUNC_GPIO &pcfg_input_high>, + <2 23 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + i2s2-0 { + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + <1 21 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + <1 22 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_lrckrx: i2s2m0-lrckrx { + rockchip,pins = + <1 26 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_lrcktx: i2s2m0-lrcktx { + rockchip,pins = + <1 23 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + <1 24 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + <1 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_sleep: i2s2m0-sleep { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_input_high>, + <1 22 RK_FUNC_GPIO &pcfg_input_high>, + <1 26 RK_FUNC_GPIO &pcfg_input_high>, + <1 23 RK_FUNC_GPIO &pcfg_input_high>, + <1 24 RK_FUNC_GPIO &pcfg_input_high>, + <1 25 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + i2s2-1 { + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + <1 21 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + <3 0 RK_FUNC_6 &pcfg_pull_none>; + }; + + i2s2m1_lrckrx: i2sm1-lrckrx { + rockchip,pins = + <3 8 RK_FUNC_6 &pcfg_pull_none>; + }; + + i2s2m1_lrcktx: i2s2m1-lrcktx { + rockchip,pins = + <3 8 RK_FUNC_4 &pcfg_pull_none>; + }; + + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + <3 2 RK_FUNC_6 &pcfg_pull_none>; + }; + + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + <3 1 RK_FUNC_6 &pcfg_pull_none>; + }; + + i2s2m1_sleep: i2s2m1-sleep { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_input_high>, + <3 0 RK_FUNC_GPIO &pcfg_input_high>, + <3 8 RK_FUNC_GPIO &pcfg_input_high>, + <3 2 RK_FUNC_GPIO &pcfg_input_high>, + <3 1 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + spdif-0 { + spdifm0_tx: spdifm0-tx { + rockchip,pins = + <0 27 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spdif-1 { + spdifm1_tx: spdifm1-tx { + rockchip,pins = + <2 17 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + spdif-2 { + spdifm2_tx: spdifm2-tx { + rockchip,pins = + <0 2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + sdmmc0-0 { + sdmmc0m0_pwren: sdmmc0m0-pwren { + rockchip,pins = + <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0m0_gpio: sdmmc0m0-gpio { + rockchip,pins = + <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc0-1 { + sdmmc0m1_pwren: sdmmc0m1-pwren { + rockchip,pins = + <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0m1_gpio: sdmmc0m1-gpio { + rockchip,pins = + <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc0 { + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; + }; + + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_dectn: sdmmc0-dectn { + rockchip,pins = + <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_wrprt: sdmmc0-wrprt { + rockchip,pins = + <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_bus1: sdmmc0-bus1 { + rockchip,pins = + <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, + <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, + <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, + <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_gpio: sdmmc0-gpio { + rockchip,pins = + <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc0ext { + sdmmc0ext_clk: sdmmc0ext-clk { + rockchip,pins = + <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; + }; + + sdmmc0ext_cmd: sdmmc0ext-cmd { + rockchip,pins = + <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_wrprt: sdmmc0ext-wrprt { + rockchip,pins = + <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_dectn: sdmmc0ext-dectn { + rockchip,pins = + <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_bus1: sdmmc0ext-bus1 { + rockchip,pins = + <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_bus4: sdmmc0ext-bus4 { + rockchip,pins = + <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, + <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, + <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, + <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_gpio: sdmmc0ext-gpio { + rockchip,pins = + <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc1 { + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; + }; + + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_wrprt: sdmmc1-wrprt { + rockchip,pins = + <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_dectn: sdmmc1-dectn { + rockchip,pins = + <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_bus1: sdmmc1-bus1 { + rockchip,pins = + <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, + <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, + <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, + <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_gpio: sdmmc1-gpio { + rockchip,pins = + <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = + <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = + <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = + <3 22 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_rstnout: emmc-rstnout { + rockchip,pins = + <3 20 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = + <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = + <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = + <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, + <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, + <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, + <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = + <2 4 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = + <2 5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = + <2 6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwmir { + pwmir_pin: pwmir-pin { + rockchip,pins = + <2 2 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + gmac-0 { + rgmiim0_pins: rgmiim0-pins { + rockchip,pins = + /* mac_txclk */ + <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_rxclk */ + <0 10 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdio */ + <0 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_clk */ + <0 24 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxdv */ + <0 25 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ + <0 19 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd1 */ + <0 14 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd0 */ + <0 15 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_rxd3 */ + <0 20 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd2 */ + <0 21 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd3 */ + <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_txd2 */ + <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + + rmiim0_pins: rmiim0-pins { + rockchip,pins = + /* mac_mdio */ + <0 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_clk */ + <0 24 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxer */ + <0 13 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxdv */ + <0 25 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ + <0 19 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd1 */ + <0 14 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd0 */ + <0 15 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + }; + + gmac-1 { + rgmiim1_pins: rgmiim1-pins { + rockchip,pins = + /* mac_txclk */ + <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_rxclk */ + <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_mdio */ + <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_txen */ + <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_clk */ + <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxdv */ + <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_mdc */ + <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxd1 */ + <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxd0 */ + <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_txd1 */ + <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_rxd3 */ + <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxd2 */ + <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_txd3 */ + <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_txd2 */ + <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, + + /* mac_txclk */ + <0 8 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <0 12 RK_FUNC_1 &pcfg_pull_none>, + /* mac_clk */ + <0 24 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 16 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd0 */ + <0 17 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd3 */ + <0 23 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd2 */ + <0 22 RK_FUNC_1 &pcfg_pull_none>; + }; + + rmiim1_pins: rmiim1-pins { + rockchip,pins = + /* mac_mdio */ + <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_txen */ + <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_clk */ + <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxer */ + <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxdv */ + <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_mdc */ + <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxd1 */ + <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxd0 */ + <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_txd1 */ + <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, + + /* mac_mdio */ + <0 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <0 12 RK_FUNC_1 &pcfg_pull_none>, + /* mac_clk */ + <0 24 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ + <0 19 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 16 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd0 */ + <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + gmac2phy { + fephyled_speed100: fephyled-speed100 { + rockchip,pins = + <0 31 RK_FUNC_1 &pcfg_pull_none>; + }; + + fephyled_speed10: fephyled-speed10 { + rockchip,pins = + <0 30 RK_FUNC_1 &pcfg_pull_none>; + }; + + fephyled_duplex: fephyled-duplex { + rockchip,pins = + <0 30 RK_FUNC_2 &pcfg_pull_none>; + }; + + fephyled_rxm0: fephyled-rxm0 { + rockchip,pins = + <0 29 RK_FUNC_1 &pcfg_pull_none>; + }; + + fephyled_txm0: fephyled-txm0 { + rockchip,pins = + <0 29 RK_FUNC_2 &pcfg_pull_none>; + }; + + fephyled_linkm0: fephyled-linkm0 { + rockchip,pins = + <0 28 RK_FUNC_1 &pcfg_pull_none>; + }; + + fephyled_rxm1: fephyled-rxm1 { + rockchip,pins = + <2 25 RK_FUNC_2 &pcfg_pull_none>; + }; + + fephyled_txm1: fephyled-txm1 { + rockchip,pins = + <2 25 RK_FUNC_3 &pcfg_pull_none>; + }; + + fephyled_linkm1: fephyled-linkm1 { + rockchip,pins = + <2 24 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + tsadc_pin { + tsadc_int: tsadc-int { + rockchip,pins = + <2 13 RK_FUNC_2 &pcfg_pull_none>; + }; + tsadc_gpio: tsadc-gpio { + rockchip,pins = + <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi_pin { + hdmi_cec: hdmi-cec { + rockchip,pins = + <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + + hdmi_hpd: hdmi-hpd { + rockchip,pins = + <0 4 RK_FUNC_1 &pcfg_pull_down>; + }; + }; + + cif-0 { + dvp_d2d9_m0:dvp-d2d9-m0 { + rockchip,pins = + /* cif_d0 */ + <3 4 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d1 */ + <3 5 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d2 */ + <3 6 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d3 */ + <3 7 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d4 */ + <3 8 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d5m0 */ + <3 9 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d6m0 */ + <3 10 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d7m0 */ + <3 11 RK_FUNC_2 &pcfg_pull_none>, + /* cif_href */ + <3 1 RK_FUNC_2 &pcfg_pull_none>, + /* cif_vsync */ + <3 0 RK_FUNC_2 &pcfg_pull_none>, + /* cif_clkoutm0 */ + <3 3 RK_FUNC_2 &pcfg_pull_none>, + /* cif_clkin */ + <3 2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + cif-1 { + dvp_d2d9_m1:dvp-d2d9-m1 { + rockchip,pins = + /* cif_d0 */ + <3 4 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d1 */ + <3 5 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d2 */ + <3 6 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d3 */ + <3 7 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d4 */ + <3 8 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d5m1 */ + <2 16 RK_FUNC_4 &pcfg_pull_none>, + /* cif_d6m1 */ + <2 17 RK_FUNC_4 &pcfg_pull_none>, + /* cif_d7m1 */ + <2 18 RK_FUNC_4 &pcfg_pull_none>, + /* cif_href */ + <3 1 RK_FUNC_2 &pcfg_pull_none>, + /* cif_vsync */ + <3 0 RK_FUNC_2 &pcfg_pull_none>, + /* cif_clkoutm1 */ + <2 15 RK_FUNC_4 &pcfg_pull_none>, + /* cif_clkin */ + <3 2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index fa60e191ed..a959989735 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -7,6 +7,7 @@ /dts-v1/; #include <dt-bindings/pwm/pwm.h> #include "rk3399.dtsi" +#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" / { model = "Rockchip RK3399 Evaluation Board"; @@ -69,6 +70,7 @@ }; &sdmmc { + bus-width = <4>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi new file mode 100644 index 0000000000..65dfc3806c --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi @@ -0,0 +1,1536 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&dmc { + rockchip,sdram-params = < + 0x2 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + 0x1d191519 + 0x14040808 + 0x00000002 + 0x00006226 + 0x00000054 + 0x00000000 + 0x2 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + 0x1d191519 + 0x14040808 + 0x00000002 + 0x00006226 + 0x00000054 + 0x00000000 + 800 + 6 + 2 + 13 + 1 + 0x00000700 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000050 + 0x00027100 + 0x00000320 + 0x00001f40 + 0x00000050 + 0x00027100 + 0x00000320 + 0x00001f40 + 0x00000050 + 0x00027100 + 0x00000320 + 0x01001f40 + 0x00000000 + 0x00000101 + 0x00020100 + 0x000000a0 + 0x00000190 + 0x00000000 + 0x06180000 + 0x00061800 + 0x04000618 + 0x33080004 + 0x280f0622 + 0x22330800 + 0x00280f06 + 0x06223308 + 0x0600280f + 0x00000a0a + 0x0600dac0 + 0x0a0a060c + 0x0600dac0 + 0x0a0a060c + 0x0600dac0 + 0x0203000c + 0x0f0c0f00 + 0x040c0f0c + 0x14000a0a + 0x03030a0a + 0x00010003 + 0x031b1b1b + 0x00111111 + 0x00000000 + 0x03010000 + 0x0c2800a8 + 0x0c2800a8 + 0x0c2800a8 + 0x00000000 + 0x00060006 + 0x00140006 + 0x00140014 + 0x000f0f0f + 0x00000000 + 0x00000000 + 0x00000000 + 0x00b00000 + 0x00b000b0 + 0x00b000b0 + 0x000000b0 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000301 + 0x00000001 + 0x00000000 + 0x00000000 + 0x01000000 + 0x80104002 + 0x00040003 + 0x00040005 + 0x00030000 + 0x00050004 + 0x00000004 + 0x00040003 + 0x00040005 + 0x30a00000 + 0x00001850 + 0x185030a0 + 0x30a00000 + 0x00001850 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x02020200 + 0x00020202 + 0x00030200 + 0x00040700 + 0x00000302 + 0x02000407 + 0x00000003 + 0x00030f04 + 0x00070004 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00010000 + 0x20040020 + 0x00200400 + 0x01000400 + 0x00000b80 + 0x00000000 + 0x00000001 + 0x00000002 + 0x0000000e + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00a00000 + 0x00c80050 + 0x00c80000 + 0x005000a0 + 0x000000c8 + 0x00a000c8 + 0x00c80050 + 0x00c80000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00430000 + 0x0000001a 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"rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; @@ -416,6 +419,7 @@ }; pmugrf: syscon@ff320000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; #address-cells = <1>; @@ -427,6 +431,12 @@ }; }; + pmusgrf: syscon@ff330000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-pmusgrf", "syscon"; + reg = <0x0 0xff330000 0x0 0xe3d4>; + }; + spi3: spi@ff350000 { compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; reg = <0x0 0xff350000 0x0 0x1000>; @@ -497,7 +507,40 @@ status = "disabled"; }; + cic: syscon@ff620000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-cic", "syscon"; + reg = <0x0 0xff620000 0x0 0x100>; + }; + + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + reg = <0x0 0xffa80000 0x0 0x0800 + 0x0 0xffa80800 0x0 0x1800 + 0x0 0xffa82000 0x0 0x2000 + 0x0 0xffa84000 0x0 0x1000 + 0x0 0xffa88000 0x0 0x0800 + 0x0 0xffa88800 0x0 0x1800 + 0x0 0xffa8a000 0x0 0x2000 + 0x0 0xffa8c000 0x0 0x1000>; + }; + pmucru: pmu-clock-controller@ff750000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; #clock-cells = <1>; @@ -507,6 +550,7 @@ }; cru: clock-controller@ff760000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; #clock-cells = <1>; @@ -530,6 +574,7 @@ }; grf: syscon@ff770000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; @@ -607,6 +652,7 @@ }; pinctrl: pinctrl { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pinctrl"; rockchip,grf = <&grf>; rockchip,pmu = <&pmugrf>; diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi new file mode 100644 index 0000000000..6d9e36d235 --- /dev/null +++ b/arch/arm/dts/rk3xxx.dtsi @@ -0,0 +1,417 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + ethernet0 = &emac; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + mshc0 = &emmc; + mshc1 = &mmc0; + mshc2 = &mmc1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dmac1_s: dma-controller@20018000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20018000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + }; + + dmac1_ns: dma-controller@2001c000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x2001c000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dmac2: dma-controller@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMA2>; + clock-names = "apb_pclk"; + }; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + clock-output-names = "xin24m"; + }; + + L2: l2-cache-controller@10138000 { + compatible = "arm,pl310-cache"; + reg = <0x10138000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + scu@1013c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1013c000 0x100>; + }; + + global_timer: global-timer@1013c200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x1013c200 0x20>; + interrupts = <GIC_PPI 11 0x304>; + clocks = <&cru CORE_PERI>; + }; + + local_timer: local-timer@1013c600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1013c600 0x20>; + interrupts = <GIC_PPI 13 0x304>; + clocks = <&cru CORE_PERI>; + }; + + gic: interrupt-controller@1013d000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1013d000 0x1000>, + <0x1013c100 0x0100>; + }; + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + status = "disabled"; + }; + + uart1: serial@10126000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10126000 0x400>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + status = "disabled"; + }; + + noc: syscon@10128000 { + u-boot,dm-spl; + compatible = "rockchip,rk3188-noc", "syscon"; + reg = <0x10128000 0x2000>; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3066-usb", "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host: usb@101c0000 { + compatible = "snps,dwc2"; + reg = <0x101c0000 0x40000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG1>; + clock-names = "otg"; + dr_mode = "host"; + phys = <&usbphy1>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + emac: ethernet@10204000 { + compatible = "snps,arc-emac"; + reg = <0x10204000 0x3c>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; + clock-names = "hclk", "macref"; + max-speed = <100>; + phy-mode = "rmii"; + + status = "disabled"; + }; + + mmc0: dwmmc@10214000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10214000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <256>; + status = "disabled"; + }; + + mmc1: dwmmc@10218000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x10218000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; + clock-names = "biu", "ciu"; + fifo-depth = <256>; + status = "disabled"; + }; + + emmc: dwmmc@1021c000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x1021c000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <256>; + status = "disabled"; + }; + + pmu: pmu@20004000 { + compatible = "rockchip,rk3066-pmu", "syscon"; + reg = <0x20004000 0x100>; + u-boot,dm-spl; + }; + + grf: grf@20008000 { + compatible = "syscon"; + reg = <0x20008000 0x200>; + u-boot,dm-spl; + }; + + dmc: dmc@20020000 { + /* unreviewed u-boot-specific binding */ + compatible = "rockchip,rk3188-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + rockchip,noc = <&noc>; + reg = <0x20020000 0x3fc + 0x20040000 0x294>; + clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>; + clock-names = "pclk_ddrupctl", "pclk_publ"; + u-boot,dm-spl; + }; + + i2c0: i2c@2002d000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2002d000 0x1000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + + status = "disabled"; + }; + + i2c1: i2c@2002f000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2002f000 0x1000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C1>; + clock-names = "i2c"; + + status = "disabled"; + }; + + pwm0: pwm@20030000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030000 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM01>; + status = "disabled"; + }; + + pwm1: pwm@20030010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030010 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM01>; + status = "disabled"; + }; + + wdt: watchdog@2004c000 { + compatible = "snps,dw-wdt"; + reg = <0x2004c000 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM23>; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM23>; + status = "disabled"; + }; + + i2c2: i2c@20056000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x20056000 0x1000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C2>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c3: i2c@2005a000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2005a000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C3>; + clock-names = "i2c"; + + status = "disabled"; + }; + + i2c4: i2c@2005e000 { + compatible = "rockchip,rk3066-i2c"; + reg = <0x2005e000 0x1000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru PCLK_I2C4>; + clock-names = "i2c"; + + status = "disabled"; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clock-frequency = <24000000>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + status = "disabled"; + }; + + uart3: serial@20068000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20068000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clock-names = "baudclk", "apb_pclk"; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + status = "disabled"; + }; + + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + + spi0: spi@20070000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x20070000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac2 10>, <&dmac2 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@20074000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x20074000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac2 12>, <&dmac2 13>; + dma-names = "tx", "rx"; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index bad0698193..07e0ca7021 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -61,12 +61,24 @@ }; aliases { + serial0 = &usart1; spi0 = &qspi; }; }; +&clk_hse { + clock-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + &mac { status = "okay"; + pinctrl-0 = <ðernet_mii>; phy-mode = "rmii"; phy-handle = <&phy0>; @@ -81,6 +93,7 @@ }; &qspi { + pinctrl-0 = <&qspi_pins>; status = "okay"; qflash0: n25q128a { diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 3902e7625f..b2b0b5f099 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -48,7 +48,16 @@ #include <dt-bindings/pinctrl/stm32f746-pinfunc.h> / { + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + soc { + u-boot,dm-pre-reloc; mac: ethernet@40028000 { compatible = "st,stm32-dwmac"; reg = <0x40028000 0x8000>; @@ -71,6 +80,69 @@ spi-max-frequency = <108000000>; status = "disabled"; }; + usart1: serial@40011000 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 0 164>; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + rcc: rcc@40023810 { + #reset-cells = <1>; + #clock-cells = <2>; + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>; + u-boot,dm-pre-reloc; + }; + + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f746-pinctrl"; + ranges = <0 0x40020000 0x3000>; + u-boot,dm-pre-reloc; + pins-are-numbered; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32F746_PB7_FUNC_USART1_RX>; + bias-disable; + }; + }; + ethernet_mii: mii@0 { + pins { + pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, + <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, + <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, + <STM32F746_PA2_FUNC_ETH_MDIO>, + <STM32F746_PC1_FUNC_ETH_MDC>, + <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, + <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, + <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, + <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; + slew-rate = <2>; + }; + }; + qspi_pins: qspi@0{ + pins { + pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, + <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, + <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, + <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, + <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, + <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; + slew-rate = <2>; + }; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index fa9ee276cb..34fc6e5f89 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -248,12 +248,14 @@ }; slcr: slcr@f8000000 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { + u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0>; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 586ce17215..b5b08aae23 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -33,8 +33,8 @@ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ /* DDR */ -#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_CCSR_GUR_LE #define CONFIG_SYS_FSL_CCSR_SCFG_LE diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 4ea4aeaf4c..bcf3e3863e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -115,7 +115,11 @@ static struct mm_region early_map[] = { }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ @@ -130,7 +134,7 @@ static struct mm_region early_map[] = { }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #elif defined(CONFIG_FSL_LSCH2) @@ -158,12 +162,16 @@ static struct mm_region early_map[] = { }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 43ae686a29..08ea8fb8ef 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -177,21 +177,23 @@ struct ccsr_gur { u8 res_008[0x20-0x8]; u32 gpporcr1; /* General-purpose POR configuration */ u32 gpporcr2; /* General-purpose POR configuration 2 */ -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25 + u32 gpporcr3; + u32 gpporcr4; + u8 res_030[0x60-0x30]; +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20 +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F u32 dcfg_fusesr; /* Fuse status register */ - u32 gpporcr3; - u32 gpporcr4; - u8 res_034[0x70-0x34]; - u32 devdisr; /* Device disable control */ + u8 res_064[0x70-0x64]; + u32 devdisr; /* Device disable control 1 */ u32 devdisr2; /* Device disable control 2 */ u32 devdisr3; /* Device disable control 3 */ u32 devdisr4; /* Device disable control 4 */ u32 devdisr5; /* Device disable control 5 */ u32 devdisr6; /* Device disable control 6 */ - u32 devdisr7; /* Device disable control 7 */ + u8 res_088[0x94-0x88]; + u32 coredisr; /* Device disable control 7 */ #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 @@ -216,15 +218,11 @@ struct ccsr_gur { #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 - u8 res_08c[0x90-0x8c]; - u32 coredisru; /* uppper portion for support of 64 cores */ - u32 coredisrl; /* lower portion for support of 64 cores */ u8 res_098[0xa0-0x98]; u32 pvr; /* Processor version */ u32 svr; /* System version */ - u32 mvr; /* Manufacturing version */ - u8 res_0ac[0x100-0xac]; - u32 rcwsr[32]; /* Reset control word status */ + u8 res_0a8[0x100-0xa8]; + u32 rcwsr[30]; /* Reset control word status */ #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f @@ -239,24 +237,53 @@ struct ccsr_gur { #define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_MASK 0x00000400 - u8 res_180[0x200-0x180]; - u32 scratchrw[32]; /* Scratch Read/Write */ - u8 res_280[0x300-0x280]; + u8 res_178[0x200-0x178]; + u32 scratchrw[16]; /* Scratch Read/Write */ + u8 res_240[0x300-0x240]; u32 scratchw1r[4]; /* Scratch Read (Write once) */ u8 res_310[0x400-0x310]; u32 bootlocptrl; /* Boot location pointer low-order addr */ u32 bootlocptrh; /* Boot location pointer high-order addr */ - u8 res_408[0x500-0x408]; - u8 res_500[0x740-0x500]; /* add more registers when needed */ + u8 res_408[0x520-0x408]; + u32 usb1_amqr; + u32 usb2_amqr; + u8 res_528[0x530-0x528]; /* add more registers when needed */ + u32 sdmm1_amqr; + u8 res_534[0x550-0x534]; /* add more registers when needed */ + u32 sata1_amqr; + u32 sata2_amqr; + u8 res_558[0x570-0x558]; /* add more registers when needed */ + u32 misc1_amqr; + u8 res_574[0x590-0x574]; /* add more registers when needed */ + u32 spare1_amqr; + u32 spare2_amqr; + u8 res_598[0x620-0x598]; /* add more registers when needed */ + u32 gencr[7]; /* General Control Registers */ + u8 res_63c[0x640-0x63c]; /* add more registers when needed */ + u32 cgensr1; /* Core General Status Register */ + u8 res_644[0x660-0x644]; /* add more registers when needed */ + u32 cgencr1; /* Core General Control Register */ + u8 res_664[0x740-0x664]; /* add more registers when needed */ u32 tp_ityp[64]; /* Topology Initiator Type Register */ struct { u32 upper; u32 lower; - } tp_cluster[3]; /* Core Cluster n Topology Register */ - u8 res_858[0x1000-0x858]; + } tp_cluster[4]; /* Core cluster n Topology Register */ + u8 res_864[0x920-0x864]; /* add more registers when needed */ + u32 ioqoscr[8]; /*I/O Quality of Services Register */ + u32 uccr; + u8 res_944[0x960-0x944]; /* add more registers when needed */ + u32 ftmcr; + u8 res_964[0x990-0x964]; /* add more registers when needed */ + u32 coredisablesr; + u8 res_994[0xa00-0x994]; /* add more registers when needed */ + u32 sdbgcr; /*Secure Debug Confifuration Register */ + u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */ + u32 ipbrr1; + u32 ipbrr2; + u8 res_858[0x1000-0xc00]; }; - struct ccsr_clk_cluster_group { struct { u8 res_00[0x10]; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h index d54eacd4a0..d232bec1e4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h @@ -6,5 +6,5 @@ #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ #define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ -#include <asm/arch-armv8/mmu.h> +void update_early_mmu_table(void); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */ diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h new file mode 100644 index 0000000000..79fb1a07ac --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2017 Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_BOOTROM_H +#define _ASM_ARCH_BOOTROM_H + +/* + * Saved Stack pointer address. + * Access might be needed in some special cases. + */ +extern u32 SAVE_SP_ADDR; + +/* + * Hand control back to the bootrom to load another + * boot stage. + */ +extern void back_to_bootrom(void); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 804c77beaa..b06bb6c9ec 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -17,6 +17,8 @@ enum { ROCKCHIP_SYSCON_SGRF, ROCKCHIP_SYSCON_PMU, ROCKCHIP_SYSCON_PMUGRF, + ROCKCHIP_SYSCON_PMUSGRF, + ROCKCHIP_SYSCON_CIC, }; /* Standard Rockchip clock numbers */ @@ -63,6 +65,13 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) */ void *rockchip_get_cru(void); +/** + * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers + * + * @return pointer to registers, or -ve error on error + */ +void *rockchip_get_pmucru(void); + struct rk3288_cru; struct rk3288_grf; diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h new file mode 100644 index 0000000000..74f0fedcc6 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3188_H +#define _ASM_ARCH_CRU_RK3188_H + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (1608 * 1000000) +#define GPLL_HZ (594 * 1000000) +#define CPLL_HZ (384 * 1000000) + +/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */ +#define CPU_ACLK_HZ 297000000 +#define CPU_HCLK_HZ 148500000 +#define CPU_PCLK_HZ 74250000 +#define CPU_H2P_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3188_clk_priv { + struct rk3188_grf *grf; + struct rk3188_cru *cru; + ulong rate; + bool has_bwadj; +}; + +struct rk3188_cru { + struct rk3188_pll { + u32 con0; + u32 con1; + u32 con2; + u32 con3; + } pll[4]; + u32 cru_mode_con; + u32 cru_clksel_con[35]; + u32 cru_clkgate_con[10]; + u32 reserved1[2]; + u32 cru_glb_srst_fst_value; + u32 cru_glb_srst_snd_value; + u32 reserved2[2]; + u32 cru_softrst_con[9]; + u32 cru_misc_con; + u32 reserved3[2]; + u32 cru_glb_cnt_th; +}; +check_member(rk3188_cru, cru_glb_cnt_th, 0x0140); + +/* CRU_CLKSEL0_CON */ +enum { + /* a9_core_div: core = core_src / (a9_core_div + 1) */ + A9_CORE_DIV_SHIFT = 9, + A9_CORE_DIV_MASK = 0x1f, + CORE_PLL_SHIFT = 8, + CORE_PLL_MASK = 1, + CORE_PLL_SELECT_APLL = 0, + CORE_PLL_SELECT_GPLL, + + /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */ + CORE_PERI_DIV_SHIFT = 6, + CORE_PERI_DIV_MASK = 3, + + /* aclk_cpu pll selection */ + CPU_ACLK_PLL_SHIFT = 5, + CPU_ACLK_PLL_MASK = 1, + CPU_ACLK_PLL_SELECT_APLL = 0, + CPU_ACLK_PLL_SELECT_GPLL, + + /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */ + A9_CPU_DIV_SHIFT = 0, + A9_CPU_DIV_MASK = 0x1f, +}; + +/* CRU_CLKSEL1_CON */ +enum { + /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */ + AHB2APB_DIV_SHIFT = 14, + AHB2APB_DIV_MASK = 3, + + /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */ + CPU_PCLK_DIV_SHIFT = 12, + CPU_PCLK_DIV_MASK = 3, + + /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */ + CPU_HCLK_DIV_SHIFT = 8, + CPU_HCLK_DIV_MASK = 3, + + /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */ + CORE_ACLK_DIV_SHIFT = 3, + CORE_ACLK_DIV_MASK = 7, +}; + +/* CRU_CLKSEL10_CON */ +enum { + PERI_SEL_PLL_MASK = 1, + PERI_SEL_PLL_SHIFT = 15, + PERI_SEL_CPLL = 0, + PERI_SEL_GPLL, + + /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */ + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 3, + + /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */ + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3, + + /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */ + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f, +}; +/* CRU_CLKSEL11_CON */ +enum { + HSICPHY_DIV_SHIFT = 8, + HSICPHY_DIV_MASK = 0x3f, + + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x3f, +}; + +/* CRU_CLKSEL12_CON */ +enum { + UART_PLL_SHIFT = 15, + UART_PLL_MASK = 1, + UART_PLL_SELECT_GENERAL = 0, + UART_PLL_SELECT_CODEC, + + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0x3f, + + SDIO_DIV_SHIFT = 0, + SDIO_DIV_MASK = 0x3f, +}; + +/* CRU_CLKSEL25_CON */ +enum { + SPI1_DIV_SHIFT = 8, + SPI1_DIV_MASK = 0x7f, + + SPI0_DIV_SHIFT = 0, + SPI0_DIV_MASK = 0x7f, +}; + +/* CRU_MODE_CON */ +enum { + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORMAL, + GPLL_MODE_DEEP, + + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 3, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORMAL, + CPLL_MODE_DEEP, + + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 3, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORMAL, + DPLL_MODE_DEEP, + + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 3, + APLL_MODE_SLOW = 0, + APLL_MODE_NORMAL, + APLL_MODE_DEEP, +}; + +/* CRU_APLL_CON0 */ +enum { + CLKR_SHIFT = 8, + CLKR_MASK = 0x3f, + + CLKOD_SHIFT = 0, + CLKOD_MASK = 0x3f, +}; + +/* CRU_APLL_CON1 */ +enum { + CLKF_SHIFT = 0, + CLKF_MASK = 0x1fff, +}; + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h new file mode 100644 index 0000000000..948706e9a3 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CRU_RK3328_H_ +#define __ASM_ARCH_CRU_RK3328_H_ + +#include <common.h> + +struct rk3328_clk_priv { + struct rk3328_cru *cru; + ulong rate; +}; + +struct rk3328_cru { + u32 apll_con[5]; + u32 reserved1[3]; + u32 dpll_con[5]; + u32 reserved2[3]; + u32 cpll_con[5]; + u32 reserved3[3]; + u32 gpll_con[5]; + u32 reserved4[3]; + u32 mode_con; + u32 misc; + u32 reserved5[2]; + u32 glb_cnt_th; + u32 glb_rst_st; + u32 glb_srst_snd_value; + u32 glb_srst_fst_value; + u32 npll_con[5]; + u32 reserved6[(0x100 - 0xb4) / 4]; + u32 clksel_con[53]; + u32 reserved7[(0x200 - 0x1d4) / 4]; + u32 clkgate_con[29]; + u32 reserved8[3]; + u32 ssgtbl[32]; + u32 softrst_con[12]; + u32 reserved9[(0x380 - 0x330) / 4]; + u32 sdmmc_con[2]; + u32 sdio_con[2]; + u32 emmc_con[2]; + u32 sdmmc_ext_con[2]; +}; +check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (576 * MHz) +#define CPLL_HZ (594 * MHz) + +#define CLK_CORE_HZ (600 * MHz) +#define ACLKM_CORE_HZ (300 * MHz) +#define PCLK_DBG_HZ (300 * MHz) + +#define PERIHP_ACLK_HZ (144000 * KHz) +#define PERIHP_HCLK_HZ (72000 * KHz) +#define PERIHP_PCLK_HZ (72000 * KHz) + +#define PWM_CLOCK_HZ (74 * MHz) + +enum apll_frequencies { + APLL_816_MHZ, + APLL_600_MHZ, +}; + +#endif /* __ASM_ARCH_CRU_RK3328_H_ */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index 98fba2bd75..cf830d04ea 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -15,6 +15,11 @@ struct rk3399_clk_priv { ulong rate; }; +struct rk3399_pmuclk_priv { + struct rk3399_pmucru *pmucru; + ulong rate; +}; + struct rk3399_pmucru { u32 ppll_con[6]; u32 reserved[0x1a]; diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h new file mode 100644 index 0000000000..3d7929fb71 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_DDR_RK3188_H +#define _ASM_ARCH_DDR_RK3188_H + +#include <asm/arch/ddr_rk3288.h> + +/* + * RK3188 Memory scheduler register map. + */ +struct rk3188_msch { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; +}; +check_member(rk3188_msch, readlatency, 0x0014); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h index fccabcd2c0..9a59075afc 100644 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h @@ -425,6 +425,14 @@ enum { #define START_CMD (1u << 31) +/* + * DDRCONF + * [5:4] row(13+n) + * [1:0] col(9+n), assume bw=2 + */ +#define DDRCONF_ROW_SHIFT 4 +#define DDRCONF_COL_SHIFT 0 + /* DEVTODEV */ #define BUSWRTORD_SHIFT 4 #define BUSRDTOWR_SHIFT 2 diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h new file mode 100644 index 0000000000..ce7bac5338 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h @@ -0,0 +1,589 @@ +/* + * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_GRF_RK3188_H +#define _ASM_ARCH_GRF_RK3188_H + +struct rk3188_grf_gpio_lh { + u32 l; + u32 h; +}; + +struct rk3188_grf { + struct rk3188_grf_gpio_lh gpio_dir[4]; + struct rk3188_grf_gpio_lh gpio_do[4]; + struct rk3188_grf_gpio_lh gpio_en[4]; + + u32 reserved[2]; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_status0; + + u32 busdmac_con[3]; + u32 peridmac_con[4]; + + u32 cpu_con[6]; + u32 reserved0[2]; + + u32 ddrc_con0; + u32 ddrc_stat; + + u32 io_con[5]; + u32 soc_status1; + + u32 uoc0_con[4]; + u32 uoc1_con[4]; + u32 uoc2_con[2]; + u32 reserved1; + u32 uoc3_con[2]; + u32 hsic_stat; + u32 os_reg[8]; + + u32 gpio0_p[3]; + u32 gpio1_p[3][4]; + + u32 flash_data_p; + u32 flash_cmd_p; +}; +check_member(rk3188_grf, flash_cmd_p, 0x01a4); + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D7_SHIFT = 14, + GPIO0D7_MASK = 1, + GPIO0D7_GPIO = 0, + GPIO0D7_SPI1_CSN0, + + GPIO0D6_SHIFT = 12, + GPIO0D6_MASK = 1, + GPIO0D6_GPIO = 0, + GPIO0D6_SPI1_CLK, + + GPIO0D5_SHIFT = 10, + GPIO0D5_MASK = 1, + GPIO0D5_GPIO = 0, + GPIO0D5_SPI1_TXD, + + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 1, + GPIO0D4_GPIO = 0, + GPIO0D4_SPI0_RXD, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 3, + GPIO0D3_GPIO = 0, + GPIO0D3_FLASH_CSN3, + GPIO0D3_EMMC_RSTN_OUT, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 3, + GPIO0D2_GPIO = 0, + GPIO0D2_FLASH_CSN2, + GPIO0D2_EMMC_CMD, + + GPIO0D1_SHIFT = 2, + GPIO0D1_MASK = 1, + GPIO0D1_GPIO = 0, + GPIO0D1_FLASH_CSN1, + + GPIO0D0_SHIFT = 0, + GPIO0D0_MASK = 3, + GPIO0D0_GPIO = 0, + GPIO0D0_FLASH_DQS, + GPIO0D0_EMMC_CLKOUT +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A7_SHIFT = 14, + GPIO1A7_MASK = 3, + GPIO1A7_GPIO = 0, + GPIO1A7_UART1_RTS_N, + GPIO1A7_SPI0_CSN0, + + GPIO1A6_SHIFT = 12, + GPIO1A6_MASK = 3, + GPIO1A6_GPIO = 0, + GPIO1A6_UART1_CTS_N, + GPIO1A6_SPI0_CLK, + + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 3, + GPIO1A5_GPIO = 0, + GPIO1A5_UART1_SOUT, + GPIO1A5_SPI0_TXD, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 3, + GPIO1A4_GPIO = 0, + GPIO1A4_UART1_SIN, + GPIO1A4_SPI0_RXD, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1, + GPIO1A3_GPIO = 0, + GPIO1A3_UART0_RTS_N, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 1, + GPIO1A2_GPIO = 0, + GPIO1A2_UART0_CTS_N, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 1, + GPIO1A1_GPIO = 0, + GPIO1A1_UART0_SOUT, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 1, + GPIO1A0_GPIO = 0, + GPIO1A0_UART0_SIN, +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 1, + GPIO1B7_GPIO = 0, + GPIO1B7_SPI0_CSN1, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 3, + GPIO1B6_GPIO = 0, + GPIO1B6_SPDIF_TX, + GPIO1B6_SPI1_CSN1, + + GPIO1B5_SHIFT = 10, + GPIO1B5_MASK = 3, + GPIO1B5_GPIO = 0, + GPIO1B5_UART3_RTS_N, + GPIO1B5_RESERVED, + + GPIO1B4_SHIFT = 8, + GPIO1B4_MASK = 3, + GPIO1B4_GPIO = 0, + GPIO1B4_UART3_CTS_N, + GPIO1B4_GPS_RFCLK, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 3, + GPIO1B3_GPIO = 0, + GPIO1B3_UART3_SOUT, + GPIO1B3_GPS_SIG, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3, + GPIO1B2_GPIO = 0, + GPIO1B2_UART3_SIN, + GPIO1B2_GPS_MAG, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3, + GPIO1B1_GPIO = 0, + GPIO1B1_UART2_SOUT, + GPIO1B1_JTAG_TDO, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3, + GPIO1B0_GPIO = 0, + GPIO1B0_UART2_SIN, + GPIO1B0_JTAG_TDI, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 1, + GPIO1D7_GPIO = 0, + GPIO1D7_I2C4_SCL, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 1, + GPIO1D6_GPIO = 0, + GPIO1D6_I2C4_SDA, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 1, + GPIO1D5_GPIO = 0, + GPIO1D5_I2C2_SCL, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 1, + GPIO1D4_GPIO = 0, + GPIO1D4_I2C2_SDA, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 1, + GPIO1D3_GPIO = 0, + GPIO1D3_I2C1_SCL, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 1, + GPIO1D2_GPIO = 0, + GPIO1D2_I2C1_SDA, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 1, + GPIO1D1_GPIO = 0, + GPIO1D1_I2C0_SCL, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 1, + GPIO1D0_GPIO = 0, + GPIO1D0_I2C0_SDA, +}; + +/* GRF_GPIO3A_IOMUX */ +enum { + GPIO3A7_SHIFT = 14, + GPIO3A7_MASK = 1, + GPIO3A7_GPIO = 0, + GPIO3A7_SDMMC0_DATA3, + + GPIO3A6_SHIFT = 12, + GPIO3A6_MASK = 1, + GPIO3A6_GPIO = 0, + GPIO3A6_SDMMC0_DATA2, + + GPIO3A5_SHIFT = 10, + GPIO3A5_MASK = 1, + GPIO3A5_GPIO = 0, + GPIO3A5_SDMMC0_DATA1, + + GPIO3A4_SHIFT = 8, + GPIO3A4_MASK = 1, + GPIO3A4_GPIO = 0, + GPIO3A4_SDMMC0_DATA0, + + GPIO3A3_SHIFT = 6, + GPIO3A3_MASK = 1, + GPIO3A3_GPIO = 0, + GPIO3A3_SDMMC0_CMD, + + GPIO3A2_SHIFT = 4, + GPIO3A2_MASK = 1, + GPIO3A2_GPIO = 0, + GPIO3A2_SDMMC0_CLKOUT, + + GPIO3A1_SHIFT = 2, + GPIO3A1_MASK = 1, + GPIO3A1_GPIO = 0, + GPIO3A1_SDMMC0_PWREN, + + GPIO3A0_SHIFT = 0, + GPIO3A0_MASK = 1, + GPIO3A0_GPIO = 0, + GPIO3A0_SDMMC0_RSTN, +}; + +/* GRF_GPIO3B_IOMUX */ +enum { + GPIO3B7_SHIFT = 14, + GPIO3B7_MASK = 3, + GPIO3B7_GPIO = 0, + GPIO3B7_CIF_DATA11, + GPIO3B7_I2C3_SCL, + + GPIO3B6_SHIFT = 12, + GPIO3B6_MASK = 3, + GPIO3B6_GPIO = 0, + GPIO3B6_CIF_DATA10, + GPIO3B6_I2C3_SDA, + + GPIO3B5_SHIFT = 10, + GPIO3B5_MASK = 3, + GPIO3B5_GPIO = 0, + GPIO3B5_CIF_DATA1, + GPIO3B5_HSADC_DATA9, + + GPIO3B4_SHIFT = 8, + GPIO3B4_MASK = 3, + GPIO3B4_GPIO = 0, + GPIO3B4_CIF_DATA0, + GPIO3B4_HSADC_DATA8, + + GPIO3B3_SHIFT = 6, + GPIO3B3_MASK = 1, + GPIO3B3_GPIO = 0, + GPIO3B3_CIF_CLKOUT, + + GPIO3B2_SHIFT = 4, + GPIO3B2_MASK = 1, + GPIO3B2_GPIO = 0, + /* no muxes */ + + GPIO3B1_SHIFT = 2, + GPIO3B1_MASK = 1, + GPIO3B1_GPIO = 0, + GPIO3B1_SDMMC0_WRITE_PRT, + + GPIO3B0_SHIFT = 0, + GPIO3B0_MASK = 1, + GPIO3B0_GPIO = 0, + GPIO3B0_SDMMC_DETECT_N, +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C7_SHIFT = 14, + GPIO3C7_MASK = 3, + GPIO3C7_GPIO = 0, + GPIO3C7_SDMMC1_WRITE_PRT, + GPIO3C7_RMII_CRS_DVALID, + GPIO3C7_RESERVED, + + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 3, + GPIO3C6_GPIO = 0, + GPIO3C6_SDMMC1_DECTN, + GPIO3C6_RMII_RX_ERR, + GPIO3C6_RESERVED, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 3, + GPIO3C5_GPIO = 0, + GPIO3C5_SDMMC1_CLKOUT, + GPIO3C5_RMII_CLKOUT, + GPIO3C5_RMII_CLKIN, + + GPIO3C4_SHIFT = 8, + GPIO3C4_MASK = 3, + GPIO3C4_GPIO = 0, + GPIO3C4_SDMMC1_DATA3, + GPIO3C4_RMII_RXD1, + GPIO3C4_RESERVED, + + GPIO3C3_SHIFT = 6, + GPIO3C3_MASK = 3, + GPIO3C3_GPIO = 0, + GPIO3C3_SDMMC1_DATA2, + GPIO3C3_RMII_RXD0, + GPIO3C3_RESERVED, + + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 3, + GPIO3C2_GPIO = 0, + GPIO3C2_SDMMC1_DATA1, + GPIO3C2_RMII_TXD0, + GPIO3C2_RESERVED, + + GPIO3C1_SHIFT = 2, + GPIO3C1_MASK = 3, + GPIO3C1_GPIO = 0, + GPIO3C1_SDMMC1_DATA0, + GPIO3C1_RMII_TXD1, + GPIO3C1_RESERVED, + + GPIO3C0_SHIFT = 0, + GPIO3C0_MASK = 3, + GPIO3C0_GPIO = 0, + GPIO3C0_SDMMC1_CMD, + GPIO3C0_RMII_TX_EN, + GPIO3C0_RESERVED, +}; + +/* GRF_GPIO3D_IOMUX */ +enum { + GPIO3D6_SHIFT = 12, + GPIO3D6_MASK = 3, + GPIO3D6_GPIO = 0, + GPIO3D6_PWM_3, + GPIO3D6_JTAG_TMS, + GPIO3D6_HOST_DRV_VBUS, + + GPIO3D5_SHIFT = 10, + GPIO3D5_MASK = 3, + GPIO3D5_GPIO = 0, + GPIO3D5_PWM_2, + GPIO3D5_JTAG_TCK, + GPIO3D5_OTG_DRV_VBUS, + + GPIO3D4_SHIFT = 8, + GPIO3D4_MASK = 3, + GPIO3D4_GPIO = 0, + GPIO3D4_PWM_1, + GPIO3D4_JTAG_TRSTN, + + GPIO3D3_SHIFT = 6, + GPIO3D3_MASK = 3, + GPIO3D3_GPIO = 0, + GPIO3D3_PWM_0, + + GPIO3D2_SHIFT = 4, + GPIO3D2_MASK = 3, + GPIO3D2_GPIO = 0, + GPIO3D2_SDMMC1_INT_N, + + GPIO3D1_SHIFT = 2, + GPIO3D1_MASK = 3, + GPIO3D1_GPIO = 0, + GPIO3D1_SDMMC1_BACKEND_PWR, + GPIO3D1_MII_MDCLK, + + GPIO3D0_SHIFT = 0, + GPIO3D0_MASK = 3, + GPIO3D0_GPIO = 0, + GPIO3D0_SDMMC1_PWR_EN, + GPIO3D0_MII_MD, +}; + +/* GRF_SOC_CON0 */ +enum { + HSADC_CLK_DIR_SHIFT = 15, + HSADC_CLK_DIR_MASK = 1, + + HSADC_SEL_SHIFT = 14, + HSADC_SEL_MASK = 1, + + NOC_REMAP_SHIFT = 12, + NOC_REMAP_MASK = 1, + + EMMC_FLASH_SEL_SHIFT = 11, + EMMC_FLASH_SEL_MASK = 1, + + TZPC_REVISION_SHIFT = 7, + TZPC_REVISION_MASK = 0xf, + + L2CACHE_ACC_SHIFT = 5, + L2CACHE_ACC_MASK = 3, + + L2RD_WAIT_SHIFT = 3, + L2RD_WAIT_MASK = 3, + + IMEMRD_WAIT_SHIFT = 1, + IMEMRD_WAIT_MASK = 3, +}; + +/* GRF_SOC_CON1 */ +enum { + RKI2C4_SEL_SHIFT = 15, + RKI2C4_SEL_MASK = 1, + + RKI2C3_SEL_SHIFT = 14, + RKI2C3_SEL_MASK = 1, + + RKI2C2_SEL_SHIFT = 13, + RKI2C2_SEL_MASK = 1, + + RKI2C1_SEL_SHIFT = 12, + RKI2C1_SEL_MASK = 1, + + RKI2C0_SEL_SHIFT = 11, + RKI2C0_SEL_MASK = 1, + + VCODEC_SEL_SHIFT = 10, + VCODEC_SEL_MASK = 1, + + PERI_EMEM_PAUSE_SHIFT = 9, + PERI_EMEM_PAUSE_MASK = 1, + + PERI_USB_PAUSE_SHIFT = 8, + PERI_USB_PAUSE_MASK = 1, + + SMC_MUX_MODE_0_SHIFT = 6, + SMC_MUX_MODE_0_MASK = 1, + + SMC_SRAM_MW_0_SHIFT = 4, + SMC_SRAM_MW_0_MASK = 3, + + SMC_REMAP_0_SHIFT = 3, + SMC_REMAP_0_MASK = 1, + + SMC_A_GT_M0_SYNC_SHIFT = 2, + SMC_A_GT_M0_SYNC_MASK = 1, + + EMAC_SPEED_SHIFT = 1, + EMAC_SPEEC_MASK = 1, + + EMAC_MODE_SHIFT = 0, + EMAC_MODE_MASK = 1, +}; + +/* GRF_SOC_CON2 */ +enum { + SDIO_CLK_OUT_SR_SHIFT = 15, + SDIO_CLK_OUT_SR_MASK = 1, + + MEM_EMA_L2C_SHIFT = 11, + MEM_EMA_L2C_MASK = 7, + + MEM_EMA_A9_SHIFT = 8, + MEM_EMA_A9_MASK = 7, + + MSCH4_MAINDDR3_SHIFT = 7, + MSCH4_MAINDDR3_MASK = 1, + MSCH4_MAINDDR3_DDR3 = 1, + + EMAC_NEWRCV_EN_SHIFT = 6, + EMAC_NEWRCV_EN_MASK = 1, + + SW_ADDR15_EN_SHIFT = 5, + SW_ADDR15_EN_MASK = 1, + + SW_ADDR16_EN_SHIFT = 4, + SW_ADDR16_EN_MASK = 1, + + SW_ADDR17_EN_SHIFT = 3, + SW_ADDR17_EN_MASK = 1, + + BANK2_TO_RANK_EN_SHIFT = 2, + BANK2_TO_RANK_EN_MASK = 1, + + RANK_TO_ROW15_EN_SHIFT = 1, + RANK_TO_ROW15_EN_MASK = 1, + + UPCTL_C_ACTIVE_IN_SHIFT = 0, + UPCTL_C_ACTIVE_IN_MASK = 1, + UPCTL_C_ACTIVE_IN_MAY = 0, + UPCTL_C_ACTIVE_IN_WILL, +}; + +/* GRF_DDRC_CON0 */ +enum { + DDR_16BIT_EN_SHIFT = 15, + DDR_16BIT_EN_MASK = 1, + + DTO_LB_SHIFT = 11, + DTO_LB_MASK = 3, + + DTO_TE_SHIFT = 9, + DTO_TE_MASK = 3, + + DTO_PDR_SHIFT = 7, + DTO_PDR_MASK = 3, + + DTO_PDD_SHIFT = 5, + DTO_PDD_MASK = 3, + + DTO_IOM_SHIFT = 3, + DTO_IOM_MASK = 3, + + DTO_OE_SHIFT = 1, + DTO_OE_MASK = 3, + + ATO_AE_SHIFT = 0, + ATO_AE_MASK = 1, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h new file mode 100644 index 0000000000..2776cefbb2 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__ +#define __SOC_ROCKCHIP_RK3328_GRF_H__ + +struct rk3328_grf_regs { + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2bl_iomux; + u32 gpio2bh_iomux; + u32 gpio2cl_iomux; + u32 gpio2ch_iomux; + u32 gpio2d_iomux; + u32 gpio3al_iomux; + u32 gpio3ah_iomux; + u32 gpio3bl_iomux; + u32 gpio3bh_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + u32 com_iomux; + u32 reserved1[(0x100 - 0x54) / 4]; + + u32 gpio0a_p; + u32 gpio0b_p; + u32 gpio0c_p; + u32 gpio0d_p; + u32 gpio1a_p; + u32 gpio1b_p; + u32 gpio1c_p; + u32 gpio1d_p; + u32 gpio2a_p; + u32 gpio2b_p; + u32 gpio2c_p; + u32 gpio2d_p; + u32 gpio3a_p; + u32 gpio3b_p; + u32 gpio3c_p; + u32 gpio3d_p; + u32 reserved2[(0x200 - 0x140) / 4]; + u32 gpio0a_e; + u32 gpio0b_e; + u32 gpio0c_e; + u32 gpio0d_e; + u32 gpio1a_e; + u32 gpio1b_e; + u32 gpio1c_e; + u32 gpio1d_e; + u32 gpio2a_e; + u32 gpio2b_e; + u32 gpio2c_e; + u32 gpio2d_e; + u32 gpio3a_e; + u32 gpio3b_e; + u32 gpio3c_e; + u32 gpio3d_e; + u32 reserved3[(0x300 - 0x240) / 4]; + u32 gpio0l_sr; + u32 gpio0h_sr; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 gpio2l_sr; + u32 gpio2h_sr; + u32 gpio3l_sr; + u32 gpio3h_sr; + u32 reserved4[(0x380 - 0x320) / 4]; + u32 gpio0l_smt; + u32 gpio0h_smt; + u32 gpio1l_smt; + u32 gpio1h_smt; + u32 gpio2l_smt; + u32 gpio2h_smt; + u32 gpio3l_smt; + u32 gpio3h_smt; + u32 reserved5[(0x400 - 0x3a0) / 4]; + u32 soc_con[11]; + u32 reserved6[(0x480 - 0x42c) / 4]; + u32 soc_status[5]; + u32 reserved7[(0x4c0 - 0x494) / 4]; + u32 otg3_con[2]; + u32 reserved8[(0x500 - 0x4c8) / 4]; + u32 cpu_con[2]; + u32 reserved9[(0x520 - 0x508) / 4]; + u32 cpu_status[2]; + u32 reserved10[(0x5c8 - 0x528) / 4]; + u32 os_reg[8]; + u32 reserved11[(0x680 - 0x5e8) / 4]; + u32 sig_detect_con; + u32 reserved12[3]; + u32 sig_detect_status; + u32 reserved13[3]; + u32 sig_detect_status_clr; + u32 reserved14[3]; + + u32 sdmmc_det_counter; + u32 reserved15[(0x700 - 0x6b4) / 4]; + u32 host0_con[3]; + u32 reserved16[(0x880 - 0x70c) / 4]; + u32 otg_con0; + u32 reserved17[3]; + u32 host0_status; + u32 reserved18[(0x900 - 0x894) / 4]; + u32 mac_con[3]; + u32 reserved19[(0xb00 - 0x90c) / 4]; + u32 macphy_con[4]; + u32 macphy_status; +}; +check_member(rk3328_grf_regs, macphy_status, 0xb10); + +struct rk3328_sgrf_regs { + u32 soc_con[6]; + u32 reserved0[(0x100 - 0x18) / 4]; + u32 dmac_con[6]; + u32 reserved1[(0x180 - 0x118) / 4]; + u32 fast_boot_addr; + u32 reserved2[(0x200 - 0x184) / 4]; + u32 chip_fuse_con; + u32 reserved3[(0x280 - 0x204) / 4]; + u32 hdcp_key_reg[8]; + u32 hdcp_key_access_mask; +}; +check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0); + +#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index d3d1467ea4..62d8496ca5 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -318,4 +318,122 @@ struct rk3399_pmusgrf_regs { }; check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); +enum { + /* GRF_GPIO2B_IOMUX */ + GRF_GPIO2B1_SEL_SHIFT = 0, + GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT, + GRF_SPI2TPM_RXD = 1, + GRF_GPIO2B2_SEL_SHIFT = 2, + GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT, + GRF_SPI2TPM_TXD = 1, + GRF_GPIO2B3_SEL_SHIFT = 6, + GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT, + GRF_SPI2TPM_CLK = 1, + GRF_GPIO2B4_SEL_SHIFT = 8, + GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT, + GRF_SPI2TPM_CSN0 = 1, + + /* GRF_GPIO3A_IOMUX */ + GRF_GPIO3A4_SEL_SHIFT = 8, + GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, + GRF_SPI0NORCODEC_RXD = 2, + GRF_GPIO3A5_SEL_SHIFT = 10, + GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, + GRF_SPI0NORCODEC_TXD = 2, + GRF_GPIO3A6_SEL_SHIFT = 12, + GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, + GRF_SPI0NORCODEC_CLK = 2, + GRF_GPIO3A7_SEL_SHIFT = 14, + GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, + GRF_SPI0NORCODEC_CSN0 = 2, + + /* GRF_GPIO3B_IOMUX */ + GRF_GPIO3B0_SEL_SHIFT = 0, + GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, + GRF_SPI0NORCODEC_CSN1 = 2, + + /* GRF_GPIO4B_IOMUX */ + GRF_GPIO4B0_SEL_SHIFT = 0, + GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT, + GRF_SDMMC_DATA0 = 1, + GRF_UART2DBGA_SIN = 2, + GRF_GPIO4B1_SEL_SHIFT = 2, + GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT, + GRF_SDMMC_DATA1 = 1, + GRF_UART2DBGA_SOUT = 2, + GRF_GPIO4B2_SEL_SHIFT = 4, + GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT, + GRF_SDMMC_DATA2 = 1, + GRF_GPIO4B3_SEL_SHIFT = 6, + GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT, + GRF_SDMMC_DATA3 = 1, + GRF_GPIO4B4_SEL_SHIFT = 8, + GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT, + GRF_SDMMC_CLKOUT = 1, + GRF_GPIO4B5_SEL_SHIFT = 10, + GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT, + GRF_SDMMC_CMD = 1, + + /* GRF_GPIO4C_IOMUX */ + GRF_GPIO4C0_SEL_SHIFT = 0, + GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT, + GRF_UART2DGBB_SIN = 2, + GRF_GPIO4C1_SEL_SHIFT = 2, + GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT, + GRF_UART2DGBB_SOUT = 2, + GRF_GPIO4C2_SEL_SHIFT = 4, + GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, + GRF_PWM_0 = 1, + GRF_GPIO4C3_SEL_SHIFT = 6, + GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, + GRF_UART2DGBC_SIN = 1, + GRF_GPIO4C4_SEL_SHIFT = 8, + GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, + GRF_UART2DBGC_SOUT = 1, + GRF_GPIO4C6_SEL_SHIFT = 12, + GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT, + GRF_PWM_1 = 1, + + /* GRF_SOC_CON7 */ + GRF_UART_DBG_SEL_SHIFT = 10, + GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, + GRF_UART_DBG_SEL_C = 2, + + /* PMUGRF_GPIO0A_IOMUX */ + PMUGRF_GPIO0A6_SEL_SHIFT = 12, + PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, + PMUGRF_PWM_3A = 1, + + /* PMUGRF_GPIO1A_IOMUX */ + PMUGRF_GPIO1A7_SEL_SHIFT = 14, + PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT, + PMUGRF_SPI1EC_RXD = 2, + + /* PMUGRF_GPIO1B_IOMUX */ + PMUGRF_GPIO1B0_SEL_SHIFT = 0, + PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT, + PMUGRF_SPI1EC_TXD = 2, + PMUGRF_GPIO1B1_SEL_SHIFT = 2, + PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT, + PMUGRF_SPI1EC_CLK = 2, + PMUGRF_GPIO1B2_SEL_SHIFT = 4, + PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT, + PMUGRF_SPI1EC_CSN0 = 2, + PMUGRF_GPIO1B6_SEL_SHIFT = 12, + PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT, + PMUGRF_PWM_3B = 1, + PMUGRF_GPIO1B7_SEL_SHIFT = 14, + PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT, + PMUGRF_I2C0PMU_SDA = 2, + + /* PMUGRF_GPIO1C_IOMUX */ + PMUGRF_GPIO1C0_SEL_SHIFT = 0, + PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT, + PMUGRF_I2C0PMU_SCL = 2, + PMUGRF_GPIO1C3_SEL_SHIFT = 6, + PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT, + PMUGRF_PWM_2 = 1, + +}; + #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h new file mode 100644 index 0000000000..d3feac3832 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_PMU_RK3188_H +#define _ASM_ARCH_PMU_RK3188_H + +struct rk3188_pmu { + u32 wakeup_cfg[2]; + u32 pwrdn_con; + u32 pwrdn_st; + + u32 int_con; + u32 int_st; + u32 misc_con; + + u32 osc_cnt; + u32 pll_cnt; + u32 pmu_cnt; + u32 ddrio_pwron_cnt; + u32 wakeup_rst_clr_cnt; + u32 scu_pwrdwn_cnt; + u32 scu_pwrup_cnt; + u32 misc_con1; + u32 gpio0_con; + + u32 sys_reg[4]; + u32 reserved0[4]; + u32 stop_int_dly; + u32 gpio0_p[2]; +}; +check_member(rk3188_pmu, gpio0_p[1], 0x0068); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h new file mode 100644 index 0000000000..22a6ca9ae1 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SDRAM_RK3399_H +#define _ASM_ARCH_SDRAM_RK3399_H + +enum { + DDR3 = 0x3, + LPDDR2 = 0x5, + LPDDR3 = 0x6, + LPDDR4 = 0x7, + UNUSED = 0xFF +}; + +struct rk3399_ddr_pctl_regs { + u32 denali_ctl[332]; +}; + +struct rk3399_ddr_publ_regs { + u32 denali_phy[959]; +}; + +struct rk3399_ddr_pi_regs { + u32 denali_pi[200]; +}; + +struct rk3399_msch_regs { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrsize; + u32 ddrtiminga0; + u32 ddrtimingb0; + u32 ddrtimingc0; + u32 devtodev0; + u32 reserved0[(0x110 - 0x20) / 4]; + u32 ddrmode; + u32 reserved1[(0x1000 - 0x114) / 4]; + u32 agingx0; +}; + +struct rk3399_msch_timings { + u32 ddrtiminga0; + u32 ddrtimingb0; + u32 ddrtimingc0; + u32 devtodev0; + u32 ddrmode; + u32 agingx0; +}; + +struct rk3399_ddr_cic_regs { + u32 cic_ctrl0; + u32 cic_ctrl1; + u32 cic_idle_th; + u32 cic_cg_wait_th; + u32 cic_status0; + u32 cic_status1; + u32 cic_ctrl2; + u32 cic_ctrl3; + u32 cic_ctrl4; +}; + +/* DENALI_CTL_00 */ +#define START 1 + +/* DENALI_CTL_68 */ +#define PWRUP_SREFRESH_EXIT (1 << 16) + +/* DENALI_CTL_274 */ +#define MEM_RST_VALID 1 + +struct rk3399_sdram_channel { + unsigned int rank; + /* dram column number, 0 means this channel is invalid */ + unsigned int col; + /* dram bank number, 3:8bank, 2:4bank */ + unsigned int bk; + /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int bw; + /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int dbw; + /* + * row_3_4 = 1: 6Gb or 12Gb die + * row_3_4 = 0: normal die, power of 2 + */ + unsigned int row_3_4; + unsigned int cs0_row; + unsigned int cs1_row; + unsigned int ddrconfig; + struct rk3399_msch_timings noc_timings; +}; + +struct rk3399_base_params { + unsigned int ddr_freq; + unsigned int dramtype; + unsigned int num_channels; + unsigned int stride; + unsigned int odt; +}; + +struct rk3399_sdram_params { + struct rk3399_sdram_channel ch[2]; + struct rk3399_base_params base; + struct rk3399_ddr_pctl_regs pctl_regs; + struct rk3399_ddr_pi_regs pi_regs; + struct rk3399_ddr_publ_regs phy_regs; +}; + +#define PI_CA_TRAINING (1 << 0) +#define PI_WRITE_LEVELING (1 << 1) +#define PI_READ_GATE_TRAINING (1 << 2) +#define PI_READ_LEVELING (1 << 3) +#define PI_WDQ_LEVELING (1 << 4) +#define PI_FULL_TRAINING 0xff + +#endif diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 8c54fcedf4..7b11895481 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -8,13 +8,6 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H -#ifndef CONFIG_CLK_ZYNQMP -/* Setup clk for network */ -static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) -{ -} -#endif - int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index e9b4cdbbcd..a34990368e 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -53,6 +53,7 @@ #define PTE_TYPE_FAULT (0 << 0) #define PTE_TYPE_TABLE (3 << 0) #define PTE_TYPE_BLOCK (1 << 0) +#define PTE_TYPE_VALID (1 << 0) #define PTE_TABLE_PXN (1UL << 59) #define PTE_TABLE_XN (1UL << 60) @@ -77,6 +78,10 @@ */ #define PMD_ATTRINDX(t) ((t) << 2) #define PMD_ATTRINDX_MASK (7 << 2) +#define PMD_ATTRMASK (PTE_BLOCK_PXN | \ + PTE_BLOCK_UXN | \ + PMD_ATTRINDX_MASK | \ + PTE_TYPE_VALID) /* * TCR flags. diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index c56daf2a1f..b146918586 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -57,17 +57,17 @@ #define PLD(code...) #endif +/* + * We only support cores that support at least Thumb-1 and thus we use + * 'bx lr' + */ .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo .macro ret\c, reg -#if defined(__ARM_ARCH_5E__) - mov\c pc, \reg -#else .ifeqs "\reg", "lr" bx\c \reg .else mov\c pc, \reg .endif -#endif .endm .endr @@ -77,7 +77,7 @@ * We disable it especially for Thumb builds since those instructions * are not made in a Thumb ready way... */ -#ifdef CONFIG_SYS_THUMB_BUILD +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) #define CALGN(code...) #else #define CALGN(code...) code diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 5400cbe18f..fac65d8d7c 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -16,7 +16,7 @@ /* * Invalidate L2 Cache using co-proc instruction */ -#ifdef CONFIG_SYS_THUMB_BUILD +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) void invalidate_l2_cache(void); #else static inline void invalidate_l2_cache(void) diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index ccb513fba2..fd627c0874 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -86,8 +86,8 @@ /* For SD boot address and size are assigned in terms of sector * offset and no. of sectors respectively. */ -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000800 -#define CONFIG_BS_ADDR_DEVICE 0x00000840 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900 +#define CONFIG_BS_ADDR_DEVICE 0x00000940 #define CONFIG_BS_HDR_SIZE 0x00000010 #define CONFIG_BS_SIZE 0x00000008 #else diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index aee87cdcbf..dfcbcceba3 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -59,6 +59,13 @@ struct arch_global_data { phys_addr_t secure_ram; unsigned long tlb_allocated; #endif +#ifdef CONFIG_RESV_RAM + /* + * Reserved RAM for memory resident, eg. Management Complex (MC) + * driver which continues to run after U-Boot exits. + */ + phys_addr_t resv_ram; +#endif #ifdef CONFIG_ARCH_OMAP2 u32 omap_boot_device; diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h index df9934b267..c3399a7e15 100644 --- a/arch/arm/include/asm/setjmp.h +++ b/arch/arm/include/asm/setjmp.h @@ -39,7 +39,7 @@ static inline int setjmp(jmp_buf jmp) "x30", "cc", "memory"); #else asm volatile( -#ifdef CONFIG_SYS_THUMB_BUILD +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) ".align 2\n" "adr r0, jmp_target\n" "add r0, r0, $1\n" diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 766e929d46..9c3261c884 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -226,6 +226,7 @@ void protect_secure_region(void); void smp_kick_all_cpus(void); void flush_l3_cache(void); +void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); /* *Issue a secure monitor call in accordance with ARM "SMC Calling convention", diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 166fa9e3da..b95e10599b 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -71,7 +71,7 @@ asflags-y += -DCONFIG_ARM_ASM_UNIFIED # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_SYS_THUMB_BUILD +ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL ifndef CONFIG_HAS_THUMB2 diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 4f72f8914c..7683386ad9 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -107,7 +107,7 @@ phys_addr_t noncached_alloc(size_t size, size_t align) } #endif /* CONFIG_SYS_NONCACHED_MEMORY */ -#if defined(CONFIG_SYS_THUMB_BUILD) +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) void invalidate_l2_cache(void) { unsigned int val = 0; diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 8415f77e1b..fa81317717 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -71,18 +71,12 @@ ENTRY(_main) */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) - ldr sp, =(CONFIG_SPL_STACK) + ldr r0, =(CONFIG_SPL_STACK) #else - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) #endif -#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */ - mov r3, sp - bic r3, r3, #7 - mov sp, r3 -#else - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ -#endif - mov r0, sp + bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ + mov sp, r0 bl board_init_f_alloc_reserve mov sp, r0 /* set up gd here, outside any C code */ @@ -100,14 +94,9 @@ ENTRY(_main) * 'here' but relocated. */ - ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ -#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */ - mov r3, sp - bic r3, r3, #7 - mov sp, r3 -#else - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ -#endif + ldr r0, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ + bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ + mov sp, r0 ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ sub r9, r9, #GD_SIZE /* new GD is below bd */ @@ -167,7 +156,7 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ mov r0, r9 /* gd_t */ ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */ /* call board_init_r */ -#if defined(CONFIG_SYS_THUMB_BUILD) +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) ldr lr, =board_init_r /* this is auto-relocated! */ bx lr #else diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S index 76968cee17..6e29cbf2ab 100644 --- a/arch/arm/lib/lib1funcs.S +++ b/arch/arm/lib/lib1funcs.S @@ -368,7 +368,7 @@ ENDPROC(Ldiv0) .popsection /* Thumb-1 specialities */ -#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2) +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2) .pushsection .text.__gnu_thumb1_case_sqi, "ax" ENTRY(__gnu_thumb1_case_sqi) push {r1} diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index 00602e9cf8..588b3f8971 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -56,7 +56,7 @@ /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ .syntax unified -#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD) +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD) .thumb .thumb_func #endif diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index df053a31d5..cc4cc44cbb 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -16,7 +16,7 @@ .align 5 .syntax unified -#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD) +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD) .thumb .thumb_func #endif diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index d36e15a51c..624ccd7c2f 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -27,3 +27,11 @@ obj-y += timer.o ifndef CONFIG_SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o endif + +ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +CFLAGS_cache.o := -marm + +endif +endif diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 446457fd81..b786df0aaf 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -24,7 +24,6 @@ #endif /* CONFIG_KW88F6281 */ #include <asm/arch/soc.h> -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index 926d347110..ab704d9afc 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -139,7 +139,6 @@ struct kwgpio_registers { /* * functions */ -unsigned char get_random_hex(void); unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 33dcad40f2..5249aa8844 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -19,7 +19,7 @@ endif # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_SYS_THUMB_BUILD +ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cpu.o := -marm diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 5c4a4c2291..bf8e6be410 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -11,6 +11,21 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3188 + bool "Support Rockchip RK3188" + select CPU_V7 + select SUPPORT_SPL + select SUPPORT_TPL + select SPL + select TPL + select ROCKCHIP_BROM_HELPER + help + The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 + including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two + video interfaces, several memory options and video codec support. + Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, + UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7 @@ -23,9 +38,22 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3328 + bool "Support Rockchip RK3328" + select ARM64 + help + The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. + including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two + video interfaces supporting HDMI and eDP, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. + config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" select ARM64 + select SUPPORT_SPL + select SPL + select SPL_SEPARATE_BSS help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. @@ -37,15 +65,21 @@ config ROCKCHIP_RK3399 config ROCKCHIP_SPL_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 + select ROCKCHIP_BROM_HELPER help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, SPL will return to the boot rom, which will then load the U-Boot binary to keep going on. +config ROCKCHIP_BROM_HELPER + bool + config SPL_MMC_SUPPORT default y if !ROCKCHIP_SPL_BACK_TO_BROM source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" +source "arch/arm/mach-rockchip/rk3328/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 6e79fed485..6b251c7e7e 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -4,11 +4,17 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_TPL_BUILD +obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o +obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o +else ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o -obj-$(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) += save_boot_param.o +obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o +obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o else +obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o endif @@ -16,5 +22,11 @@ ifndef CONFIG_ARM64 obj-y += rk_timer.o endif obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ + +ifndef CONFIG_TPL_BUILD +obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ +endif + obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 801548109b..0522d65467 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -7,6 +7,7 @@ #include <common.h> #include <debug_uart.h> #include <asm/io.h> +#include <asm/arch/bootrom.h> #include <asm/arch/grf_rk3036.h> #include <asm/arch/hardware.h> #include <asm/arch/sdram_rk3036.h> @@ -20,8 +21,6 @@ static struct rk3036_grf * const grf = (void *)GRF_BASE; #define DEBUG_UART_BASE 0x20068000 -extern void back_to_bootrom(void); - void board_init_f(ulong dummy) { #ifdef EARLY_DEBUG diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c new file mode 100644 index 0000000000..f93feae0c9 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <fdtdec.h> +#include <led.h> +#include <malloc.h> +#include <ram.h> +#include <spl.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/bootrom.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <asm/arch/pmu_rk3188.h> +#include <asm/arch/sdram.h> +#include <asm/arch/timer.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <dm/test.h> +#include <dm/util.h> +#include <power/regulator.h> +#include <syscon.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + const void *blob = gd->fdt_blob; + struct udevice *dev; + const char *bootdev; + int node; + int ret; + + bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); + debug("Boot device %s\n", bootdev); + if (!bootdev) + goto fallback; + + node = fdt_path_offset(blob, bootdev); + if (node < 0) { + debug("node=%d\n", node); + goto fallback; + } + ret = device_get_global_by_of_offset(node, &dev); + if (ret) { + debug("device at node %s/%d not found: %d\n", bootdev, node, + ret); + goto fallback; + } + debug("Found device %s\n", dev->name); + switch (device_get_uclass_id(dev)) { + case UCLASS_SPI_FLASH: + return BOOT_DEVICE_SPI; + case UCLASS_MMC: + return BOOT_DEVICE_MMC1; + default: + debug("Booting from device uclass '%s' not supported\n", + dev_get_uclass_name(dev)); + } + +fallback: +#endif + return BOOT_DEVICE_MMC1; +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +void board_init_f(ulong dummy) +{ + struct udevice *pinctrl, *dev; + struct rk3188_pmu *pmu; + int ret; + + /* Example code showing how to enable the debug UART on RK3188 */ +#ifdef EARLY_UART +#include <asm/arch/grf_rk3188.h> + /* Enable early UART on the RK3188 */ +#define GRF_BASE 0x20008000 + struct rk3188_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK << GPIO1B1_SHIFT | + GPIO1B0_MASK << GPIO1B0_SHIFT, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printch('s'); + printch('p'); + printch('l'); + printch('\n'); +#endif + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + rockchip_timer_init(); + + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return; + } + + /* + * Recover the bootrom's stackpointer. + * For whatever reason needs to run after rockchip_get_clk. + */ + pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + if (IS_ERR(pmu)) + error("pmu syscon returned %ld\n", PTR_ERR(pmu)); + SAVE_SP_ADDR = readl(&pmu->sys_reg[2]); + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("Pinctrl init failed: %d\n", ret); + return; + } + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } + +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) + back_to_bootrom(); +#endif +} + +static int setup_led(void) +{ +#ifdef CONFIG_SPL_LED + struct udevice *dev; + char *led_name; + int ret; + + led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); + if (!led_name) + return 0; + ret = led_get_by_label(led_name, &dev); + if (ret) { + debug("%s: get=%d\n", __func__, ret); + return ret; + } + ret = led_set_on(dev, 1); + if (ret) + return ret; +#endif + + return 0; +} + +void spl_board_init(void) +{ + struct udevice *pinctrl; + int ret; + + ret = setup_led(); + if (ret) { + debug("LED ret=%d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + +#ifdef CONFIG_SPL_MMC_SUPPORT + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); + if (ret) { + debug("%s: Failed to set up SD card\n", __func__); + goto err; + } +#endif + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + goto err; + } + + preloader_console_init(); +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM + back_to_bootrom(); +#endif + return; + +err: + printf("spl_board_init: Error %d\n", ret); + + /* No way to report error here */ + hang(); +} diff --git a/arch/arm/mach-rockchip/rk3188-board-tpl.c b/arch/arm/mach-rockchip/rk3188-board-tpl.c new file mode 100644 index 0000000000..442bfe7aa7 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188-board-tpl.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/bootrom.h> +#include <asm/arch/pmu_rk3188.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* track how often we were entered */ +static int rk3188_num_entries __attribute__ ((section(".data"))); + +#define PMU_BASE 0x20004000 +#define TPL_ENTRY 0x10080C00 + +static void jump_to_spl(void) +{ + typedef void __noreturn (*image_entry_noargs_t)(void); + + struct rk3188_pmu * const pmu = (void *)PMU_BASE; + image_entry_noargs_t tpl_entry = + (image_entry_noargs_t)(unsigned long)TPL_ENTRY; + + /* Store the SAVE_SP_ADDR in a location shared with TPL. */ + writel(SAVE_SP_ADDR, &pmu->sys_reg[2]); + tpl_entry(); +} + +void board_init_f(ulong dummy) +{ + /* Example code showing how to enable the debug UART on RK3188 */ +#ifdef EARLY_UART +#include <asm/arch/grf_rk3188.h> + /* Enable early UART on the RK3188 */ +#define GRF_BASE 0x20008000 + struct rk3188_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK << GPIO1B1_SHIFT | + GPIO1B0_MASK << GPIO1B0_SHIFT, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + + printch('t'); + printch('p'); + printch('l'); + printch('-'); + printch(rk3188_num_entries + 1 + '0'); + printch('\n'); +#endif + + rk3188_num_entries++; + + if (rk3188_num_entries == 1) { + /* + * The original loader did some very basic integrity + * checking at this point, but the remaining few bytes + * could be used for any improvement making sense + * really early on. + */ + + back_to_bootrom(); + } else { + /* + * TPL part of the loader should now wait for us + * at offset 0xC00 in the sram. Should never return + * from there. + */ + jump_to_spl(); + } +} diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c new file mode 100644 index 0000000000..16f38559af --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <ram.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <asm/arch/pmu_rk3288.h> +#include <asm/arch/boot_mode.h> +#include <asm/gpio.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) + struct udevice *pinctrl; + int ret; + + /* + * We need to implement sdcard iomux here for the further + * initialization, otherwise, it'll hit sdcard command sending + * timeout exception. + */ + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); + if (ret) { + debug("%s: Failed to set up SD card\n", __func__); + goto err; + } + + return 0; +err: + printf("board_init: Error %d\n", ret); + + /* No way to report error here */ + hang(); + + return -1; +#else + return 0; +#endif +} + +int dram_init(void) +{ + /* FIXME: read back ram size from sys_reg2 */ + gd->ram_size = 0x40000000; + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig new file mode 100644 index 0000000000..f8e1d0316b --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -0,0 +1,24 @@ +if ROCKCHIP_RK3188 + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + +config TPL_LIBCOMMON_SUPPORT + default y + +config TPL_SERIAL_SUPPORT + default y + +endif diff --git a/arch/arm/mach-rockchip/rk3188/Makefile b/arch/arm/mach-rockchip/rk3188/Makefile new file mode 100644 index 0000000000..2dc9511de7 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (c) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_TPL_BUILD +obj-y += clk_rk3188.o +obj-y += sdram_rk3188.o +obj-y += syscon_rk3188.o +endif diff --git a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c new file mode 100644 index 0000000000..1ec9e1cb75 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3188.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3188_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3188_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c new file mode 100644 index 0000000000..461cfcdc83 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c @@ -0,0 +1,995 @@ +/* + * (C) Copyright 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + * Adapted from the very similar rk3288 ddr init. + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-structs.h> +#include <errno.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3188.h> +#include <asm/arch/ddr_rk3188.h> +#include <asm/arch/grf_rk3188.h> +#include <asm/arch/pmu_rk3188.h> +#include <asm/arch/sdram.h> +#include <linux/err.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct chan_info { + struct rk3288_ddr_pctl *pctl; + struct rk3288_ddr_publ *publ; + struct rk3188_msch *msch; +}; + +struct dram_info { + struct chan_info chan[1]; + struct ram_info info; + struct clk ddr_clk; + struct rk3188_cru *cru; + struct rk3188_grf *grf; + struct rk3188_sgrf *sgrf; + struct rk3188_pmu *pmu; +}; + +struct rk3188_sdram_params { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3188_dmc of_plat; +#endif + struct rk3288_sdram_channel ch[2]; + struct rk3288_sdram_pctl_timing pctl_timing; + struct rk3288_sdram_phy_timing phy_timing; + struct rk3288_base_params base; + int num_channels; + struct regmap *map; +}; + +const int ddrconf_table[] = { + /* + * [5:4] row(13+n) + * [1:0] col(9+n), assume bw=2 + * row col,bw + */ + 0, + ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#define TEST_PATTEN 0x5aa5f00f +#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) +#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) + +#ifdef CONFIG_SPL_BUILD +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) +{ + u32 phy_ctl_srstn_shift = 13; + u32 ctl_psrstn_shift = 11; + u32 ctl_srstn_shift = 10; + u32 phy_psrstn_shift = 9; + u32 phy_srstn_shift = 8; + + rk_clrsetreg(&cru->cru_softrst_con[5], + 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | + 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | + 1 << phy_srstn_shift, + phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | + ctl << ctl_srstn_shift | phy << phy_psrstn_shift | + phy << phy_srstn_shift); +} + +static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n) +{ + u32 phy_ctl_srstn_shift = 13; + + rk_clrsetreg(&cru->cru_softrst_con[5], + 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); +} + +static void phy_pctrl_reset(struct rk3188_cru *cru, + struct rk3288_ddr_publ *publ, + int channel) +{ + int i; + + ddr_reset(cru, channel, 1, 1); + udelay(1); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + ddr_reset(cru, channel, 1, 0); + udelay(10); + ddr_reset(cru, channel, 0, 0); + udelay(10); +} + +static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, + u32 freq) +{ + int i; + + if (freq <= 250000000) { + if (freq <= 150000000) + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + else + setbits_le32(&publ->dllgcr, SBIAS_BYPASS); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + + setbits_le32(&publ->pir, PIR_DLLBYP); + } else { + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) { + clrbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + } + + clrbits_le32(&publ->pir, PIR_DLLBYP); + } +} + +static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) +{ + writel(DFI_INIT_START, &pctl->dfistcfg0); + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, + &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, + &pctl->dfilpcfg0); + + writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); + writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); + writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); + writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); + writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); + writel(1, &pctl->dfitphyupdtype0); + + /* cs0 and cs1 write odt enable */ + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), + &pctl->dfiodtcfg); + /* odt write length */ + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); + /* phyupd and ctrlupd disabled */ + writel(0, &pctl->dfiupdcfg); +} + +static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable) +{ + uint val = 0; + + if (enable) + val = 1 << DDR_16BIT_EN_SHIFT; + + rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val); +} + +static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel, + bool ddr3_mode) +{ + uint mask, val; + + mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT; + val = ddr3_mode << MSCH4_MAINDDR3_SHIFT; + rk_clrsetreg(&grf->soc_con2, mask, val); +} + +static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable) +{ + uint mask, val; + + mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT; + val = enable << RANK_TO_ROW15_EN_SHIFT; + rk_clrsetreg(&grf->soc_con2, mask, val); +} + +static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, + struct rk3188_sdram_params *sdram_params, + struct rk3188_grf *grf) +{ + copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, + sizeof(sdram_params->pctl_timing)); + switch (sdram_params->base.dramtype) { + case DDR3: + if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { + writel(sdram_params->pctl_timing.tcl - 3, + &pctl->dfitrddataen); + } else { + writel(sdram_params->pctl_timing.tcl - 2, + &pctl->dfitrddataen); + } + writel(sdram_params->pctl_timing.tcwl - 1, + &pctl->dfitphywrlat); + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | + DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, + &pctl->mcfg); + ddr_set_ddr3_mode(grf, channel, true); + ddr_set_enable(grf, channel, true); + break; + } + + setbits_le32(&pctl->scfg, 1); +} + +static void phy_cfg(const struct chan_info *chan, int channel, + struct rk3188_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3188_msch *msch = chan->msch; + uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; + u32 dinit2; + int i; + + dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); + /* DDR PHY Timing */ + copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, + sizeof(sdram_params->phy_timing)); + writel(sdram_params->base.noc_timing, &msch->ddrtiming); + writel(0x3f, &msch->readlatency); + writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | + 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); + writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, + &publ->ptr[1]); + writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, + &publ->ptr[2]); + + switch (sdram_params->base.dramtype) { + case DDR3: + clrbits_le32(&publ->pgcr, 0x1f); + clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, + DDRMD_DDR3 << DDRMD_SHIFT); + break; + } + if (sdram_params->base.odt) { + /*dynamic RTT enable */ + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } else { + /*dynamic RTT disable */ + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } +} + +static void phy_init(struct rk3288_ddr_publ *publ) +{ + setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST + | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); + udelay(1); + while ((readl(&publ->pgsr) & + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) + ; +} + +static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, + u32 cmd, u32 arg) +{ + writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); + udelay(1); + while (readl(&pctl->mcmd) & START_CMD) + ; +} + +static inline void send_command_op(struct rk3288_ddr_pctl *pctl, + u32 rank, u32 cmd, u32 ma, u32 op) +{ + send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | + (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); +} + +static void memory_init(struct rk3288_ddr_publ *publ, + u32 dramtype) +{ + setbits_le32(&publ->pir, + (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP + | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC + | (dramtype == DDR3 ? PIR_DRAMRST : 0))); + udelay(1); + while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) + != (PGSR_IDONE | PGSR_DLDONE)) + ; +} + +static void move_to_config_state(struct rk3288_ddr_publ *publ, + struct rk3288_ddr_pctl *pctl) +{ + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) + != ACCESS) + ; + /* wait DLL lock */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + /* + * if at low power state,need wakeup first, + * and then enter the config, so + * fallthrough + */ + case ACCESS: + /* fallthrough */ + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + break; + case CONFIG: + return; + default: + break; + } + } +} + +static void set_bandwidth_ratio(const struct chan_info *chan, int channel, + u32 n, struct rk3188_grf *grf) +{ + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3188_msch *msch = chan->msch; + + if (n == 1) { + setbits_le32(&pctl->ppcfg, 1); + ddr_set_enable(grf, channel, 1); + setbits_le32(&msch->ddrtiming, 1 << 31); + /* Data Byte disable*/ + clrbits_le32(&publ->datx8[2].dxgcr, 1); + clrbits_le32(&publ->datx8[3].dxgcr, 1); + /* disable DLL */ + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + } else { + clrbits_le32(&pctl->ppcfg, 1); + ddr_set_enable(grf, channel, 0); + clrbits_le32(&msch->ddrtiming, 1 << 31); + /* Data Byte enable*/ + setbits_le32(&publ->datx8[2].dxgcr, 1); + setbits_le32(&publ->datx8[3].dxgcr, 1); + + /* enable DLL */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + /* reset DLL */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + udelay(10); + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + } + setbits_le32(&pctl->dfistcfg0, 1 << 2); +} + +static int data_training(const struct chan_info *chan, int channel, + struct rk3188_sdram_params *sdram_params) +{ + unsigned int j; + int ret = 0; + u32 rank; + int i; + u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + + /* disable auto refresh */ + writel(0, &pctl->trefi); + + if (sdram_params->base.dramtype != LPDDR3) + setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + rank = sdram_params->ch[channel].rank | 1; + for (j = 0; j < ARRAY_SIZE(step); j++) { + /* + * trigger QSTRN and RVTRN + * clear DTDONE status + */ + setbits_le32(&publ->pir, PIR_CLRSR); + + /* trigger DTT */ + setbits_le32(&publ->pir, + PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | + PIR_CLRSR); + udelay(1); + /* wait echo byte DTDONE */ + while ((readl(&publ->datx8[0].dxgsr[0]) & rank) + != rank) + ; + while ((readl(&publ->datx8[1].dxgsr[0]) & rank) + != rank) + ; + if (!(readl(&pctl->ppcfg) & 1)) { + while ((readl(&publ->datx8[2].dxgsr[0]) + & rank) != rank) + ; + while ((readl(&publ->datx8[3].dxgsr[0]) + & rank) != rank) + ; + } + if (readl(&publ->pgsr) & + (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { + ret = -1; + break; + } + } + /* send some auto refresh to complement the lost while DTT */ + for (i = 0; i < (rank > 1 ? 8 : 4); i++) + send_command(pctl, rank, REF_CMD, 0); + + if (sdram_params->base.dramtype != LPDDR3) + clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + + /* resume auto refresh */ + writel(sdram_params->pctl_timing.trefi, &pctl->trefi); + + return ret; +} + +static void move_to_access_state(const struct chan_info *chan) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & + LP_TRIG_MASK) == 1) + return; + + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) + ; + /* wait DLL lock */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + break; + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + /* fallthrough */ + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) + ; + break; + case ACCESS: + return; + default: + break; + } + } +} + +static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum, + struct rk3188_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + + if (sdram_params->ch[chnum].bk == 3) + clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, + 1 << PDQ_SHIFT); + else + clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); + + writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); +} + +static void dram_all_config(const struct dram_info *dram, + struct rk3188_sdram_params *sdram_params) +{ + unsigned int chan; + u32 sys_reg = 0; + + sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; + for (chan = 0; chan < sdram_params->num_channels; chan++) { + const struct rk3288_sdram_channel *info = + &sdram_params->ch[chan]; + + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); + + dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); + } + if (sdram_params->ch[0].rank == 2) + ddr_rank_2_row15en(dram->grf, 0); + else + ddr_rank_2_row15en(dram->grf, 1); + + writel(sys_reg, &dram->pmu->sys_reg[2]); +} + +static int sdram_rank_bw_detect(struct dram_info *dram, int channel, + struct rk3188_sdram_params *sdram_params) +{ + int reg; + int need_trainig = 0; + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_publ *publ = chan->publ; + + ddr_rank_2_row15en(dram->grf, 0); + + if (data_training(chan, channel, sdram_params) < 0) { + printf("first data training fail!\n"); + reg = readl(&publ->datx8[0].dxgsr[0]); + /* Check the result for rank 0 */ + if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { + printf("data training fail!\n"); + return -EIO; + } + + /* Check the result for rank 1 */ + if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { + sdram_params->ch[channel].rank = 1; + clrsetbits_le32(&publ->pgcr, 0xF << 18, + sdram_params->ch[channel].rank << 18); + need_trainig = 1; + } + reg = readl(&publ->datx8[2].dxgsr[0]); + if (reg & (1 << 4)) { + sdram_params->ch[channel].bw = 1; + set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, + dram->grf); + need_trainig = 1; + } + } + /* Assume the Die bit width are the same with the chip bit width */ + sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; + + if (need_trainig && + (data_training(chan, channel, sdram_params) < 0)) { + if (sdram_params->base.dramtype == LPDDR3) { + ddr_phy_ctl_reset(dram->cru, channel, 1); + udelay(10); + ddr_phy_ctl_reset(dram->cru, channel, 0); + udelay(10); + } + printf("2nd data training failed!"); + return -EIO; + } + + return 0; +} + +/* + * Detect ram columns and rows. + * @dram: dram info struct + * @channel: channel number to handle + * @sdram_params: sdram parameters, function will fill in col and row values + * + * Returns 0 or negative on error. + */ +static int sdram_col_row_detect(struct dram_info *dram, int channel, + struct rk3188_sdram_params *sdram_params) +{ + int row, col; + unsigned int addr; + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + int ret = 0; + + /* Detect col */ + for (col = 11; col >= 9; col--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + + (1 << (col + sdram_params->ch[channel].bw - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (col == 8) { + printf("Col detect error\n"); + ret = -EINVAL; + goto out; + } else { + sdram_params->ch[channel].col = col; + } + + ddr_rank_2_row15en(dram->grf, 1); + move_to_config_state(publ, pctl); + writel(1, &chan->msch->ddrconf); + move_to_access_state(chan); + /* Detect row, max 15,min13 in rk3188*/ + for (row = 16; row >= 13; row--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (row == 12) { + printf("Row detect error\n"); + ret = -EINVAL; + } else { + sdram_params->ch[channel].cs1_row = row; + sdram_params->ch[channel].row_3_4 = 0; + debug("chn %d col %d, row %d\n", channel, col, row); + sdram_params->ch[channel].cs0_row = row; + } + +out: + return ret; +} + +static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params) +{ + int i, tmp, size, ret = 0; + + tmp = sdram_params->ch[0].col - 9; + tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; + tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4); + size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]); + for (i = 0; i < size; i++) + if (tmp == ddrconf_table[i]) + break; + if (i >= size) { + printf("niu config not found\n"); + ret = -EINVAL; + } else { + debug("niu config %d\n", i); + sdram_params->base.ddrconfig = i; + } + + return ret; +} + +static int sdram_init(struct dram_info *dram, + struct rk3188_sdram_params *sdram_params) +{ + int channel; + int zqcr; + int ret; + + if ((sdram_params->base.dramtype == DDR3 && + sdram_params->base.ddr_freq > 800000000)) { + printf("SDRAM frequency is too high!"); + return -E2BIG; + } + + ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); + if (ret) { + printf("Could not set DDR clock\n"); + return ret; + } + + for (channel = 0; channel < 1; channel++) { + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + + phy_pctrl_reset(dram->cru, publ, channel); + phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); + + dfi_cfg(pctl, sdram_params->base.dramtype); + + pctl_cfg(channel, pctl, sdram_params, dram->grf); + + phy_cfg(chan, channel, sdram_params); + + phy_init(publ); + + writel(POWER_UP_START, &pctl->powctl); + while (!(readl(&pctl->powstat) & POWER_UP_DONE)) + ; + + memory_init(publ, sdram_params->base.dramtype); + move_to_config_state(publ, pctl); + + /* Using 32bit bus width for detect */ + sdram_params->ch[channel].bw = 2; + set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, dram->grf); + /* + * set cs, using n=3 for detect + * CS0, n=1 + * CS1, n=2 + * CS0 & CS1, n = 3 + */ + sdram_params->ch[channel].rank = 2, + clrsetbits_le32(&publ->pgcr, 0xF << 18, + (sdram_params->ch[channel].rank | 1) << 18); + + /* DS=40ohm,ODT=155ohm */ + zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | + 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | + 0x19 << PD_OUTPUT_SHIFT; + writel(zqcr, &publ->zq1cr[0]); + writel(zqcr, &publ->zq0cr[0]); + + /* Detect the rank and bit-width with data-training */ + writel(1, &chan->msch->ddrconf); + sdram_rank_bw_detect(dram, channel, sdram_params); + + if (sdram_params->base.dramtype == LPDDR3) { + u32 i; + writel(0, &pctl->mrrcfg0); + for (i = 0; i < 17; i++) + send_command_op(pctl, 1, MRR_CMD, i, 0); + } + writel(4, &chan->msch->ddrconf); + move_to_access_state(chan); + /* DDR3 and LPDDR3 are always 8 bank, no need detect */ + sdram_params->ch[channel].bk = 3; + /* Detect Col and Row number*/ + ret = sdram_col_row_detect(dram, channel, sdram_params); + if (ret) + goto error; + } + /* Find NIU DDR configuration */ + ret = sdram_get_niu_config(sdram_params); + if (ret) + goto error; + + dram_all_config(dram, sdram_params); + debug("%s done\n", __func__); + + return 0; +error: + printf("DRAM init failed!\n"); + hang(); +} +#endif /* CONFIG_SPL_BUILD */ + +size_t sdram_size_mb(struct rk3188_pmu *pmu) +{ + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; + size_t chipsize_mb = 0; + size_t size_mb = 0; + u32 ch; + u32 sys_reg = readl(&pmu->sys_reg[2]); + u32 chans; + + chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); + + for (ch = 0; ch < chans; ch++) { + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & + SYS_REG_RANK_MASK); + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK); + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK); + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & + SYS_REG_ROW_3_4_MASK; + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + + if (rank > 1) + chipsize_mb += chipsize_mb >> + (cs0_row - cs1_row); + if (row_3_4) + chipsize_mb = chipsize_mb * 3 / 4; + size_mb += chipsize_mb; + } + + /* there can be no more than 2gb of memory */ + size_mb = min(size_mb, 0x80000000 >> 20); + + return size_mb; +} + +#ifdef CONFIG_SPL_BUILD +static int setup_sdram(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3188_sdram_params *params = dev_get_platdata(dev); + + return sdram_init(priv, params); +} + +static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3188_sdram_params *params = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + int ret; + + /* rk3188 supports only one-channel */ + params->num_channels = 1; + ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", + (u32 *)¶ms->pctl_timing, + sizeof(params->pctl_timing) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,pctl-timing\n", __func__); + return -EINVAL; + } + ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing", + (u32 *)¶ms->phy_timing, + sizeof(params->phy_timing) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,phy-timing\n", __func__); + return -EINVAL; + } + ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", + (u32 *)¶ms->base, + sizeof(params->base) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,sdram-params\n", __func__); + return -EINVAL; + } + ret = regmap_init_mem(dev, ¶ms->map); + if (ret) + return ret; +#endif + + return 0; +} +#endif /* CONFIG_SPL_BUILD */ + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_platdata(struct udevice *dev) +{ + struct rk3188_sdram_params *plat = dev_get_platdata(dev); + struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat; + int ret; + + memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, + sizeof(plat->pctl_timing)); + memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, + sizeof(plat->phy_timing)); + memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); + /* rk3188 supports dual-channel, set default channel num to 2 */ + plat->num_channels = 1; + ret = regmap_init_mem_platdata(dev, of_plat->reg, + ARRAY_SIZE(of_plat->reg) / 2, + &plat->map); + if (ret) + return ret; + + return 0; +} +#endif + +static int rk3188_dmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_SPL_BUILD + struct rk3188_sdram_params *plat = dev_get_platdata(dev); +#endif + struct dram_info *priv = dev_get_priv(dev); + struct regmap *map; + int ret; + struct udevice *dev_clk; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_platdata(dev); + if (ret) + return ret; +#endif + map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); + if (IS_ERR(map)) + return PTR_ERR(map); + priv->chan[0].msch = regmap_get_range(map, 0); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + +#ifdef CONFIG_SPL_BUILD + priv->chan[0].pctl = regmap_get_range(plat->map, 0); + priv->chan[0].publ = regmap_get_range(plat->map, 1); +#endif + + ret = rockchip_get_clk(&dev_clk); + if (ret) + return ret; + priv->ddr_clk.id = CLK_DDR; + ret = clk_request(dev_clk, &priv->ddr_clk); + if (ret) + return ret; + + priv->cru = rockchip_get_cru(); + if (IS_ERR(priv->cru)) + return PTR_ERR(priv->cru); +#ifdef CONFIG_SPL_BUILD + ret = setup_sdram(dev); + if (ret) + return ret; +#endif + priv->info.base = 0; + priv->info.size = sdram_size_mb(priv->pmu) << 20; + + return 0; +} + +static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3188_dmc_ops = { + .get_info = rk3188_dmc_get_info, +}; + +static const struct udevice_id rk3188_dmc_ids[] = { + { .compatible = "rockchip,rk3188-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3188) = { + .name = "rockchip_rk3188_dmc", + .id = UCLASS_RAM, + .of_match = rk3188_dmc_ids, + .ops = &rk3188_dmc_ops, +#ifdef CONFIG_SPL_BUILD + .ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata, +#endif + .probe = rk3188_dmc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), +#ifdef CONFIG_SPL_BUILD + .platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params), +#endif +}; diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c new file mode 100644 index 0000000000..aeee6bfcad --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3188_syscon_ids[] = { + { .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC }, + { .compatible = "rockchip,rk3188-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3188-pmu", .data = ROCKCHIP_SYSCON_PMU }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3188) = { + .name = "rk3188_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3188_syscon_ids, +}; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rk3188_syscon_bind_of_platdata(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rk3188_noc) = { + .name = "rockchip_rk3188_noc", + .id = UCLASS_SYSCON, + .of_match = rk3188_syscon_ids, + .bind = rk3188_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3188_grf) = { + .name = "rockchip_rk3188_grf", + .id = UCLASS_SYSCON, + .of_match = rk3188_syscon_ids + 1, + .bind = rk3188_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3188_pmu) = { + .name = "rockchip_rk3188_pmu", + .id = UCLASS_SYSCON, + .of_match = rk3188_syscon_ids + 2, + .bind = rk3188_syscon_bind_of_platdata, +}; +#endif diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 930939ad24..74f3379194 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -14,6 +14,7 @@ #include <spl.h> #include <asm/gpio.h> #include <asm/io.h> +#include <asm/arch/bootrom.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> #include <asm/arch/periph.h> @@ -155,7 +156,7 @@ static int configure_emmc(struct udevice *pinctrl) return 0; } #endif -extern void back_to_bootrom(void); + void board_init_f(ulong dummy) { struct udevice *pinctrl; @@ -184,9 +185,9 @@ void board_init_f(ulong dummy) debug_uart_init(); #endif - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index 89fd8e6bff..8549b28243 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -57,6 +57,26 @@ struct rk3288_sdram_params { struct regmap *map; }; +const int ddrconf_table[] = { + /* row col,bw */ + 0, + ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((3 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((4 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((3 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + ((3 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + 0, + 0, + 0, + 0, + ((4 << 4) | 2), +}; + #define TEST_PATTEN 0x5aa5f00f #define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) #define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) @@ -100,7 +120,7 @@ static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n) static void phy_pctrl_reset(struct rk3288_cru *cru, struct rk3288_ddr_publ *publ, - u32 channel) + int channel) { int i; @@ -126,6 +146,7 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, u32 freq) { int i; + if (freq <= 250000000) { if (freq <= 150000000) clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); @@ -217,7 +238,7 @@ static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel, UPCTL0_LPDDR3_ODT_EN_SHIFT)); } -static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl, +static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, struct rk3288_sdram_params *sdram_params, struct rk3288_grf *grf) { @@ -267,7 +288,7 @@ static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl, setbits_le32(&pctl->scfg, 1); } -static void phy_cfg(const struct chan_info *chan, u32 channel, +static void phy_cfg(const struct chan_info *chan, int channel, struct rk3288_sdram_params *sdram_params) { struct rk3288_ddr_publ *publ = chan->publ; @@ -392,7 +413,8 @@ static void move_to_config_state(struct rk3288_ddr_publ *publ, while ((readl(&publ->pgsr) & PGSR_DLDONE) != PGSR_DLDONE) ; - /* if at low power state,need wakeup first, + /* + * if at low power state,need wakeup first, * and then enter the config * so here no break. */ @@ -411,7 +433,7 @@ static void move_to_config_state(struct rk3288_ddr_publ *publ, } } -static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel, +static void set_bandwidth_ratio(const struct chan_info *chan, int channel, u32 n, struct rk3288_grf *grf) { struct rk3288_ddr_pctl *pctl = chan->pctl; @@ -449,7 +471,7 @@ static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel, setbits_le32(&pctl->dfistcfg0, 1 << 2); } -static int data_training(const struct chan_info *chan, u32 channel, +static int data_training(const struct chan_info *chan, int channel, struct rk3288_sdram_params *sdram_params) { unsigned int j; @@ -593,25 +615,6 @@ static void dram_all_config(const struct dram_info *dram, writel(sys_reg, &dram->pmu->sys_reg[2]); rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); } -const int ddrconf_table[] = { - /* row col,bw */ - 0, - ((1 << 4) | 1), - ((2 << 4) | 1), - ((3 << 4) | 1), - ((4 << 4) | 1), - ((1 << 4) | 2), - ((2 << 4) | 2), - ((3 << 4) | 2), - ((1 << 4) | 0), - ((2 << 4) | 0), - ((3 << 4) | 0), - 0, - 0, - 0, - 0, - ((4 << 4) | 2), -}; static int sdram_rank_bw_detect(struct dram_info *dram, int channel, struct rk3288_sdram_params *sdram_params) @@ -621,12 +624,12 @@ static int sdram_rank_bw_detect(struct dram_info *dram, int channel, const struct chan_info *chan = &dram->chan[channel]; struct rk3288_ddr_publ *publ = chan->publ; - if (-1 == data_training(chan, channel, sdram_params)) { + if (data_training(chan, channel, sdram_params) < 0) { reg = readl(&publ->datx8[0].dxgsr[0]); /* Check the result for rank 0 */ if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { debug("data training fail!\n"); - return -EIO; + return -EIO; } else if ((channel == 1) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { sdram_params->num_channels = 1; @@ -652,7 +655,7 @@ static int sdram_rank_bw_detect(struct dram_info *dram, int channel, sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; if (need_trainig && - (-1 == data_training(chan, channel, sdram_params))) { + (data_training(chan, channel, sdram_params) < 0)) { if (sdram_params->base.dramtype == LPDDR3) { ddr_phy_ctl_reset(dram->cru, channel, 1); udelay(10); diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig new file mode 100644 index 0000000000..43afba2430 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -0,0 +1,23 @@ +if ROCKCHIP_RK3328 + +choice + prompt "RK3328 board select" + +config TARGET_EVB_RK3328 + bool "RK3328 evaluation board" + help + RK3328evb is a evaluation board for Rockchip rk3328, + with full function and phisical connectors support like + usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... + +endchoice + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +source "board/rockchip/evb_rk3328/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3328/Makefile b/arch/arm/mach-rockchip/rk3328/Makefile new file mode 100644 index 0000000000..bbab036a12 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clk_rk3328.o +obj-y += rk3328.o +obj-y += syscon_rk3328.o diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c new file mode 100644 index 0000000000..1205516227 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3328.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3328_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3328_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_addr_ptr(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c new file mode 100644 index 0000000000..857f0142b0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> + +static struct mm_region rk3328_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3328_mem_map; + +int arch_cpu_init(void) +{ + /* We do some SoC one time setting here. */ + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c new file mode 100644 index 0000000000..a1a368fcd2 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <dm.h> +#include <syscon.h> + +static const struct udevice_id rk3328_syscon_ids[] = { + { .compatible = "rockchip,rk3328-grf", .data = ROCKCHIP_SYSCON_GRF }, +}; + +U_BOOT_DRIVER(syscon_rk3328) = { + .name = "rk3328_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3328_syscon_ids, +}; diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c new file mode 100644 index 0000000000..8ae305542b --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <fdtdec.h> +#include <led.h> +#include <malloc.h> +#include <ram.h> +#include <spl.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <asm/arch/sdram.h> +#include <asm/arch/timer.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <dm/test.h> +#include <dm/util.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +#define TIMER_CHN10_BASE 0xff8680a0 +#define TIMER_END_COUNT_L 0x00 +#define TIMER_END_COUNT_H 0x04 +#define TIMER_INIT_COUNT_L 0x10 +#define TIMER_INIT_COUNT_H 0x14 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) + +void secure_timer_init(void) +{ + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); + writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); +} + +#define GRF_EMMCCORE_CON11 0xff77f02c +void board_init_f(ulong dummy) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + + /* Example code showing how to enable the debug UART on RK3288 */ +#include <asm/arch/grf_rk3399.h> + /* Enable early UART2 channel C on the RK3399 */ +#define GRF_BASE 0xff770000 + struct rk3399_grf_regs * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C3_SEL_MASK, + GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C4_SEL_MASK, + GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->soc_con7, + GRF_UART_DBG_SEL_MASK, + GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); +#define EARLY_UART +#ifdef EARLY_UART + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("U-Boot SPL board init"); +#endif + /* Emmc clock generator: disable the clock multipilier */ + rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + secure_timer_init(); + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("Pinctrl init failed: %d\n", ret); + return; + } + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +void spl_board_init(void) +{ + struct udevice *pinctrl; + int ret; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + goto err; + } + + preloader_console_init(); +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM + back_to_bootrom(); +#endif + return; +err: + printf("spl_board_init: Error %d\n", ret); + + /* No way to report error here */ + hang(); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3399/Makefile b/arch/arm/mach-rockchip/rk3399/Makefile index 98ebeac340..793ce31c12 100644 --- a/arch/arm/mach-rockchip/rk3399/Makefile +++ b/arch/arm/mach-rockchip/rk3399/Makefile @@ -6,4 +6,5 @@ obj-y += clk_rk3399.o obj-y += rk3399.o +obj-y += sdram_rk3399.o obj-y += syscon_rk3399.o diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index ce706a61e2..cf5b8c9548 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -31,3 +31,24 @@ void *rockchip_get_cru(void) return priv->cru; } + +static int rockchip_get_pmucruclk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp); +} + +void *rockchip_get_pmucru(void) +{ + struct rk3399_pmuclk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_pmucruclk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->pmucru; +} diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 8bb950ebd1..cbfd3fa09a 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -40,5 +40,6 @@ int arch_cpu_init(void) /* Emmc clock generator: disable the clock multipilier */ rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); + printf("time %x, %x\n", readl(0xff8680a8), readl(0xff8680ac)); return 0; } diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file mode 100644 index 0000000000..749b52c8e7 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -0,0 +1,1321 @@ +/* + * (C) Copyright 2016-2017 Rockchip Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + * Adapted from coreboot. + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-structs.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/sdram_rk3399.h> +#include <asm/arch/cru_rk3399.h> +#include <asm/arch/grf_rk3399.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +DECLARE_GLOBAL_DATA_PTR; +struct chan_info { + struct rk3399_ddr_pctl_regs *pctl; + struct rk3399_ddr_pi_regs *pi; + struct rk3399_ddr_publ_regs *publ; + struct rk3399_msch_regs *msch; +}; + +struct dram_info { +#ifdef CONFIG_SPL_BUILD + struct chan_info chan[2]; + struct clk ddr_clk; + struct rk3399_cru *cru; + struct rk3399_pmucru *pmucru; + struct rk3399_pmusgrf_regs *pmusgrf; + struct rk3399_ddr_cic_regs *cic; +#endif + struct ram_info info; + struct rk3399_pmugrf_regs *pmugrf; +}; + +/* + * sys_reg bitfield struct + * [31] row_3_4_ch1 + * [30] row_3_4_ch0 + * [29:28] chinfo + * [27] rank_ch1 + * [26:25] col_ch1 + * [24] bk_ch1 + * [23:22] cs0_row_ch1 + * [21:20] cs1_row_ch1 + * [19:18] bw_ch1 + * [17:16] dbw_ch1; + * [15:13] ddrtype + * [12] channelnum + * [11] rank_ch0 + * [10:9] col_ch0 + * [8] bk_ch0 + * [7:6] cs0_row_ch0 + * [5:4] cs1_row_ch0 + * [3:2] bw_ch0 + * [1:0] dbw_ch0 +*/ +#define SYS_REG_DDRTYPE_SHIFT 13 +#define SYS_REG_DDRTYPE_MASK 7 +#define SYS_REG_NUM_CH_SHIFT 12 +#define SYS_REG_NUM_CH_MASK 1 +#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) +#define SYS_REG_ROW_3_4_MASK 1 +#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) +#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) +#define SYS_REG_RANK_MASK 1 +#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) +#define SYS_REG_COL_MASK 3 +#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) +#define SYS_REG_BK_MASK 1 +#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) +#define SYS_REG_CS0_ROW_MASK 3 +#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) +#define SYS_REG_CS1_ROW_MASK 3 +#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) +#define SYS_REG_BW_MASK 3 +#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) +#define SYS_REG_DBW_MASK 3 + +#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) +#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) +#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) + +#define PHY_DRV_ODT_Hi_Z 0x0 +#define PHY_DRV_ODT_240 0x1 +#define PHY_DRV_ODT_120 0x8 +#define PHY_DRV_ODT_80 0x9 +#define PHY_DRV_ODT_60 0xc +#define PHY_DRV_ODT_48 0xd +#define PHY_DRV_ODT_40 0xe +#define PHY_DRV_ODT_34_3 0xf + +#ifdef CONFIG_SPL_BUILD + +struct rockchip_dmc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3399_dmc dtplat; +#else + struct rk3399_sdram_params sdram_params; +#endif + struct regmap *map; +}; + +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, + u32 freq) +{ + u32 *denali_phy = ddr_publ_regs->denali_phy; + + /* From IP spec, only freq small than 125 can enter dll bypass mode */ + if (freq <= 125) { + /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ + setbits_le32(&denali_phy[86], (0x3 << 2) << 8); + setbits_le32(&denali_phy[214], (0x3 << 2) << 8); + setbits_le32(&denali_phy[342], (0x3 << 2) << 8); + setbits_le32(&denali_phy[470], (0x3 << 2) << 8); + + /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ + setbits_le32(&denali_phy[547], (0x3 << 2) << 16); + setbits_le32(&denali_phy[675], (0x3 << 2) << 16); + setbits_le32(&denali_phy[803], (0x3 << 2) << 16); + } else { + /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ + clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); + clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); + clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); + clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); + + /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ + clrbits_le32(&denali_phy[547], (0x3 << 2) << 16); + clrbits_le32(&denali_phy[675], (0x3 << 2) << 16); + clrbits_le32(&denali_phy[803], (0x3 << 2) << 16); + } +} + +static void set_memory_map(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *sdram_params) +{ + const struct rk3399_sdram_channel *sdram_ch = + &sdram_params->ch[channel]; + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_pi = chan->pi->denali_pi; + u32 cs_map; + u32 reduc; + u32 row; + + /* Get row number from ddrconfig setting */ + if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4) + row = 16; + else if (sdram_ch->ddrconfig == 3) + row = 14; + else + row = 15; + + cs_map = (sdram_ch->rank > 1) ? 3 : 1; + reduc = (sdram_ch->bw == 2) ? 0 : 1; + + /* Set the dram configuration to ctrl */ + clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); + clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), + ((3 - sdram_ch->bk) << 16) | + ((16 - row) << 24)); + + clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), + cs_map | (reduc << 16)); + + /* PI_199 PI_COL_DIFF:RW:0:4 */ + clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); + + /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ + clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), + ((3 - sdram_ch->bk) << 16) | + ((16 - row) << 24)); + /* PI_41 PI_CS_MAP:RW:24:4 */ + clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); + if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3)) + writel(0x2EC7FFFF, &denali_pi[34]); +} + +static void set_ds_odt(const struct chan_info *chan, + const struct rk3399_sdram_params *sdram_params) +{ + u32 *denali_phy = chan->publ->denali_phy; + + u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; + u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; + u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; + u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; + u32 reg_value; + + if (sdram_params->base.dramtype == LPDDR4) { + tsel_rd_select_p = PHY_DRV_ODT_Hi_Z; + tsel_wr_select_p = PHY_DRV_ODT_40; + ca_tsel_wr_select_p = PHY_DRV_ODT_40; + tsel_idle_select_p = PHY_DRV_ODT_Hi_Z; + + tsel_rd_select_n = PHY_DRV_ODT_240; + tsel_wr_select_n = PHY_DRV_ODT_40; + ca_tsel_wr_select_n = PHY_DRV_ODT_40; + tsel_idle_select_n = PHY_DRV_ODT_240; + } else if (sdram_params->base.dramtype == LPDDR3) { + tsel_rd_select_p = PHY_DRV_ODT_240; + tsel_wr_select_p = PHY_DRV_ODT_34_3; + ca_tsel_wr_select_p = PHY_DRV_ODT_48; + tsel_idle_select_p = PHY_DRV_ODT_240; + + tsel_rd_select_n = PHY_DRV_ODT_Hi_Z; + tsel_wr_select_n = PHY_DRV_ODT_34_3; + ca_tsel_wr_select_n = PHY_DRV_ODT_48; + tsel_idle_select_n = PHY_DRV_ODT_Hi_Z; + } else { + tsel_rd_select_p = PHY_DRV_ODT_240; + tsel_wr_select_p = PHY_DRV_ODT_34_3; + ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; + tsel_idle_select_p = PHY_DRV_ODT_240; + + tsel_rd_select_n = PHY_DRV_ODT_240; + tsel_wr_select_n = PHY_DRV_ODT_34_3; + ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; + tsel_idle_select_n = PHY_DRV_ODT_240; + } + + if (sdram_params->base.odt == 1) + tsel_rd_en = 1; + else + tsel_rd_en = 0; + + tsel_wr_en = 0; + tsel_idle_en = 0; + + /* + * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 + * sets termination values for read/idle cycles and drive strength + * for write cycles for DQ/DM + */ + reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | + (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | + (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); + clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); + + /* + * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 + * sets termination values for read/idle cycles and drive strength + * for write cycles for DQS + */ + clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); + + /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ + reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); + clrsetbits_le32(&denali_phy[544], 0xff, reg_value); + clrsetbits_le32(&denali_phy[672], 0xff, reg_value); + clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + + /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ + clrsetbits_le32(&denali_phy[928], 0xff, reg_value); + + /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ + clrsetbits_le32(&denali_phy[937], 0xff, reg_value); + + /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ + clrsetbits_le32(&denali_phy[935], 0xff, reg_value); + + /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ + clrsetbits_le32(&denali_phy[939], 0xff, reg_value); + + /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ + clrsetbits_le32(&denali_phy[929], 0xff, reg_value); + + /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ + clrsetbits_le32(&denali_phy[924], 0xff, + tsel_wr_select_n | (tsel_wr_select_p << 4)); + clrsetbits_le32(&denali_phy[925], 0xff, + tsel_rd_select_n | (tsel_rd_select_p << 4)); + + /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ + reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) + << 16; + clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); + clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); + clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); + clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); + + /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ + reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) + << 24; + clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); + clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); + clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); + clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); + + /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ + reg_value = tsel_wr_en << 8; + clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); + clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); + clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); + + /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ + reg_value = tsel_wr_en << 17; + clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); + /* + * pad_rst/cke/cs/clk_term tsel 1bits + * DENALI_PHY_938/936/940/934 offset_17 + */ + clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); + clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); + clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); + clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); + + /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ + clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); +} + +static int phy_io_config(const struct chan_info *chan, + const struct rk3399_sdram_params *sdram_params) +{ + u32 *denali_phy = chan->publ->denali_phy; + u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; + u32 mode_sel; + u32 reg_value; + u32 drv_value, odt_value; + u32 speed; + + /* vref setting */ + if (sdram_params->base.dramtype == LPDDR4) { + /* LPDDR4 */ + vref_mode_dq = 0x6; + vref_value_dq = 0x1f; + vref_mode_ac = 0x6; + vref_value_ac = 0x1f; + } else if (sdram_params->base.dramtype == LPDDR3) { + if (sdram_params->base.odt == 1) { + vref_mode_dq = 0x5; /* LPDDR3 ODT */ + drv_value = (readl(&denali_phy[6]) >> 12) & 0xf; + odt_value = (readl(&denali_phy[6]) >> 4) & 0xf; + if (drv_value == PHY_DRV_ODT_48) { + switch (odt_value) { + case PHY_DRV_ODT_240: + vref_value_dq = 0x16; + break; + case PHY_DRV_ODT_120: + vref_value_dq = 0x26; + break; + case PHY_DRV_ODT_60: + vref_value_dq = 0x36; + break; + default: + debug("Invalid ODT value.\n"); + return -EINVAL; + } + } else if (drv_value == PHY_DRV_ODT_40) { + switch (odt_value) { + case PHY_DRV_ODT_240: + vref_value_dq = 0x19; + break; + case PHY_DRV_ODT_120: + vref_value_dq = 0x23; + break; + case PHY_DRV_ODT_60: + vref_value_dq = 0x31; + break; + default: + debug("Invalid ODT value.\n"); + return -EINVAL; + } + } else if (drv_value == PHY_DRV_ODT_34_3) { + switch (odt_value) { + case PHY_DRV_ODT_240: + vref_value_dq = 0x17; + break; + case PHY_DRV_ODT_120: + vref_value_dq = 0x20; + break; + case PHY_DRV_ODT_60: + vref_value_dq = 0x2e; + break; + default: + debug("Invalid ODT value.\n"); + return -EINVAL; + } + } else { + debug("Invalid DRV value.\n"); + return -EINVAL; + } + } else { + vref_mode_dq = 0x2; /* LPDDR3 */ + vref_value_dq = 0x1f; + } + vref_mode_ac = 0x2; + vref_value_ac = 0x1f; + } else if (sdram_params->base.dramtype == DDR3) { + /* DDR3L */ + vref_mode_dq = 0x1; + vref_value_dq = 0x1f; + vref_mode_ac = 0x1; + vref_value_ac = 0x1f; + } else { + debug("Unknown DRAM type.\n"); + return -EINVAL; + } + + reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; + + /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ + clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); + /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ + clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); + /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ + clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); + /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ + clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); + + reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; + + /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ + clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); + + if (sdram_params->base.dramtype == LPDDR4) + mode_sel = 0x6; + else if (sdram_params->base.dramtype == LPDDR3) + mode_sel = 0x0; + else if (sdram_params->base.dramtype == DDR3) + mode_sel = 0x1; + else + return -EINVAL; + + /* PHY_924 PHY_PAD_FDBK_DRIVE */ + clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); + + + /* speed setting */ + if (sdram_params->base.ddr_freq < 400) + speed = 0x0; + else if (sdram_params->base.ddr_freq < 800) + speed = 0x1; + else if (sdram_params->base.ddr_freq < 1200) + speed = 0x2; + else + speed = 0x3; + + /* PHY_924 PHY_PAD_FDBK_DRIVE */ + clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); + + return 0; +} + +static int pctl_cfg(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *sdram_params) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_pi = chan->pi->denali_pi; + u32 *denali_phy = chan->publ->denali_phy; + const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; + const u32 *params_phy = sdram_params->phy_regs.denali_phy; + u32 tmp, tmp1, tmp2; + u32 pwrup_srefresh_exit; + int ret; + + /* + * work around controller bug: + * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed + */ + copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], + sizeof(struct rk3399_ddr_pctl_regs) - 4); + writel(params_ctl[0], &denali_ctl[0]); + copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], + sizeof(struct rk3399_ddr_pi_regs)); + /* rank count need to set for init */ + set_memory_map(chan, channel, sdram_params); + + writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); + writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); + writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); + + pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; + clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); + + /* PHY_DLL_RST_EN */ + clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24); + + setbits_le32(&denali_pi[0], START); + setbits_le32(&denali_ctl[0], START); + + /* Wating for phy DLL lock */ + while (1) { + tmp = readl(&denali_phy[920]); + tmp1 = readl(&denali_phy[921]); + tmp2 = readl(&denali_phy[922]); + if ((((tmp >> 16) & 0x1) == 0x1) && + (((tmp1 >> 16) & 0x1) == 0x1) && + (((tmp1 >> 0) & 0x1) == 0x1) && + (((tmp2 >> 0) & 0x1) == 0x1)) + break; + } + + copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); + copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); + copy_to_reg(&denali_phy[128], ¶ms_phy[128], (218 - 128 + 1) * 4); + copy_to_reg(&denali_phy[256], ¶ms_phy[256], (346 - 256 + 1) * 4); + copy_to_reg(&denali_phy[384], ¶ms_phy[384], (474 - 384 + 1) * 4); + copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); + copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); + copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); + set_ds_odt(chan, sdram_params); + + /* + * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 + * dqs_tsel_wr_end[7:4] add Half cycle + */ + tmp = (readl(&denali_phy[84]) >> 8) & 0xff; + clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); + tmp = (readl(&denali_phy[212]) >> 8) & 0xff; + clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); + tmp = (readl(&denali_phy[340]) >> 8) & 0xff; + clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); + tmp = (readl(&denali_phy[468]) >> 8) & 0xff; + clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); + + /* + * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 + * dq_tsel_wr_end[7:4] add Half cycle + */ + tmp = (readl(&denali_phy[83]) >> 16) & 0xff; + clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); + tmp = (readl(&denali_phy[211]) >> 16) & 0xff; + clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); + tmp = (readl(&denali_phy[339]) >> 16) & 0xff; + clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); + tmp = (readl(&denali_phy[467]) >> 16) & 0xff; + clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); + + ret = phy_io_config(chan, sdram_params); + if (ret) + return ret; + + /* PHY_DLL_RST_EN */ + clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); + + /* Wating for PHY and DRAM init complete */ + tmp = 0; + while (!(readl(&denali_ctl[203]) & (1 << 3))) { + mdelay(10); + tmp++; + if (tmp > 10) + return -ETIME; + } + + clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, + pwrup_srefresh_exit); + return 0; +} + +static void select_per_cs_training_index(const struct chan_info *chan, + u32 rank) +{ + u32 *denali_phy = chan->publ->denali_phy; + + /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ + if ((readl(&denali_phy[84])>>16) & 1) { + /* + * PHY_8/136/264/392 + * phy_per_cs_training_index_X 1bit offset_24 + */ + clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); + clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); + clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); + clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); + } +} + +static void override_write_leveling_value(const struct chan_info *chan) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_phy = chan->publ->denali_phy; + u32 byte; + + /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ + setbits_le32(&denali_phy[896], 1); + + /* + * PHY_8/136/264/392 + * phy_per_cs_training_multicast_en_X 1bit offset_16 + */ + clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); + + for (byte = 0; byte < 4; byte++) + clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, + 0x200 << 16); + + /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ + clrbits_le32(&denali_phy[896], 1); + + /* CTL_200 ctrlupd_req 1bit offset_8 */ + clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); +} + +static int data_training_ca(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *sdram_params) +{ + u32 *denali_pi = chan->pi->denali_pi; + u32 *denali_phy = chan->publ->denali_phy; + u32 i, tmp; + u32 obs_0, obs_1, obs_2, obs_err = 0; + u32 rank = sdram_params->ch[channel].rank; + + for (i = 0; i < rank; i++) { + select_per_cs_training_index(chan, i); + /* PI_100 PI_CALVL_EN:RW:8:2 */ + clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); + /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ + clrsetbits_le32(&denali_pi[92], + (0x1 << 16) | (0x3 << 24), + (0x1 << 16) | (i << 24)); + + /* Waiting for training complete */ + while (1) { + /* PI_174 PI_INT_STATUS:RD:8:18 */ + tmp = readl(&denali_pi[174]) >> 8; + /* + * check status obs + * PHY_532/660/789 phy_adr_calvl_obs1_:0:32 + */ + obs_0 = readl(&denali_phy[532]); + obs_1 = readl(&denali_phy[660]); + obs_2 = readl(&denali_phy[788]); + if (((obs_0 >> 30) & 0x3) || + ((obs_1 >> 30) & 0x3) || + ((obs_2 >> 30) & 0x3)) + obs_err = 1; + if ((((tmp >> 11) & 0x1) == 0x1) && + (((tmp >> 13) & 0x1) == 0x1) && + (((tmp >> 5) & 0x1) == 0x0) && + (obs_err == 0)) + break; + else if ((((tmp >> 5) & 0x1) == 0x1) || + (obs_err == 1)) + return -EIO; + } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + } + clrbits_le32(&denali_pi[100], 0x3 << 8); + + return 0; +} + +static int data_training_wl(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *sdram_params) +{ + u32 *denali_pi = chan->pi->denali_pi; + u32 *denali_phy = chan->publ->denali_phy; + u32 i, tmp; + u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; + u32 rank = sdram_params->ch[channel].rank; + + for (i = 0; i < rank; i++) { + select_per_cs_training_index(chan, i); + /* PI_60 PI_WRLVL_EN:RW:8:2 */ + clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); + /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ + clrsetbits_le32(&denali_pi[59], + (0x1 << 8) | (0x3 << 16), + (0x1 << 8) | (i << 16)); + + /* Waiting for training complete */ + while (1) { + /* PI_174 PI_INT_STATUS:RD:8:18 */ + tmp = readl(&denali_pi[174]) >> 8; + + /* + * check status obs, if error maybe can not + * get leveling done PHY_40/168/296/424 + * phy_wrlvl_status_obs_X:0:13 + */ + obs_0 = readl(&denali_phy[40]); + obs_1 = readl(&denali_phy[168]); + obs_2 = readl(&denali_phy[296]); + obs_3 = readl(&denali_phy[424]); + if (((obs_0 >> 12) & 0x1) || + ((obs_1 >> 12) & 0x1) || + ((obs_2 >> 12) & 0x1) || + ((obs_3 >> 12) & 0x1)) + obs_err = 1; + if ((((tmp >> 10) & 0x1) == 0x1) && + (((tmp >> 13) & 0x1) == 0x1) && + (((tmp >> 4) & 0x1) == 0x0) && + (obs_err == 0)) + break; + else if ((((tmp >> 4) & 0x1) == 0x1) || + (obs_err == 1)) + return -EIO; + } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + } + + override_write_leveling_value(chan); + clrbits_le32(&denali_pi[60], 0x3 << 8); + + return 0; +} + +static int data_training_rg(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *sdram_params) +{ + u32 *denali_pi = chan->pi->denali_pi; + u32 *denali_phy = chan->publ->denali_phy; + u32 i, tmp; + u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; + u32 rank = sdram_params->ch[channel].rank; + + for (i = 0; i < rank; i++) { + select_per_cs_training_index(chan, i); + /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ + clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); + /* + * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 + * PI_RDLVL_CS:RW:24:2 + */ + clrsetbits_le32(&denali_pi[74], + (0x1 << 16) | (0x3 << 24), + (0x1 << 16) | (i << 24)); + + /* Waiting for training complete */ + while (1) { + /* PI_174 PI_INT_STATUS:RD:8:18 */ + tmp = readl(&denali_pi[174]) >> 8; + + /* + * check status obs + * PHY_43/171/299/427 + * PHY_GTLVL_STATUS_OBS_x:16:8 + */ + obs_0 = readl(&denali_phy[43]); + obs_1 = readl(&denali_phy[171]); + obs_2 = readl(&denali_phy[299]); + obs_3 = readl(&denali_phy[427]); + if (((obs_0 >> (16 + 6)) & 0x3) || + ((obs_1 >> (16 + 6)) & 0x3) || + ((obs_2 >> (16 + 6)) & 0x3) || + ((obs_3 >> (16 + 6)) & 0x3)) + obs_err = 1; + if ((((tmp >> 9) & 0x1) == 0x1) && + (((tmp >> 13) & 0x1) == 0x1) && + (((tmp >> 3) & 0x1) == 0x0) && + (obs_err == 0)) + break; + else if ((((tmp >> 3) & 0x1) == 0x1) || + (obs_err == 1)) + return -EIO; + } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + } + clrbits_le32(&denali_pi[80], 0x3 << 24); + + return 0; +} + +static int data_training_rl(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *sdram_params) +{ + u32 *denali_pi = chan->pi->denali_pi; + u32 i, tmp; + u32 rank = sdram_params->ch[channel].rank; + + for (i = 0; i < rank; i++) { + select_per_cs_training_index(chan, i); + /* PI_80 PI_RDLVL_EN:RW:16:2 */ + clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); + /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ + clrsetbits_le32(&denali_pi[74], + (0x1 << 8) | (0x3 << 24), + (0x1 << 8) | (i << 24)); + + /* Waiting for training complete */ + while (1) { + /* PI_174 PI_INT_STATUS:RD:8:18 */ + tmp = readl(&denali_pi[174]) >> 8; + + /* + * make sure status obs not report error bit + * PHY_46/174/302/430 + * phy_rdlvl_status_obs_X:16:8 + */ + if ((((tmp >> 8) & 0x1) == 0x1) && + (((tmp >> 13) & 0x1) == 0x1) && + (((tmp >> 2) & 0x1) == 0x0)) + break; + else if (((tmp >> 2) & 0x1) == 0x1) + return -EIO; + } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + } + clrbits_le32(&denali_pi[80], 0x3 << 16); + + return 0; +} + +static int data_training_wdql(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *sdram_params) +{ + u32 *denali_pi = chan->pi->denali_pi; + u32 i, tmp; + u32 rank = sdram_params->ch[channel].rank; + + for (i = 0; i < rank; i++) { + select_per_cs_training_index(chan, i); + /* + * disable PI_WDQLVL_VREF_EN before wdq leveling? + * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 + */ + clrbits_le32(&denali_pi[181], 0x1 << 8); + /* PI_124 PI_WDQLVL_EN:RW:16:2 */ + clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); + /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ + clrsetbits_le32(&denali_pi[121], + (0x1 << 8) | (0x3 << 16), + (0x1 << 8) | (i << 16)); + + /* Waiting for training complete */ + while (1) { + /* PI_174 PI_INT_STATUS:RD:8:18 */ + tmp = readl(&denali_pi[174]) >> 8; + if ((((tmp >> 12) & 0x1) == 0x1) && + (((tmp >> 13) & 0x1) == 0x1) && + (((tmp >> 6) & 0x1) == 0x0)) + break; + else if (((tmp >> 6) & 0x1) == 0x1) + return -EIO; + } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + } + clrbits_le32(&denali_pi[124], 0x3 << 16); + + return 0; +} + +static int data_training(const struct chan_info *chan, u32 channel, + const struct rk3399_sdram_params *sdram_params, + u32 training_flag) +{ + u32 *denali_phy = chan->publ->denali_phy; + + /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ + setbits_le32(&denali_phy[927], (1 << 22)); + + if (training_flag == PI_FULL_TRAINING) { + if (sdram_params->base.dramtype == LPDDR4) { + training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | + PI_READ_GATE_TRAINING | + PI_READ_LEVELING | PI_WDQ_LEVELING; + } else if (sdram_params->base.dramtype == LPDDR3) { + training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | + PI_READ_GATE_TRAINING; + } else if (sdram_params->base.dramtype == DDR3) { + training_flag = PI_WRITE_LEVELING | + PI_READ_GATE_TRAINING | + PI_READ_LEVELING; + } + } + + /* ca training(LPDDR4,LPDDR3 support) */ + if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) + data_training_ca(chan, channel, sdram_params); + + /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ + if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) + data_training_wl(chan, channel, sdram_params); + + /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ + if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) + data_training_rg(chan, channel, sdram_params); + + /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ + if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) + data_training_rl(chan, channel, sdram_params); + + /* wdq leveling(LPDDR4 support) */ + if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) + data_training_wdql(chan, channel, sdram_params); + + /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ + clrbits_le32(&denali_phy[927], (1 << 22)); + + return 0; +} + +static void set_ddrconfig(const struct chan_info *chan, + const struct rk3399_sdram_params *sdram_params, + unsigned char channel, u32 ddrconfig) +{ + /* only need to set ddrconfig */ + struct rk3399_msch_regs *ddr_msch_regs = chan->msch; + unsigned int cs0_cap = 0; + unsigned int cs1_cap = 0; + + cs0_cap = (1 << (sdram_params->ch[channel].cs0_row + + sdram_params->ch[channel].col + + sdram_params->ch[channel].bk + + sdram_params->ch[channel].bw - 20)); + if (sdram_params->ch[channel].rank > 1) + cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row + - sdram_params->ch[channel].cs1_row); + if (sdram_params->ch[channel].row_3_4) { + cs0_cap = cs0_cap * 3 / 4; + cs1_cap = cs1_cap * 3 / 4; + } + + writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); + writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8), + &ddr_msch_regs->ddrsize); +} + +static void dram_all_config(struct dram_info *dram, + const struct rk3399_sdram_params *sdram_params) +{ + u32 sys_reg = 0; + unsigned int channel, idx; + + sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= (sdram_params->base.num_channels - 1) + << SYS_REG_NUM_CH_SHIFT; + for (channel = 0, idx = 0; + (idx < sdram_params->base.num_channels) && (channel < 2); + channel++) { + const struct rk3399_sdram_channel *info = + &sdram_params->ch[channel]; + struct rk3399_msch_regs *ddr_msch_regs; + const struct rk3399_msch_timings *noc_timing; + + if (sdram_params->ch[channel].col == 0) + continue; + idx++; + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel); + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel); + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel); + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel); + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel); + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); + + ddr_msch_regs = dram->chan[channel].msch; + noc_timing = &sdram_params->ch[channel].noc_timings; + writel(noc_timing->ddrtiminga0, + &ddr_msch_regs->ddrtiminga0); + writel(noc_timing->ddrtimingb0, + &ddr_msch_regs->ddrtimingb0); + writel(noc_timing->ddrtimingc0, + &ddr_msch_regs->ddrtimingc0); + writel(noc_timing->devtodev0, + &ddr_msch_regs->devtodev0); + writel(noc_timing->ddrmode, + &ddr_msch_regs->ddrmode); + + /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ + if (sdram_params->ch[channel].rank == 1) + setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], + 1 << 17); + } + + writel(sys_reg, &dram->pmugrf->os_reg2); + rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, + sdram_params->base.stride << 10); + + /* reboot hold register set */ + writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | + PRESET_GPIO1_HOLD(1), + &dram->pmucru->pmucru_rstnhold_con[1]); + clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); +} + +static int switch_to_phy_index1(struct dram_info *dram, + const struct rk3399_sdram_params *sdram_params) +{ + u32 channel; + u32 *denali_phy; + u32 ch_count = sdram_params->base.num_channels; + int ret; + int i = 0; + + writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, + 1 << 4 | 1 << 2 | 1), + &dram->cic->cic_ctrl0); + while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { + mdelay(10); + i++; + if (i > 10) { + debug("index1 frequency change overtime\n"); + return -ETIME; + } + } + + i = 0; + writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0); + while (!(readl(&dram->cic->cic_status0) & (1 << 0))) { + mdelay(10); + if (i > 10) { + debug("index1 frequency done overtime\n"); + return -ETIME; + } + } + + for (channel = 0; channel < ch_count; channel++) { + denali_phy = dram->chan[channel].publ->denali_phy; + clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); + ret = data_training(&dram->chan[channel], channel, + sdram_params, PI_FULL_TRAINING); + if (ret) { + debug("index1 training failed\n"); + return ret; + } + } + + return 0; +} + +static int sdram_init(struct dram_info *dram, + const struct rk3399_sdram_params *sdram_params) +{ + unsigned char dramtype = sdram_params->base.dramtype; + unsigned int ddr_freq = sdram_params->base.ddr_freq; + int channel; + + debug("Starting SDRAM initialization...\n"); + + if ((dramtype == DDR3 && ddr_freq > 800) || + (dramtype == LPDDR3 && ddr_freq > 933) || + (dramtype == LPDDR4 && ddr_freq > 800)) { + debug("SDRAM frequency is to high!"); + return -E2BIG; + } + + for (channel = 0; channel < 2; channel++) { + const struct chan_info *chan = &dram->chan[channel]; + struct rk3399_ddr_publ_regs *publ = chan->publ; + + phy_dll_bypass_set(publ, ddr_freq); + + if (channel >= sdram_params->base.num_channels) + continue; + + if (pctl_cfg(chan, channel, sdram_params) != 0) { + printf("pctl_cfg fail, reset\n"); + return -EIO; + } + + /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ + if (dramtype == LPDDR3) + udelay(10); + + if (data_training(chan, channel, + sdram_params, PI_FULL_TRAINING)) { + printf("SDRAM initialization failed, reset\n"); + return -EIO; + } + + set_ddrconfig(chan, sdram_params, channel, + sdram_params->ch[channel].ddrconfig); + } + dram_all_config(dram, sdram_params); + switch_to_phy_index1(dram, sdram_params); + + debug("Finish SDRAM initialization...\n"); + return 0; +} + +static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_dmc_plat *plat = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + int ret; + + ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", + (u32 *)&plat->sdram_params, + sizeof(plat->sdram_params) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,sdram-params %d\n", + __func__, ret); + return ret; + } + ret = regmap_init_mem(dev, &plat->map); + if (ret) + printf("%s: regmap failed %d\n", __func__, ret); + +#endif + return 0; +} + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_platdata(struct udevice *dev) +{ + struct rockchip_dmc_plat *plat = dev_get_platdata(dev); + struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; + int ret; + + ret = regmap_init_mem_platdata(dev, dtplat->reg, + ARRAY_SIZE(dtplat->reg) / 4, + &plat->map); + if (ret) + return ret; + + return 0; +} +#endif + +static int rk3399_dmc_init(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rockchip_dmc_plat *plat = dev_get_platdata(dev); + int ret; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3399_sdram_params *params = &plat->sdram_params; +#else + struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; + struct rk3399_sdram_params *params = + (void *)dtplat->rockchip_sdram_params; + + ret = conv_of_platdata(dev); + if (ret) + return ret; +#endif + + priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); + priv->pmucru = rockchip_get_pmucru(); + priv->cru = rockchip_get_cru(); + priv->chan[0].pctl = regmap_get_range(plat->map, 0); + priv->chan[0].pi = regmap_get_range(plat->map, 1); + priv->chan[0].publ = regmap_get_range(plat->map, 2); + priv->chan[0].msch = regmap_get_range(plat->map, 3); + priv->chan[1].pctl = regmap_get_range(plat->map, 4); + priv->chan[1].pi = regmap_get_range(plat->map, 5); + priv->chan[1].publ = regmap_get_range(plat->map, 6); + priv->chan[1].msch = regmap_get_range(plat->map, 7); + + debug("con reg %p %p %p %p %p %p %p %p\n", + priv->chan[0].pctl, priv->chan[0].pi, + priv->chan[0].publ, priv->chan[0].msch, + priv->chan[1].pctl, priv->chan[1].pi, + priv->chan[1].publ, priv->chan[1].msch); + debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru, + priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru); +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); +#else + ret = clk_get_by_index(dev, 0, &priv->ddr_clk); +#endif + if (ret) { + printf("%s clk get failed %d\n", __func__, ret); + return ret; + } + ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); + if (ret < 0) { + printf("%s clk set failed %d\n", __func__, ret); + return ret; + } + ret = sdram_init(priv, params); + if (ret < 0) { + printf("%s DRAM init failed%d\n", __func__, ret); + return ret; + } + + return 0; +} +#endif + +size_t sdram_size_mb(struct dram_info *dram) +{ + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; + size_t chipsize_mb = 0; + size_t size_mb = 0; + u32 ch; + + u32 sys_reg = readl(&dram->pmugrf->os_reg2); + u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) + & SYS_REG_NUM_CH_MASK); + + for (ch = 0; ch < ch_num; ch++) { + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & + SYS_REG_RANK_MASK); + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK); + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK); + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & + SYS_REG_ROW_3_4_MASK; + + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + + if (rank > 1) + chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); + if (row_3_4) + chipsize_mb = chipsize_mb * 3 / 4; + size_mb += chipsize_mb; + } + + /* + * we use the 0x00000000~0xf7ffffff space + * since 0xf8000000~0xffffffff is soc register space + * so we reserve it + */ + size_mb = min_t(size_t, size_mb, 0xf8000000/(1<<20)); + + return size_mb; +} + +static int rk3399_dmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_SPL_BUILD + if (rk3399_dmc_init(dev)) + return 0; +#else + struct dram_info *priv = dev_get_priv(dev); + + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); +#endif + return 0; +} + +static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + info = &priv->info; + priv->info.base = 0; + priv->info.size = sdram_size_mb(priv) << 20; + + return 0; +} + +static struct ram_ops rk3399_dmc_ops = { + .get_info = rk3399_dmc_get_info, +}; + + +static const struct udevice_id rk3399_dmc_ids[] = { + { .compatible = "rockchip,rk3399-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3399) = { + .name = "rockchip_rk3399_dmc", + .id = UCLASS_RAM, + .of_match = rk3399_dmc_ids, + .ops = &rk3399_dmc_ops, +#ifdef CONFIG_SPL_BUILD + .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata, +#endif + .probe = rk3399_dmc_probe, +#ifdef CONFIG_SPL_BUILD + .priv_auto_alloc_size = sizeof(struct dram_info), + .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat), +#endif +}; diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index 2cef68bc4d..d32985b453 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -12,6 +12,8 @@ static const struct udevice_id rk3399_syscon_ids[] = { { .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF }, { .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF }, + { .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC }, }; U_BOOT_DRIVER(syscon_rk3399) = { @@ -19,3 +21,41 @@ U_BOOT_DRIVER(syscon_rk3399) = { .id = UCLASS_SYSCON, .of_match = rk3399_syscon_ids, }; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rk3399_syscon_bind_of_platdata(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rk3399_grf) = { + .name = "rockchip_rk3399_grf", + .id = UCLASS_SYSCON, + .of_match = rk3399_syscon_ids, + .bind = rk3399_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3399_pmugrf) = { + .name = "rockchip_rk3399_pmugrf", + .id = UCLASS_SYSCON, + .of_match = rk3399_syscon_ids + 1, + .bind = rk3399_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3399_pmusgrf) = { + .name = "rockchip_rk3399_pmusgrf", + .id = UCLASS_SYSCON, + .of_match = rk3399_syscon_ids + 2, + .bind = rk3399_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3399_cic) = { + .name = "rockchip_rk3399_cic", + .id = UCLASS_SYSCON, + .of_match = rk3399_syscon_ids + 3, + .bind = rk3399_syscon_bind_of_platdata, +}; +#endif diff --git a/arch/arm/mach-stm32/stm32f7/Makefile b/arch/arm/mach-stm32/stm32f7/Makefile index 643d4d919c..03269bd461 100644 --- a/arch/arm/mach-stm32/stm32f7/Makefile +++ b/arch/arm/mach-stm32/stm32f7/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += timer.o clock.o soc.o +obj-y += timer.o soc.o diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c index 8baee99a4f..06af631cc1 100644 --- a/arch/arm/mach-stm32/stm32f7/soc.c +++ b/arch/arm/mach-stm32/stm32f7/soc.c @@ -17,8 +17,6 @@ u32 get_cpu_rev(void) int arch_cpu_init(void) { - configure_clocks(); - /* * Configure the memory protection unit (MPU) * 0x00000000 - 0xffffffff: Strong-order, Shareable diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index 40383c11c9..1369cd095b 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -4,645 +4,65 @@ * * SPDX-License-Identifier: GPL-2.0+ */ +#include <clk.h> #include <common.h> -#include <errno.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> +#include <dm.h> #include <asm/arch/clk.h> -/* Board oscillator frequency */ -#ifndef CONFIG_ZYNQ_PS_CLK_FREQ -# define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL -#endif - -/* Register bitfield defines */ -#define PLLCTRL_FBDIV_MASK 0x7f000 -#define PLLCTRL_FBDIV_SHIFT 12 -#define PLLCTRL_BPFORCE_MASK (1 << 4) -#define PLLCTRL_PWRDWN_MASK 2 -#define PLLCTRL_PWRDWN_SHIFT 1 -#define PLLCTRL_RESET_MASK 1 -#define PLLCTRL_RESET_SHIFT 0 - -#define ZYNQ_CLK_MAXDIV 0x3f -#define CLK_CTRL_DIV1_SHIFT 20 -#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT) -#define CLK_CTRL_DIV0_SHIFT 8 -#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) -#define CLK_CTRL_SRCSEL_SHIFT 4 -#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT) - -#define CLK_CTRL_DIV2X_SHIFT 26 -#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT) -#define CLK_CTRL_DIV3X_SHIFT 20 -#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT) - -#define ZYNQ_CLKMUX_SEL_0 0 -#define ZYNQ_CLKMUX_SEL_1 1 -#define ZYNQ_CLKMUX_SEL_2 2 -#define ZYNQ_CLKMUX_SEL_3 3 - DECLARE_GLOBAL_DATA_PTR; -struct clk; - -/** - * struct zynq_clk_ops: - * @set_rate: Function pointer to set_rate() implementation - * @get_rate: Function pointer to get_rate() implementation - */ -struct zynq_clk_ops { - int (*set_rate)(struct clk *clk, unsigned long rate); - unsigned long (*get_rate)(struct clk *clk); -}; - -/** - * struct clk: - * @name: Clock name - * @frequency: Currenct frequency - * @parent: Parent clock - * @flags: Clock flags - * @reg: Clock control register - * @ops: Clock operations - */ -struct clk { - char *name; - unsigned long frequency; - enum zynq_clk parent; - unsigned int flags; - u32 *reg; - struct zynq_clk_ops ops; +static const char * const clk_names[clk_max] = { + "armpll", "ddrpll", "iopll", + "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", + "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", + "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", + "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", + "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", + "smc_aper", "swdt", "dbg_trc", "dbg_apb" }; -#define ZYNQ_CLK_FLAGS_HAS_2_DIVS 1 - -static struct clk clks[clk_max]; - -/** - * __zynq_clk_cpu_get_parent() - Decode clock multiplexer - * @srcsel: Mux select value - * Returns the clock identifier associated with the selected mux input. - */ -static int __zynq_clk_cpu_get_parent(unsigned int srcsel) -{ - unsigned int ret; - - switch (srcsel) { - case ZYNQ_CLKMUX_SEL_0: - case ZYNQ_CLKMUX_SEL_1: - ret = armpll_clk; - break; - case ZYNQ_CLKMUX_SEL_2: - ret = ddrpll_clk; - break; - case ZYNQ_CLKMUX_SEL_3: - ret = iopll_clk; - break; - default: - ret = armpll_clk; - break; - } - - return ret; -} - -/** - * ddr2x_get_rate() - Get clock rate of DDR2x clock - * @clk: Clock handle - * Returns the current clock rate of @clk. - */ -static unsigned long ddr2x_get_rate(struct clk *clk) -{ - u32 clk_ctrl = readl(clk->reg); - u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT; - - return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div); -} - -/** - * ddr3x_get_rate() - Get clock rate of DDR3x clock - * @clk: Clock handle - * Returns the current clock rate of @clk. - */ -static unsigned long ddr3x_get_rate(struct clk *clk) -{ - u32 clk_ctrl = readl(clk->reg); - u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT; - - return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div); -} - -static void init_ddr_clocks(void) -{ - u32 div0, div1; - unsigned long prate = zynq_clk_get_rate(ddrpll_clk); - u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); - - /* DDR2x */ - clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl; - clks[ddr2x_clk].parent = ddrpll_clk; - clks[ddr2x_clk].name = "ddr_2x"; - clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]); - clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate; - - /* DDR3x */ - clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl; - clks[ddr3x_clk].parent = ddrpll_clk; - clks[ddr3x_clk].name = "ddr_3x"; - clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]); - clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate; - - /* DCI */ - clk_ctrl = readl(&slcr_base->dci_clk_ctrl); - div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; - div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; - clks[dci_clk].reg = &slcr_base->dci_clk_ctrl; - clks[dci_clk].parent = ddrpll_clk; - clks[dci_clk].frequency = DIV_ROUND_CLOSEST( - DIV_ROUND_CLOSEST(prate, div0), div1); - clks[dci_clk].name = "dci"; - - gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000; -} - -static void init_cpu_clocks(void) -{ - int clk_621; - u32 reg, div, srcsel; - enum zynq_clk parent; - - reg = readl(&slcr_base->arm_clk_ctrl); - clk_621 = readl(&slcr_base->clk_621_true) & 1; - div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; - srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; - parent = __zynq_clk_cpu_get_parent(srcsel); - - /* cpu clocks */ - clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl; - clks[cpu_6or4x_clk].parent = parent; - clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST( - zynq_clk_get_rate(parent), div); - clks[cpu_6or4x_clk].name = "cpu_6or4x"; - - clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl; - clks[cpu_3or2x_clk].parent = cpu_6or4x_clk; - clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2; - clks[cpu_3or2x_clk].name = "cpu_3or2x"; - - clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl; - clks[cpu_2x_clk].parent = cpu_6or4x_clk; - clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / - (2 + clk_621); - clks[cpu_2x_clk].name = "cpu_2x"; - - clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl; - clks[cpu_1x_clk].parent = cpu_6or4x_clk; - clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / - (4 + 2 * clk_621); - clks[cpu_1x_clk].name = "cpu_1x"; -} - -/** - * periph_calc_two_divs() - Calculate clock dividers - * @cur_rate: Current clock rate - * @tgt_rate: Target clock rate - * @prate: Parent clock rate - * @div0: First divider (output) - * @div1: Second divider (output) - * Returns the actual clock rate possible. - * - * Calculates clock dividers for clocks with two 6-bit dividers. - */ -static unsigned long periph_calc_two_divs(unsigned long cur_rate, - unsigned long tgt_rate, unsigned long prate, u32 *div0, - u32 *div1) -{ - long err, best_err = (long)(~0UL >> 1); - unsigned long rate, best_rate = 0; - u32 d0, d1; - - for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) { - for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) { - rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0), - d1); - err = abs(rate - tgt_rate); - - if (err < best_err) { - *div0 = d0; - *div1 = d1; - best_err = err; - best_rate = rate; - } - } - } - - return best_rate; -} - -/** - * zynq_clk_periph_set_rate() - Set clock rate - * @clk: Handle of the peripheral clock - * @rate: New clock rate - * Sets the clock frequency of @clk to @rate. Returns zero on success. - */ -static int zynq_clk_periph_set_rate(struct clk *clk, - unsigned long rate) -{ - u32 ctrl, div0 = 0, div1 = 0; - unsigned long prate, new_rate, cur_rate = clk->frequency; - - ctrl = readl(clk->reg); - prate = zynq_clk_get_rate(clk->parent); - ctrl &= ~CLK_CTRL_DIV0_MASK; - - if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) { - ctrl &= ~CLK_CTRL_DIV1_MASK; - new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0, - &div1); - ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; - } else { - div0 = DIV_ROUND_CLOSEST(prate, rate); - div0 &= ZYNQ_CLK_MAXDIV; - new_rate = DIV_ROUND_CLOSEST(rate, div0); - } - - /* write new divs to hardware */ - ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; - writel(ctrl, clk->reg); - - /* update frequency in clk framework */ - clk->frequency = new_rate; - - return 0; -} - -/** - * zynq_clk_periph_get_rate() - Get clock rate - * @clk: Handle of the peripheral clock - * Returns the current clock rate of @clk. - */ -static unsigned long zynq_clk_periph_get_rate(struct clk *clk) -{ - u32 clk_ctrl = readl(clk->reg); - u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; - u32 div1 = 1; - - if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) - div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; - - /* a register value of zero == division by 1 */ - if (!div0) - div0 = 1; - if (!div1) - div1 = 1; - - return - DIV_ROUND_CLOSEST( - DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0), - div1); -} - -/** - * __zynq_clk_periph_get_parent() - Decode clock multiplexer - * @srcsel: Mux select value - * Returns the clock identifier associated with the selected mux input. - */ -static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel) -{ - switch (srcsel) { - case ZYNQ_CLKMUX_SEL_0: - case ZYNQ_CLKMUX_SEL_1: - return iopll_clk; - case ZYNQ_CLKMUX_SEL_2: - return armpll_clk; - case ZYNQ_CLKMUX_SEL_3: - return ddrpll_clk; - default: - return 0; - } -} - -/** - * zynq_clk_periph_get_parent() - Decode clock multiplexer - * @clk: Clock handle - * Returns the clock identifier associated with the selected mux input. - */ -static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk) -{ - u32 clk_ctrl = readl(clk->reg); - u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; - - return __zynq_clk_periph_get_parent(srcsel); -} - -/** - * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework - * @clk: Pointer to struct clk for the clock - * @ctrl: Clock control register - * @name: PLL name - * @two_divs: Indicates whether the clock features one or two dividers - */ -static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name, - bool two_divs) -{ - clk->name = name; - clk->reg = ctrl; - if (two_divs) - clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS; - clk->parent = zynq_clk_periph_get_parent(clk); - clk->frequency = zynq_clk_periph_get_rate(clk); - clk->ops.get_rate = zynq_clk_periph_get_rate; - clk->ops.set_rate = zynq_clk_periph_set_rate; - - return 0; -} - -static void init_periph_clocks(void) -{ - zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl, - "gem0", 1); - zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl, - "gem1", 1); - - zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl, - "smc", 0); - - zynq_clk_register_periph_clk(&clks[lqspi_clk], - &slcr_base->lqspi_clk_ctrl, "lqspi", 0); - - zynq_clk_register_periph_clk(&clks[sdio0_clk], - &slcr_base->sdio_clk_ctrl, "sdio0", 0); - zynq_clk_register_periph_clk(&clks[sdio1_clk], - &slcr_base->sdio_clk_ctrl, "sdio1", 0); - - zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl, - "spi0", 0); - zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl, - "spi1", 0); - - zynq_clk_register_periph_clk(&clks[uart0_clk], - &slcr_base->uart_clk_ctrl, "uart0", 0); - zynq_clk_register_periph_clk(&clks[uart1_clk], - &slcr_base->uart_clk_ctrl, "uart1", 0); - - zynq_clk_register_periph_clk(&clks[dbg_trc_clk], - &slcr_base->dbg_clk_ctrl, "dbg_trc", 0); - zynq_clk_register_periph_clk(&clks[dbg_apb_clk], - &slcr_base->dbg_clk_ctrl, "dbg_apb", 0); - - zynq_clk_register_periph_clk(&clks[pcap_clk], - &slcr_base->pcap_clk_ctrl, "pcap", 0); - - zynq_clk_register_periph_clk(&clks[fclk0_clk], - &slcr_base->fpga0_clk_ctrl, "fclk0", 1); - zynq_clk_register_periph_clk(&clks[fclk1_clk], - &slcr_base->fpga1_clk_ctrl, "fclk1", 1); - zynq_clk_register_periph_clk(&clks[fclk2_clk], - &slcr_base->fpga2_clk_ctrl, "fclk2", 1); - zynq_clk_register_periph_clk(&clks[fclk3_clk], - &slcr_base->fpga3_clk_ctrl, "fclk3", 1); -} - -/** - * zynq_clk_register_aper_clk() - Set up a APER clock with the framework - * @clk: Pointer to struct clk for the clock - * @ctrl: Clock control register - * @name: PLL name - */ -static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name) -{ - clk->name = name; - clk->reg = ctrl; - clk->parent = cpu_1x_clk; - clk->frequency = zynq_clk_get_rate(clk->parent); -} - -static void init_aper_clocks(void) -{ - zynq_clk_register_aper_clk(&clks[usb0_aper_clk], - &slcr_base->aper_clk_ctrl, "usb0_aper"); - zynq_clk_register_aper_clk(&clks[usb1_aper_clk], - &slcr_base->aper_clk_ctrl, "usb1_aper"); - - zynq_clk_register_aper_clk(&clks[gem0_aper_clk], - &slcr_base->aper_clk_ctrl, "gem0_aper"); - zynq_clk_register_aper_clk(&clks[gem1_aper_clk], - &slcr_base->aper_clk_ctrl, "gem1_aper"); - - zynq_clk_register_aper_clk(&clks[sdio0_aper_clk], - &slcr_base->aper_clk_ctrl, "sdio0_aper"); - zynq_clk_register_aper_clk(&clks[sdio1_aper_clk], - &slcr_base->aper_clk_ctrl, "sdio1_aper"); - - zynq_clk_register_aper_clk(&clks[spi0_aper_clk], - &slcr_base->aper_clk_ctrl, "spi0_aper"); - zynq_clk_register_aper_clk(&clks[spi1_aper_clk], - &slcr_base->aper_clk_ctrl, "spi1_aper"); - - zynq_clk_register_aper_clk(&clks[can0_aper_clk], - &slcr_base->aper_clk_ctrl, "can0_aper"); - zynq_clk_register_aper_clk(&clks[can1_aper_clk], - &slcr_base->aper_clk_ctrl, "can1_aper"); - - zynq_clk_register_aper_clk(&clks[i2c0_aper_clk], - &slcr_base->aper_clk_ctrl, "i2c0_aper"); - zynq_clk_register_aper_clk(&clks[i2c1_aper_clk], - &slcr_base->aper_clk_ctrl, "i2c1_aper"); - - zynq_clk_register_aper_clk(&clks[uart0_aper_clk], - &slcr_base->aper_clk_ctrl, "uart0_aper"); - zynq_clk_register_aper_clk(&clks[uart1_aper_clk], - &slcr_base->aper_clk_ctrl, "uart1_aper"); - - zynq_clk_register_aper_clk(&clks[gpio_aper_clk], - &slcr_base->aper_clk_ctrl, "gpio_aper"); - - zynq_clk_register_aper_clk(&clks[lqspi_aper_clk], - &slcr_base->aper_clk_ctrl, "lqspi_aper"); - - zynq_clk_register_aper_clk(&clks[smc_aper_clk], - &slcr_base->aper_clk_ctrl, "smc_aper"); -} - -/** - * __zynq_clk_pll_get_rate() - Get PLL rate - * @addr: Address of the PLL's control register - * Returns the current PLL output rate. - */ -static unsigned long __zynq_clk_pll_get_rate(u32 *addr) -{ - u32 reg, mul, bypass; - - reg = readl(addr); - bypass = reg & PLLCTRL_BPFORCE_MASK; - if (bypass) - mul = 1; - else - mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; - - return CONFIG_ZYNQ_PS_CLK_FREQ * mul; -} - -/** - * zynq_clk_pll_get_rate() - Get PLL rate - * @pll: Handle of the PLL - * Returns the current clock rate of @pll. - */ -static unsigned long zynq_clk_pll_get_rate(struct clk *pll) -{ - return __zynq_clk_pll_get_rate(pll->reg); -} - -/** - * zynq_clk_register_pll() - Set up a PLL with the framework - * @clk: Pointer to struct clk for the PLL - * @ctrl: PLL control register - * @name: PLL name - * @prate: PLL input clock rate - */ -static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name, - unsigned long prate) -{ - clk->name = name; - clk->reg = ctrl; - clk->frequency = zynq_clk_pll_get_rate(clk); - clk->ops.get_rate = zynq_clk_pll_get_rate; -} - -/** - * clkid_2_register() - Get clock control register - * @id: Clock identifier of one of the PLLs - * Returns the address of the requested PLL's control register. - */ -static u32 *clkid_2_register(enum zynq_clk id) -{ - switch (id) { - case armpll_clk: - return &slcr_base->arm_pll_ctrl; - case ddrpll_clk: - return &slcr_base->ddr_pll_ctrl; - case iopll_clk: - return &slcr_base->io_pll_ctrl; - default: - return &slcr_base->io_pll_ctrl; - } -} - -/* API */ -/** - * zynq_clk_early_init() - Early init for the clock framework - * - * This function is called from before relocation and sets up the CPU clock - * frequency in the global data struct. - */ -void zynq_clk_early_init(void) -{ - u32 reg = readl(&slcr_base->arm_clk_ctrl); - u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; - u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; - enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel); - u32 *pllreg = clkid_2_register(parent); - unsigned long prate = __zynq_clk_pll_get_rate(pllreg); - - if (!div) - div = 1; - - gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div); -} - -/** - * get_uart_clk() - Get UART input frequency - * @dev_index: UART ID - * Returns UART input clock frequency in Hz. - * - * Compared to zynq_clk_get_rate() this function is designed to work before - * relocation and can be called when the serial UART is set up. - */ -unsigned long get_uart_clk(int dev_index) -{ - u32 reg = readl(&slcr_base->uart_clk_ctrl); - u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; - u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; - enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel); - u32 *pllreg = clkid_2_register(parent); - unsigned long prate = __zynq_clk_pll_get_rate(pllreg); - - if (!div) - div = 1; - - return DIV_ROUND_CLOSEST(prate, div); -} /** - * set_cpu_clk_info() - Initialize clock framework - * Always returns zero. + * set_cpu_clk_info() - Setup clock information * * This function is called from common code after relocation and sets up the - * clock framework. The framework must not be used before this function had been - * called. + * clock information. */ int set_cpu_clk_info(void) { - zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl, - "armpll", CONFIG_ZYNQ_PS_CLK_FREQ); - zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl, - "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ); - zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl, - "iopll", CONFIG_ZYNQ_PS_CLK_FREQ); - - init_ddr_clocks(); - init_cpu_clocks(); - init_periph_clocks(); - init_aper_clocks(); - - gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; + struct clk clk; + struct udevice *dev; + ulong rate; + int i, ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(zynq_clk), &dev); + if (ret) + return ret; + + for (i = 0; i < 2; i++) { + clk.id = i ? ddr3x_clk : cpu_6or4x_clk; + ret = clk_request(dev, &clk); + if (ret < 0) + return ret; + + rate = clk_get_rate(&clk) / 1000000; + if (i) + gd->bd->bi_ddr_freq = rate; + else + gd->bd->bi_arm_freq = rate; + + clk_free(&clk); + } gd->bd->bi_dsp_freq = 0; return 0; } /** - * zynq_clk_get_rate() - Get clock rate - * @clk: Clock identifier - * Returns the current clock rate of @clk on success or zero for an invalid - * clock id. - */ -unsigned long zynq_clk_get_rate(enum zynq_clk clk) -{ - if (clk < 0 || clk >= clk_max) - return 0; - - return clks[clk].frequency; -} - -/** - * zynq_clk_set_rate() - Set clock rate - * @clk: Clock identifier - * @rate: Requested clock rate - * Passes on the return value from the clock's set_rate() function or negative - * errno. - */ -int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate) -{ - if (clk < 0 || clk >= clk_max) - return -ENODEV; - - if (clks[clk].ops.set_rate) - return clks[clk].ops.set_rate(&clks[clk], rate); - - return -ENXIO; -} - -/** - * zynq_clk_get_name() - Get clock name - * @clk: Clock identifier - * Returns the name of @clk. - */ -const char *zynq_clk_get_name(enum zynq_clk clk) -{ - return clks[clk].name; -} - -/** * soc_clk_dump() - Print clock frequencies * Returns zero on success * @@ -650,13 +70,35 @@ const char *zynq_clk_get_name(enum zynq_clk clk) */ int soc_clk_dump(void) { - int i; + struct udevice *dev; + int i, ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(zynq_clk), &dev); + if (ret) + return ret; printf("clk\t\tfrequency\n"); for (i = 0; i < clk_max; i++) { - const char *name = zynq_clk_get_name(i); - if (name) - printf("%10s%20lu\n", name, zynq_clk_get_rate(i)); + const char *name = clk_names[i]; + if (name) { + struct clk clk; + unsigned long rate; + + clk.id = i; + ret = clk_request(dev, &clk); + if (ret < 0) + return ret; + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + if (rate == (unsigned long)-ENOSYS) + printf("%10s%20s\n", name, "unknown"); + else + printf("%10s%20lu\n", name, rate); + } } return 0; diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index ba9171ebe9..ee1c1a943b 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -35,7 +35,6 @@ int arch_cpu_init(void) writel(0xC, &slcr_base->ddr_urgent); #endif #endif - zynq_clk_early_init(); zynq_slcr_lock(); return 0; diff --git a/arch/arm/mach-zynq/include/mach/clk.h b/arch/arm/mach-zynq/include/mach/clk.h index 250c5bc07b..8a039ae56b 100644 --- a/arch/arm/mach-zynq/include/mach/clk.h +++ b/arch/arm/mach-zynq/include/mach/clk.h @@ -20,10 +20,4 @@ enum zynq_clk { uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk, smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max}; -void zynq_clk_early_init(void); -int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate); -unsigned long zynq_clk_get_rate(enum zynq_clk clk); -const char *zynq_clk_get_name(enum zynq_clk clk); -unsigned long get_uart_clk(int dev_id); - #endif diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h index 44c9b50fe5..67238e7fbc 100644 --- a/arch/arm/mach-zynq/include/mach/sys_proto.h +++ b/arch/arm/mach-zynq/include/mach/sys_proto.h @@ -10,7 +10,6 @@ extern void zynq_slcr_lock(void); extern void zynq_slcr_unlock(void); extern void zynq_slcr_cpu_reset(void); -extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate); extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 2d3bf2acef..2a207ae46c 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -9,7 +9,6 @@ #include <malloc.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/clk.h> #define SLCR_LOCK_MAGIC 0x767B #define SLCR_UNLOCK_MAGIC 0xDF0D @@ -124,34 +123,6 @@ void zynq_slcr_cpu_reset(void) writel(1, &slcr_base->pss_rst_ctrl); } -/* Setup clk for network */ -void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) -{ - int ret; - - zynq_slcr_unlock(); - - if (gem_id > 1) { - printf("Non existing GEM id %d\n", gem_id); - goto out; - } - - ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate); - if (ret) - goto out; - - if (gem_id) { - /* Configure GEM_RCLK_CTRL */ - writel(1, &slcr_base->gem1_rclk_ctrl); - } else { - /* Configure GEM_RCLK_CTRL */ - writel(1, &slcr_base->gem0_rclk_ctrl); - } - udelay(100000); -out: - zynq_slcr_lock(); -} - void zynq_slcr_devcfg_disable(void) { u32 reg_val; diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index 8ff82dc930..b1bb3b80e1 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -1,4 +1,7 @@ /* + * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG + * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> + * * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. * @@ -25,8 +28,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <clk.h> #include <common.h> #include <div64.h> +#include <dm.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/clk.h> @@ -56,6 +61,24 @@ int timer_init(void) (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) | SCUTIMER_CONTROL_ENABLE_MASK; + struct udevice *dev; + struct clk clk; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(zynq_clk), &dev); + if (ret) + return ret; + + clk.id = cpu_6or4x_clk; + ret = clk_request(dev, &clk); + if (ret < 0) + return ret; + + gd->cpu_clk = clk_get_rate(&clk); + + clk_free(&clk); + gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1); /* Load the timer counter register */ diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 1a503042f0..9b65c13b1a 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -284,10 +284,170 @@ static int set_voltage(int i2caddress, int vdd) return vdd_last; } +#ifdef CONFIG_FSL_LSCH3 int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); -#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 fusesr; + u8 vid, buf; + int vdd_target, vdd_current, vdd_last; + int ret, i2caddress; + unsigned long vdd_string_override; + char *vdd_string; + static const uint16_t vdd[32] = { + 10500, + 0, /* reserved */ + 9750, + 0, /* reserved */ + 9500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 10000, /* 1.0000V */ + 0, /* reserved */ + 10250, + 0, /* reserved */ + 10500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + struct vdd_drive { + u8 vid; + unsigned voltage; + }; + + ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID: I2C failed to switch channel\n"); + ret = -1; + goto exit; + } + ret = find_ir_chip_on_i2c(); + if (ret < 0) { + printf("VID: Could not find voltage regulator on I2C.\n"); + ret = -1; + goto exit; + } else { + i2caddress = ret; + debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); + } + + /* check IR chip work on Intel mode*/ + ret = i2c_read(i2caddress, + IR36021_INTEL_MODE_OOFSET, + 1, (void *)&buf, 1); + if (ret) { + printf("VID: failed to read IR chip mode.\n"); + ret = -1; + goto exit; + } + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { + printf("VID: IR Chip is not used in Intel mode.\n"); + ret = -1; + goto exit; + } + + /* get the voltage ID from fuse status register */ + fusesr = in_le32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; + } + vdd_target = vdd[vid]; + + /* check override variable for overriding VDD */ + vdd_string = getenv(CONFIG_VID_FLS_ENV); + if (vdd_override == 0 && vdd_string && + !strict_strtoul(vdd_string, 10, &vdd_string_override)) + vdd_override = vdd_string_override; + + if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { + vdd_target = vdd_override * 10; /* convert to 1/10 mV */ + debug("VDD override is %lu\n", vdd_override); + } else if (vdd_override != 0) { + printf("Invalid value.\n"); + } + + /* divide and round up by 10 to get a value in mV */ + vdd_target = DIV_ROUND_UP(vdd_target, 10); + if (vdd_target == 0) { + debug("VID: VID not used\n"); + ret = 0; + goto exit; + } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) { + /* Check vdd_target is in valid range */ + printf("VID: Target VID %d mV is not in range.\n", + vdd_target); + ret = -1; + goto exit; + } else { + debug("VID: vid = %d mV\n", vdd_target); + } + + /* + * Read voltage monitor to check real voltage. + */ + vdd_last = read_voltage(i2caddress); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjustment\n"); + ret = -1; + goto exit; + } + vdd_current = vdd_last; + debug("VID: Core voltage is currently at %d mV\n", vdd_last); + /* + * Adjust voltage to at or one step above target. + * As measurements are less precise than setting the values + * we may run through dummy steps that cancel each other + * when stepping up and then down. + */ + while (vdd_last > 0 && + vdd_last < vdd_target) { + vdd_current += IR_VDD_STEP_UP; + vdd_last = set_voltage(i2caddress, vdd_current); + } + while (vdd_last > 0 && + vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { + vdd_current -= IR_VDD_STEP_DOWN; + vdd_last = set_voltage(i2caddress, vdd_current); + } + + if (vdd_last > 0) + printf("VID: Core voltage after adjustment is at %d mV\n", + vdd_last); + else + ret = -1; +exit: + if (re_enable) + enable_interrupts(); + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + return ret; +} +#else /* !CONFIG_FSL_LSCH3 */ +int adjust_vdd(ulong vdd_override) +{ + int re_enable = disable_interrupts(); +#if defined(CONFIG_FSL_LSCH2) struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); #else ccsr_gur_t __iomem *gur = @@ -364,11 +524,7 @@ int adjust_vdd(ulong vdd_override) } /* get the voltage ID from fuse status register */ -#ifdef CONFIG_FSL_LSCH3 - fusesr = in_le32(&gur->dcfg_fusesr); -#else fusesr = in_be32(&gur->dcfg_fusesr); -#endif /* * VID is used according to the table below * --------------------------------------- @@ -393,13 +549,6 @@ int adjust_vdd(ulong vdd_override) vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; } -#elif defined(CONFIG_FSL_LSCH3) - vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; - if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { - vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & - FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; - } #else vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; @@ -472,6 +621,7 @@ exit: return ret; } +#endif static int print_vdd(void) { diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 789cae225b..25d22d25bf 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -12,6 +12,7 @@ #ifdef CONFIG_FSL_LS_PPA #include <asm/arch/ppa.h> #endif +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <hwconfig.h> #include <environment.h> @@ -48,6 +49,10 @@ int dram_init(void) mmdc_init(&mparam); gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif return 0; } @@ -91,32 +96,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 4281790426..97ab3400ad 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -14,6 +14,7 @@ #include <asm/arch/ppa.h> #endif #include <asm/arch/fdt.h> +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <ahci.h> #include <hwconfig.h> @@ -76,6 +77,10 @@ int dram_init(void) mmdc_init(&mparam); gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif return 0; } @@ -166,32 +171,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index e3a8a7631b..a23a23be1f 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -12,6 +12,7 @@ #ifdef CONFIG_FSL_LS_PPA #include <asm/arch/ppa.h> #endif +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <hwconfig.h> #include <ahci.h> @@ -80,6 +81,10 @@ int dram_init(void) mmdc_init(&mparam); gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif return 0; } @@ -165,32 +170,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } - -void dram_init_banksize(void) -{ - /* - * gd->secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 7882a9a9a1..c740062887 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -127,32 +127,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 8835a49bb5..6507c09143 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/fdt.h> +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <ahci.h> #include <hwconfig.h> @@ -153,6 +154,10 @@ int dram_init(void) */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); gd->ram_size = initdram(0); +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif return 0; } diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 849f1d1b66..f90b85df1a 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -188,32 +188,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index e213128c1b..2333843958 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -67,13 +67,6 @@ int checkboard(void) return 0; } -int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - int board_early_init_f(void) { fsl_lsch2_early_init_f(); diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index 4ea8b236bf..dc4d689adc 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -112,32 +112,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 552365b9d8..af3f70a38b 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/fdt.h> +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <ahci.h> #include <hwconfig.h> @@ -149,6 +150,10 @@ int dram_init(void) */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); gd->ram_size = initdram(0); +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif return 0; } diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index dd3b5d0e6b..efe2ba6eb1 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -112,32 +112,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 33a58cf440..02b6c4c375 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -56,13 +56,6 @@ int checkboard(void) return 0; } -int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - int board_early_init_f(void) { fsl_lsch2_early_init_f(); diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c index e6130ec709..5ed9e1461b 100644 --- a/board/freescale/ls2080a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -169,58 +169,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - phys_size_t dp_ddr_size; -#endif - - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } - -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - if (soc_has_dp_ddr()) { - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, - CONFIG_DP_DDR_CTRL, - CONFIG_DP_DDR_NUM_CTRLS, - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, - NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); - } - } -#endif -} diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 4f9b9c8a77..9e7701d81f 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -49,13 +49,6 @@ void detail_board_ddr_info(void) #endif } -int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { @@ -123,6 +116,16 @@ int ft_board_setup(void *blob, bd_t *bd) base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size; +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + fdt_fixup_memory_banks(blob, base, size, 2); #ifdef CONFIG_FSL_MC_ENET diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 9c6f477c7f..0408c0fc25 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -169,58 +169,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - phys_size_t dp_ddr_size; -#endif - - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } - -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - if (soc_has_dp_ddr()) { - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, - CONFIG_DP_DDR_CTRL, - CONFIG_DP_DDR_NUM_CTRLS, - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, - NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); - } - } -#endif -} diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 73a61fd75a..277013bfcc 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -22,6 +22,7 @@ #include "../common/qixis.h" #include "ls2080aqds_qixis.h" +#include "../common/vid.h" #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a @@ -240,6 +241,14 @@ int board_early_init_f(void) return 0; } +int misc_init_r(void) +{ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + + return 0; +} + void detail_board_ddr_info(void) { puts("\nDDR "); @@ -254,13 +263,6 @@ void detail_board_ddr_info(void) #endif } -int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { @@ -313,6 +315,16 @@ int ft_board_setup(void *blob, bd_t *bd) base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size; +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + fdt_fixup_memory_banks(blob, base, size, 2); fsl_fdt_fixup_dr_usb(blob, bd); diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 959dfeb02b..2851d5b443 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -172,58 +172,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - phys_size_t dp_ddr_size; -#endif - - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } - -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - if (soc_has_dp_ddr()) { - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, - CONFIG_DP_DDR_CTRL, - CONFIG_DP_DDR_NUM_CTRLS, - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, - NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); - } - } -#endif -} diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 02954ef6d7..4c01f560bc 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -17,6 +17,7 @@ #include <environment.h> #include <efi_loader.h> #include <i2c.h> +#include <asm/arch/mmu.h> #include <asm/arch/soc.h> #include <fsl_sec.h> @@ -202,14 +203,6 @@ int misc_init_r(void) if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); -#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { - efi_add_memory_map(gd->bd->bi_dram[2].start, - gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT, - EFI_RESERVED_MEMORY_TYPE, false); - } -#endif - return 0; } @@ -227,13 +220,6 @@ void detail_board_ddr_info(void) #endif } -int dram_init(void) -{ - gd->ram_size = initdram(0); - - return 0; -} - #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { @@ -286,6 +272,16 @@ int ft_board_setup(void *blob, bd_t *bd) base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size; +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + fdt_fixup_memory_banks(blob, base, size, 2); fsl_fdt_fixup_dr_usb(blob, bd); diff --git a/board/rockchip/evb_rk3328/Kconfig b/board/rockchip/evb_rk3328/Kconfig new file mode 100644 index 0000000000..ef446b49dd --- /dev/null +++ b/board/rockchip/evb_rk3328/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3328 + +config SYS_BOARD + default "evb_rk3328" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3328" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS new file mode 100644 index 0000000000..9db604fa8c --- /dev/null +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3328 +M: William Zhang <william.zhang@rock-chips.com> +S: Maintained +F: board/rockchip/evb_rk3328 +F: include/configs/evb_rk3328.h +F: configs/evb-rk3328_defconfig diff --git a/board/rockchip/evb_rk3328/Makefile b/board/rockchip/evb_rk3328/Makefile new file mode 100644 index 0000000000..81c5de86d4 --- /dev/null +++ b/board/rockchip/evb_rk3328/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb-rk3328.o diff --git a/board/rockchip/evb_rk3328/README b/board/rockchip/evb_rk3328/README new file mode 100644 index 0000000000..6cbb66a4cf --- /dev/null +++ b/board/rockchip/evb_rk3328/README @@ -0,0 +1,70 @@ +Introduction +============ + +RK3328 key features we might use in U-Boot: +* CPU: ARMv8 64bit quad-core Cortex-A53 +* IRAM: 36KB +* DRAM: 4GB-16MB dual-channel +* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50 +* SD/MMC: support SD 3.0, MMC 4.51 +* USB: USB2.0 EHCI host port *2 +* Display: RGB/HDMI/DP/MIPI/EDP + +evb key features: +* regulator: pwm regulator for CPU B/L +* PMIC: rk808 +* debug console: UART2 + +In order to support Arm Trust Firmware(ATF), we need to use the +miniloader from rockchip which: +* do DRAM init +* load and verify ATF image +* load and verify U-Boot image + +Here is the step-by-step to boot to U-Boot on rk3328. + +Get the Source and prebuild binary +================================== + + > mkdir ~/evb_rk3328 + > cd ~/evb_rk3328 + > git clone https://github.com/ARM-software/arm-trusted-firmware.git + > git clone https://github.com/rockchip-linux/rkbin + > git clone https://github.com/rockchip-linux/rkflashtool + +Compile ATF +=============== + + > cd arm-trusted-firmware + > make realclean + > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3328 bl31 + +Compile U-Boot +================== + + > cd ../u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3328_defconfig all + +Compile rkflashtool +======================= + + > cd ../rkflashtool + > make + +Package image for miniloader +================================ + > cd .. + > cp arm-trusted-firmware/build/rk3328/release/bl31.bin rkbin/rk33 + > ./rkbin/tools/trust_merger rkbin/tools/RK3328TRUST.ini + > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img + > mkdir image + > mv trust.img ./image/ + > mv uboot.img ./image/rk3328evb-uboot.bin + +Flash image +=============== +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + + > ./rkflashtool/rkflashloader rk3328evb + +You should be able to get U-Boot log message in console/UART2 now. diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c new file mode 100644 index 0000000000..7e70f381c9 --- /dev/null +++ b/board/rockchip/evb_rk3328/evb-rk3328.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> +#include <dwc3-uboot.h> +#include <usb.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + return 0; +} + +void dram_init_banksize(void) +{ + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = 0x7e000000; +} + +int usb_gadget_handle_interrupts(void) +{ + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + return 0; +} diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 7ed7bf7263..fdad8d13a7 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -27,14 +27,6 @@ const struct stm32_gpio_ctl gpio_ctl_gpout = { .af = STM32_GPIO_AF0 }; -const struct stm32_gpio_ctl gpio_ctl_usart = { - .mode = STM32_GPIO_MODE_AF, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_50M, - .pupd = STM32_GPIO_PUPD_UP, - .af = STM32_GPIO_AF7 -}; - const struct stm32_gpio_ctl gpio_ctl_fmc = { .mode = STM32_GPIO_MODE_AF, .otype = STM32_GPIO_OTYPE_PP, @@ -245,81 +237,24 @@ int dram_init(void) return rv; } -static const struct stm32_gpio_dsc usart_gpio[] = { - {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ - {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */ -}; - int uart_setup_gpio(void) { - int i; - int rv = 0; - clock_setup(GPIO_A_CLOCK_CFG); clock_setup(GPIO_B_CLOCK_CFG); - for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { - rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); - if (rv) - goto out; - } - -out: - return rv; + return 0; } -static const struct stm32x7_serial_platdata serial_platdata = { - .base = (struct stm32_usart *)USART1_BASE, - .clock = CONFIG_SYS_CLK_FREQ, -}; - -U_BOOT_DEVICE(stm32x7_serials) = { - .name = "serial_stm32x7", - .platdata = &serial_platdata, -}; - #ifdef CONFIG_ETH_DESIGNWARE -const struct stm32_gpio_ctl gpio_ctl_eth = { - .mode = STM32_GPIO_MODE_AF, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_100M, - .pupd = STM32_GPIO_PUPD_NO, - .af = STM32_GPIO_AF11 -}; - -static const struct stm32_gpio_dsc eth_gpio[] = { - {STM32_GPIO_PORT_A, STM32_GPIO_PIN_1}, /* ETH_RMII_REF_CLK */ - {STM32_GPIO_PORT_A, STM32_GPIO_PIN_2}, /* ETH_MDIO */ - {STM32_GPIO_PORT_A, STM32_GPIO_PIN_7}, /* ETH_RMII_CRS_DV */ - - {STM32_GPIO_PORT_C, STM32_GPIO_PIN_1}, /* ETH_MDC */ - {STM32_GPIO_PORT_C, STM32_GPIO_PIN_4}, /* ETH_RMII_RXD0 */ - {STM32_GPIO_PORT_C, STM32_GPIO_PIN_5}, /* ETH_RMII_RXD1 */ - - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_11}, /* ETH_RMII_TX_EN */ - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_13}, /* ETH_RMII_TXD0 */ - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_14}, /* ETH_RMII_TXD1 */ -}; static int stmmac_setup(void) { - int res = 0; - int i; - clock_setup(SYSCFG_CLOCK_CFG); - /* Set >RMII mode */ STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; clock_setup(GPIO_A_CLOCK_CFG); clock_setup(GPIO_C_CLOCK_CFG); clock_setup(GPIO_G_CLOCK_CFG); - - for (i = 0; i < ARRAY_SIZE(eth_gpio); i++) { - res = stm32_gpio_config(ð_gpio[i], &gpio_ctl_eth); - if (res) - return res; - } - clock_setup(STMMAC_CLOCK_CFG); return 0; @@ -327,55 +262,12 @@ static int stmmac_setup(void) #endif #ifdef CONFIG_STM32_QSPI -const struct stm32_gpio_ctl gpio_ctl_qspi_9 = { - .mode = STM32_GPIO_MODE_AF, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_100M, - .pupd = STM32_GPIO_PUPD_NO, - .af = STM32_GPIO_AF9 -}; - -const struct stm32_gpio_ctl gpio_ctl_qspi_10 = { - .mode = STM32_GPIO_MODE_AF, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_100M, - .pupd = STM32_GPIO_PUPD_NO, - .af = STM32_GPIO_AF10 -}; - -static const struct stm32_gpio_dsc qspi_af9_gpio[] = { - {STM32_GPIO_PORT_B, STM32_GPIO_PIN_2}, /* QUADSPI_CLK */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_11}, /* QUADSPI_BK1_IO0 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_12}, /* QUADSPI_BK1_IO1 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_13}, /* QUADSPI_BK1_IO3 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_2}, /* QUADSPI_BK1_IO2 */ -}; - -static const struct stm32_gpio_dsc qspi_af10_gpio[] = { - {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* QUADSPI_BK1_NCS */ -}; static int qspi_setup(void) { - int res = 0; - int i; - clock_setup(GPIO_B_CLOCK_CFG); clock_setup(GPIO_D_CLOCK_CFG); clock_setup(GPIO_E_CLOCK_CFG); - - for (i = 0; i < ARRAY_SIZE(qspi_af9_gpio); i++) { - res = stm32_gpio_config(&qspi_af9_gpio[i], &gpio_ctl_qspi_9); - if (res) - return res; - } - - for (i = 0; i < ARRAY_SIZE(qspi_af10_gpio); i++) { - res = stm32_gpio_config(&qspi_af10_gpio[i], &gpio_ctl_qspi_10); - if (res) - return res; - } - return 0; } #endif @@ -390,7 +282,6 @@ int board_early_init_f(void) int res; res = uart_setup_gpio(); - clock_setup(USART1_CLOCK_CFG); if (res) return res; diff --git a/cmd/Kconfig b/cmd/Kconfig index ef53156314..25e3b783a8 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -338,6 +338,20 @@ config CMD_CRC32 help Compute CRC32. +config CMD_MD5SUM + bool "md5sum" + default n + select MD5 + help + Compute MD5 checksum. + +config MD5SUM_VERFIY + bool "md5sum -v" + default n + depends on CMD_MD5SUM + help + Add -v option to verify data against an MD5 checksum. + config LOOPW bool "loopw" help diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index ae3027a297..19b8fd88fa 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -392,6 +392,10 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK); } #endif +#ifdef CONFIG_RESV_RAM + if (gd->arch.resv_ram) + print_num("Reserved ram", gd->arch.resv_ram); +#endif #if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH) print_eths(); #endif @@ -54,7 +54,7 @@ static int extract_env(const char *str, char **env) if (e == NULL) { #ifdef CONFIG_RANDOM_UUID debug("%s unset. ", str); - gen_rand_uuid_str(uuid_str, UUID_STR_FORMAT_STD); + gen_rand_uuid_str(uuid_str, UUID_STR_FORMAT_GUID); setenv(s, uuid_str); e = getenv(s); diff --git a/cmd/itest.c b/cmd/itest.c index 60626c7fe9..e1896d9f97 100644 --- a/cmd/itest.c +++ b/cmd/itest.c @@ -80,7 +80,8 @@ static long evalexp(char *s, int w) l = simple_strtoul(s, NULL, 16); } - return l & ((1UL << (w * 8)) - 1); + /* avoid overflow on mask calculus */ + return (w >= sizeof(long)) ? l : (l & ((1UL << (w * 8)) - 1)); } static char * evalstr(char *s) diff --git a/common/board_f.c b/common/board_f.c index ae6cd8528c..7d1ede0404 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -325,15 +325,6 @@ __weak ulong board_get_usable_ram_top(ulong total_size) return gd->ram_top; } -__weak phys_size_t board_reserve_ram_top(phys_size_t ram_size) -{ -#ifdef CONFIG_SYS_MEM_TOP_HIDE - return ram_size - CONFIG_SYS_MEM_TOP_HIDE; -#else - return ram_size; -#endif -} - static int setup_dest_addr(void) { debug("Monitor len: %08lX\n", gd->mon_len); @@ -341,26 +332,19 @@ static int setup_dest_addr(void) * Ram is setup, size stored in gd !! */ debug("Ram size: %08lX\n", (ulong)gd->ram_size); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - /* Reserve memory for secure MMU tables, and/or security monitor */ - gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; - /* - * Record secure memory location. Need recalcuate if memory splits - * into banks, or the ram base is not zero. - */ - gd->arch.secure_ram = gd->ram_size; -#endif +#if defined(CONFIG_SYS_MEM_TOP_HIDE) /* * Subtract specified amount of memory to hide so that it won't * get "touched" at all by U-Boot. By fixing up gd->ram_size * the Linux kernel should now get passed the now "corrected" - * memory size and won't touch it either. This has been used - * by arch/powerpc exclusively. Now ARMv8 takes advantage of - * thie mechanism. If memory is split into banks, addresses - * need to be calculated. + * memory size and won't touch it either. This should work + * for arch/ppc and arch/powerpc. Only Linux board ports in + * arch/powerpc with bootwrapper support, that recalculate the + * memory size from the SDRAM controller setup will have to + * get fixed. */ - gd->ram_size = board_reserve_ram_top(gd->ram_size); - + gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; +#endif #ifdef CONFIG_SYS_SDRAM_BASE gd->ram_top = CONFIG_SYS_SDRAM_BASE; #endif diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 60ae60c17e..6752b5c65c 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -13,6 +13,24 @@ config SPL help If you want to build SPL as well as the normal image, say Y. +config SPL_RAW_IMAGE_SUPPORT + bool "Support SPL loading and booting of RAW images" + depends on SPL + default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT)) + default y if !TI_SECURE_DEVICE + help + SPL will support loading and booting a RAW image when this option + is y. If this is not set, SPL will move on to other available + boot media to find a suitable image. + +config SPL_LEGACY_IMAGE_SUPPORT + bool "Support SPL loading and booting of Legacy images" + default y if !TI_SECURE_DEVICE + help + SPL will support loading and booting Legacy images when this option + is y. If this is not set, SPL will move on to other available + boot media to find a suitable image. + config SPL_SYS_MALLOC_SIMPLE bool depends on SPL diff --git a/common/spl/spl.c b/common/spl/spl.c index 766fb3d6f4..d98b9fcb9a 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -93,9 +93,10 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) int spl_parse_image_header(struct spl_image_info *spl_image, const struct image_header *header) { - u32 header_size = sizeof(struct image_header); - if (image_get_magic(header) == IH_MAGIC) { +#ifdef CONFIG_SPL_LEGACY_IMAGE_SUPPORT + u32 header_size = sizeof(struct image_header); + if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) { /* * On some system (e.g. powerpc), the load-address and @@ -118,6 +119,11 @@ int spl_parse_image_header(struct spl_image_info *spl_image, debug("spl: payload image: %.*s load addr: 0x%lx size: %d\n", (int)sizeof(spl_image->name), spl_image->name, spl_image->load_addr, spl_image->size); +#else + /* LEGACY image not supported */ + debug("Legacy boot image support not enabled, proceeding to other boot methods"); + return -EINVAL; +#endif } else { #ifdef CONFIG_SPL_PANIC_ON_RAW_IMAGE /* @@ -146,16 +152,18 @@ int spl_parse_image_header(struct spl_image_info *spl_image, } #endif -#ifdef CONFIG_SPL_ABORT_ON_RAW_IMAGE - /* Signature not found, proceed to other boot methods. */ - return -EINVAL; -#else +#ifdef CONFIG_SPL_RAW_IMAGE_SUPPORT /* Signature not found - assume u-boot.bin */ debug("mkimage signature not found - ih_magic = %x\n", header->ih_magic); spl_set_header_raw_uboot(spl_image); +#else + /* RAW image not supported, proceed to other boot methods. */ + debug("Raw boot image support not enabled, proceeding to other boot methods"); + return -EINVAL; #endif } + return 0; } @@ -170,22 +178,20 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) image_entry(); } -int spl_init(void) +static int spl_common_init(bool setup_malloc) { int ret; - debug("spl_init()\n"); -/* - * with CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN we set malloc_base and - * malloc_limit in spl_relocate_stack_gd - */ -#if defined(CONFIG_SYS_MALLOC_F_LEN) && \ - !defined(CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) + debug("spl_early_init()\n"); + +#if defined(CONFIG_SYS_MALLOC_F_LEN) + if (setup_malloc) { #ifdef CONFIG_MALLOC_F_ADDR - gd->malloc_base = CONFIG_MALLOC_F_ADDR; + gd->malloc_base = CONFIG_MALLOC_F_ADDR; #endif - gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN; - gd->malloc_ptr = 0; + gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN; + gd->malloc_ptr = 0; + } #endif if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { ret = fdtdec_setup(); @@ -202,6 +208,32 @@ int spl_init(void) return ret; } } + + return 0; +} + +int spl_early_init(void) +{ + int ret; + + ret = spl_common_init(true); + if (ret) + return ret; + gd->flags |= GD_FLG_SPL_EARLY_INIT; + + return 0; +} + +int spl_init(void) +{ + int ret; + + if (!(gd->flags & GD_FLG_SPL_EARLY_INIT)) { + ret = spl_common_init( + !IS_ENABLED(CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN)); + if (ret) + return ret; + } gd->flags |= GD_FLG_SPL_INIT; return 0; diff --git a/configs/CPCI2DP_defconfig b/configs/CPCI2DP_defconfig index cbecc3ed66..1787a8aa48 100644 --- a/configs/CPCI2DP_defconfig +++ b/configs/CPCI2DP_defconfig @@ -12,4 +12,5 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_NFS is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig index 09554960e9..1d1bcf235d 100644 --- a/configs/CPCI4052_defconfig +++ b/configs/CPCI4052_defconfig @@ -19,5 +19,6 @@ CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig index 61cc657420..d3742c7659 100644 --- a/configs/MIP405T_defconfig +++ b/configs/MIP405T_defconfig @@ -22,6 +22,7 @@ CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_CONSOLE_EXTRA_INFO=y CONFIG_VIDEO_CT69000=y diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig index 86c1bde0ff..f828b58783 100644 --- a/configs/MIP405_defconfig +++ b/configs/MIP405_defconfig @@ -23,6 +23,7 @@ CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig index 1e2e28553b..d8262ebf0b 100644 --- a/configs/PATI_defconfig +++ b/configs/PATI_defconfig @@ -22,3 +22,4 @@ CONFIG_SYS_PROMPT="pati=> " # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set +CONFIG_BAUDRATE=9600 diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig index b35f605a7a..1d02b9d07d 100644 --- a/configs/PIP405_defconfig +++ b/configs/PIP405_defconfig @@ -23,6 +23,7 @@ CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig index 90afe64d40..652edcdc70 100644 --- a/configs/PLU405_defconfig +++ b/configs/PLU405_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_UBI=y CONFIG_MAC_PARTITION=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig index f2e04af810..d0777ca9fb 100644 --- a/configs/VOM405_defconfig +++ b/configs/VOM405_defconfig @@ -14,5 +14,6 @@ CONFIG_CMD_PING=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set +CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig index 01033f2e8b..25a06cf7a5 100644 --- a/configs/a4m072_defconfig +++ b/configs/a4m072_defconfig @@ -18,6 +18,7 @@ CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=9600 CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig index 5b7885ebd6..d55f658951 100644 --- a/configs/adp-ag101p_defconfig +++ b/configs/adp-ag101p_defconfig @@ -10,4 +10,5 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MMC=y CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 CONFIG_SYS_NS16550=y diff --git a/configs/alt_defconfig b/configs/alt_defconfig index bc310b495d..afbfb0d4a8 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -26,5 +26,6 @@ CONFIG_CMD_FAT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_BAUDRATE=38400 CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig index f82ca16d5a..cb61842613 100644 --- a/configs/am335x_evm_norboot_defconfig +++ b/configs/am335x_evm_norboot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_AM33XX=y CONFIG_TARGET_AM335X_EVM=y CONFIG_NOR=y diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig index 99c95c44bd..91cf89ae25 100644 --- a/configs/am3517_crane_defconfig +++ b/configs/am3517_crane_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y # CONFIG_SPL_GPIO_SUPPORT is not set CONFIG_TARGET_AM3517_CRANE=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 8d209810e5..1f2cd0785a 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y # CONFIG_SPL_GPIO_SUPPORT is not set CONFIG_TARGET_AM3517_EVM=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index a9c87264cb..83546ed30b 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_AM43XX=y CONFIG_TARGET_AM43XX_EVM=y CONFIG_ISW_ENTRY_ADDR=0x30000000 diff --git a/configs/ap325rxa_defconfig b/configs/ap325rxa_defconfig index 168f00cd78..fd30665753 100644 --- a/configs/ap325rxa_defconfig +++ b/configs/ap325rxa_defconfig @@ -21,4 +21,5 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_DOS_PARTITION=y CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig index 457d5270e5..b0e099549b 100644 --- a/configs/apalis_imx6_nospl_com_defconfig +++ b/configs/apalis_imx6_nospl_com_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_TARGET_APALIS_IMX6=y CONFIG_VIDEO=y diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig index bdd4a67825..231639e6bf 100644 --- a/configs/apalis_imx6_nospl_it_defconfig +++ b/configs/apalis_imx6_nospl_it_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_TARGET_APALIS_IMX6=y CONFIG_VIDEO=y diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig index b850efe5a7..4c16ec19fd 100644 --- a/configs/armadillo-800eva_defconfig +++ b/configs/armadillo-800eva_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_RMOBILE=y CONFIG_TARGET_ARMADILLO_800EVA=y CONFIG_BOOTDELAY=3 diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 8347f6ae89..14ec8a1f11 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig index fea8c3240f..8a6fb15f5c 100644 --- a/configs/bf537-minotaur_defconfig +++ b/configs/bf537-minotaur_defconfig @@ -13,3 +13,4 @@ CONFIG_CMD_CACHE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_BAUDRATE=57600 diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig index 744eb1c767..809a06c800 100644 --- a/configs/bf561-acvilon_defconfig +++ b/configs/bf561-acvilon_defconfig @@ -16,5 +16,6 @@ CONFIG_CMD_DNS=y CONFIG_CMD_CACHE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y +CONFIG_BAUDRATE=57600 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y CONFIG_LIB_RAND=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 37a92bc33a..173b222151 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_TARGET_BK4R1=y CONFIG_DEFAULT_DEVICE_TREE="bk4r1" diff --git a/configs/blackstamp_defconfig b/configs/blackstamp_defconfig index 7aa5a52f9b..6e66331eaf 100644 --- a/configs/blackstamp_defconfig +++ b/configs/blackstamp_defconfig @@ -10,3 +10,4 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_BAUDRATE=57600 diff --git a/configs/blackvme_defconfig b/configs/blackvme_defconfig index 7c3eb9dc6b..9ef304451d 100644 --- a/configs/blackvme_defconfig +++ b/configs/blackvme_defconfig @@ -11,3 +11,4 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_BAUDRATE=57600 diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index b53c285ba3..70da41d08c 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -24,3 +24,4 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_BAUDRATE=38400 diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index e33c96b810..85c21e572b 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -14,5 +14,6 @@ CONFIG_CMD_PING=y CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig index c212a88475..8b12a3aec2 100644 --- a/configs/cm5200_defconfig +++ b/configs/cm5200_defconfig @@ -19,6 +19,7 @@ CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set +CONFIG_BAUDRATE=57600 CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig index 1997e560cd..0357b9126b 100644 --- a/configs/cm_t3517_defconfig +++ b/configs/cm_t3517_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y CONFIG_TARGET_CM_T3517=y CONFIG_BOOTDELAY=3 diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig index 1983ac7c7b..6c12b28d52 100644 --- a/configs/cm_t35_defconfig +++ b/configs/cm_t35_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y CONFIG_TARGET_CM_T35=y CONFIG_BOOTDELAY=3 diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index e817f28848..7095c6d066 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_TARGET_CM_T43=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index efe80a9e97..21d0126a5d 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -9,3 +9,4 @@ CONFIG_SYS_PROMPT="COBRA > " # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=19200 diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig index 4a8beaf2e5..4539f2b24b 100644 --- a/configs/colibri_imx6_nospl_defconfig +++ b/configs/colibri_imx6_nospl_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_TARGET_COLIBRI_IMX6=y CONFIG_VIDEO=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index ce60056596..46f7bb242f 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX7=y CONFIG_TARGET_COLIBRI_IMX7=y CONFIG_IMX_RDC=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 9d94c61897..0474abc3c5 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_TARGET_COLIBRI_VF=y CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 743581802b..6b5096407e 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -36,3 +36,4 @@ CONFIG_USB_EHCI_MSM=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y +CONFIG_CMD_MD5SUM=y diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig index 29ee7a2895..ac37764cd2 100644 --- a/configs/eco5pk_defconfig +++ b/configs/eco5pk_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y CONFIG_TARGET_ECO5PK=y CONFIG_FIT=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index a0cc7a715f..aad2533998 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -41,8 +41,11 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -# CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_ROCKCHIP_RK3288_PINCTRL=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig new file mode 100644 index 0000000000..a9304fe039 --- /dev/null +++ b/configs/evb-rk3328_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_ROCKCHIP_RK3328_PINCTRL=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index ad51ed21dd..bedc1fd31d 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -3,7 +3,16 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_ROCKCHIP_RK3399=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_OF_LIBFDT=y +CONFIG_SPL_ATF_SUPPORT=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 +CONFIG_SPL_ATF_TEXT_BASE=0x00010000 # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_GPT=y @@ -12,20 +21,29 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y +CONFIG_CMD_PXE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_MMC_DW=y -CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_ROCKCHIP_RK3399_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index a42cd9cb93..d1b0ffc467 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y @@ -40,8 +41,11 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -# CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_ROCKCHIP_RK3288_PINCTRL=y @@ -58,6 +62,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 00bfca032a..b0741d7bd9 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -16,6 +16,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y @@ -28,7 +29,6 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y @@ -65,6 +65,8 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 57ad2d7b03..4878203747 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -26,5 +26,6 @@ CONFIG_CMD_FAT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_BAUDRATE=38400 CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig index 6dc0d322dc..362698b63f 100644 --- a/configs/gr_cpci_ax2000_defconfig +++ b/configs/gr_cpci_ax2000_defconfig @@ -7,3 +7,4 @@ CONFIG_BOOTDELAY=5 # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig index 6b635e7810..c3ac42fc84 100644 --- a/configs/gr_ep2s60_defconfig +++ b/configs/gr_ep2s60_defconfig @@ -7,3 +7,4 @@ CONFIG_BOOTDELAY=5 # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig index 9f1d6a8123..ecf0886f1e 100644 --- a/configs/gr_xc3s_1500_defconfig +++ b/configs/gr_xc3s_1500_defconfig @@ -7,3 +7,4 @@ CONFIG_BOOTDELAY=5 # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig index 6cbbbe41fe..0d6ab4a925 100644 --- a/configs/grsim_defconfig +++ b/configs/grsim_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=5 # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP=y +CONFIG_BAUDRATE=38400 CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_APBUART=y CONFIG_DEBUG_UART_BASE=0x80000100 diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig index 75336a10fc..287584001b 100644 --- a/configs/grsim_leon2_defconfig +++ b/configs/grsim_leon2_defconfig @@ -15,3 +15,4 @@ CONFIG_BOOTDELAY=5 # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_BAUDRATE=38400 diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index 20801fc352..041d04817f 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_HIGHBANK=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig index a330f1af36..cace5adcb2 100644 --- a/configs/integratorap_cm720t_defconfig +++ b/configs/integratorap_cm720t_defconfig @@ -11,4 +11,5 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig index f81110732a..a1639ada33 100644 --- a/configs/integratorap_cm920t_defconfig +++ b/configs/integratorap_cm920t_defconfig @@ -11,4 +11,5 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig index fdb20d195d..f288dc88e2 100644 --- a/configs/integratorap_cm926ejs_defconfig +++ b/configs/integratorap_cm926ejs_defconfig @@ -11,4 +11,5 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig index 787187275a..c13af27def 100644 --- a/configs/integratorap_cm946es_defconfig +++ b/configs/integratorap_cm946es_defconfig @@ -11,4 +11,5 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig index cf67250ea7..1536005ce5 100644 --- a/configs/integratorcp_cm1136_defconfig +++ b/configs/integratorcp_cm1136_defconfig @@ -10,4 +10,5 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig index 3cc14aae31..4e43b4f04e 100644 --- a/configs/integratorcp_cm920t_defconfig +++ b/configs/integratorcp_cm920t_defconfig @@ -10,4 +10,5 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig index eb9b51473b..037cd4dc61 100644 --- a/configs/integratorcp_cm926ejs_defconfig +++ b/configs/integratorcp_cm926ejs_defconfig @@ -10,4 +10,5 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig index ba4c87661a..b19162f984 100644 --- a/configs/integratorcp_cm946es_defconfig +++ b/configs/integratorcp_cm946es_defconfig @@ -10,4 +10,5 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index b57426f8b3..6df0e25e37 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -26,5 +26,6 @@ CONFIG_CMD_FAT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_BAUDRATE=38400 CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig index 29d4298aa2..bc3e5d9091 100644 --- a/configs/kzm9g_defconfig +++ b/configs/kzm9g_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_RMOBILE=y CONFIG_TARGET_KZM9G=y CONFIG_BOOTDELAY=3 diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 143fdfb48b..040efc0939 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -26,5 +26,6 @@ CONFIG_CMD_FAT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_BAUDRATE=38400 CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig index aecbfdaab2..fa619dea05 100644 --- a/configs/mcx_defconfig +++ b/configs/mcx_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y # CONFIG_SPL_GPIO_SUPPORT is not set CONFIG_TARGET_MCX=y diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig index e207faa5da..c233e9ea1a 100644 --- a/configs/mecp5123_defconfig +++ b/configs/mecp5123_defconfig @@ -15,4 +15,5 @@ CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set +CONFIG_BAUDRATE=9600 CONFIG_OF_LIBFDT=y diff --git a/configs/ms7750se_defconfig b/configs/ms7750se_defconfig index d18640c78a..88bbb12003 100644 --- a/configs/ms7750se_defconfig +++ b/configs/ms7750se_defconfig @@ -22,4 +22,5 @@ CONFIG_BOOTDELAY=-1 # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index cfa00d426e..c6aad14557 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y CONFIG_TARGET_MT_VENTOUX=y CONFIG_VIDEO=y diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 0b8fccf74a..181bdb1170 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y CONFIG_TARGET_NOKIA_RX51=y CONFIG_VIDEO=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 573ae806a6..915a14271a 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_EVM=y CONFIG_BOOTDELAY=3 diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig index 5be1139452..c4ff1369ee 100644 --- a/configs/omap3_ha_defconfig +++ b/configs/omap3_ha_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y CONFIG_TARGET_TAO3530=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA" diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 067ddbc5cc..2abf3ab6a1 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_KIRKWOOD=y CONFIG_TARGET_OPENRD=y CONFIG_IDENT_STRING="\nOpenRD-Base" diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index b90ead158f..8b3f25fd95 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_KIRKWOOD=y CONFIG_TARGET_OPENRD=y CONFIG_IDENT_STRING="\nOpenRD-Client" diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 2bc8ace8d0..ba774738fc 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_KIRKWOOD=y CONFIG_TARGET_OPENRD=y CONFIG_IDENT_STRING="\nOpenRD-Ultimate" diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index b925aac022..356268f65f 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_TARGET_PCM052=y CONFIG_DEFAULT_DEVICE_TREE="pcm052" diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 7b5ed94c34..dfc84b9a83 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -41,6 +41,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 433b6adcfb..0f7f97f9a8 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -26,5 +26,6 @@ CONFIG_CMD_FAT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_BAUDRATE=38400 CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 01f6f5d5c6..7f3f5ac809 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MD5SUM=y CONFIG_LOOPW=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MX_CYCLIC=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index 10e12bf50e..3f8e70d523 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MD5SUM=y CONFIG_LOOPW=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MX_CYCLIC=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 281e441425..ade67143b1 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MD5SUM=y CONFIG_LOOPW=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MX_CYCLIC=y diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig index ace75531fe..224b55bc90 100644 --- a/configs/sh7752evb_defconfig +++ b/configs/sh7752evb_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_EXT2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_MMC=y +CONFIG_CMD_MD5SUM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig index 48e3d552b0..7bf886290d 100644 --- a/configs/sh7753evb_defconfig +++ b/configs/sh7753evb_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_EXT2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_MMC=y +CONFIG_CMD_MD5SUM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig index dc6f4e11b2..00870ac720 100644 --- a/configs/sh7757lcr_defconfig +++ b/configs/sh7757lcr_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_EXT2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_MMC=y +CONFIG_CMD_MD5SUM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 6be29454db..eeba8192ff 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -26,5 +26,6 @@ CONFIG_CMD_FAT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_BAUDRATE=38400 CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 2e43c41b21..48c8781ead 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index b67ff8862d..ca2762ad86 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y CONFIG_TARGET_SNIPER=y # CONFIG_SPL_NAND_SUPPORT is not set diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 7702f49a71..135dfac12c 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_YMODEM_SUPPORT=y diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index f638ca0924..b5457c6a24 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -39,3 +39,7 @@ CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set +CONFIG_CLK=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_PINCTRL_STM32=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 9b03eb3d3c..9646ec7162 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -26,5 +26,6 @@ CONFIG_CMD_FAT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_BAUDRATE=38400 CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig index 7140ae5847..8f12a99c73 100644 --- a/configs/tao3530_defconfig +++ b/configs/tao3530_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y CONFIG_TARGET_TAO3530=y CONFIG_BOOTDELAY=3 diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index aa9eefa402..2de9cad688 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 95a23d8250..9ba16090b2 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_TARGET_TBS2910=y CONFIG_PRE_CONSOLE_BUFFER=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 7573a2ec6d..cec39384b3 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y @@ -40,6 +41,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set @@ -57,6 +62,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/twister_defconfig b/configs/twister_defconfig index fefd4901a2..9928d0e68d 100644 --- a/configs/twister_defconfig +++ b/configs/twister_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SYS_THUMB_BUILD is not set CONFIG_OMAP34XX=y CONFIG_TARGET_TWISTER=y CONFIG_FIT=y diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig index b6c2843106..ba489ea1d1 100644 --- a/configs/vexpress_ca15_tc2_defconfig +++ b/configs/vexpress_ca15_tc2_defconfig @@ -19,4 +19,5 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig index d17cb36b0b..fb671419c5 100644 --- a/configs/vexpress_ca5x2_defconfig +++ b/configs/vexpress_ca5x2_defconfig @@ -18,4 +18,5 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index c20f7178dd..7b845c6c79 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -18,4 +18,5 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index baa7ecc579..dcbf27ac9d 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -11,5 +11,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig index 86f6fea401..a72c3d4ee7 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_TARGET_X600=y diff --git a/disk/part_efi.c b/disk/part_efi.c index 893cbbdbda..db0c890d5b 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -463,7 +463,7 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, str_uuid = partitions[i].uuid; bin_uuid = gpt_e[i].unique_partition_guid.b; - if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_STD)) { + if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_GUID)) { printf("Partition no. %d: invalid guid: %s\n", i, str_uuid); return -1; diff --git a/doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt new file mode 100644 index 0000000000..a15dc5d1f8 --- /dev/null +++ b/doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt @@ -0,0 +1,42 @@ +Rockchip Dynamic Memory Controller Driver +Required properties: +- compatible: "rockchip,rk3399-dmc", "syscon" +- rockchip,cru: this driver should access cru regs, so need get cru here +- rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here +- rockchip,pmugrf: this driver should access pmugrf regs, so need get pmugrf here +- rockchip,pmusgrf: this driver should access pmusgrf regs, so need get pmusgrf here +- rockchip,cic: this driver should access cic regs, so need get cic here +- reg: dynamic ram protocol controller(PCTL) address, PHY Independent(PI) address, phy controller(PHYCTL) address and memory schedule(MSCH) address +- clock: must include clock specifiers corresponding to entries in the clock-names property. + Must contain + dmc_clk: for ddr working frequency +- rockchip,sdram-params: SDRAM parameters, including all the information by ddr driver: + Must contain + Genarate by vendor tool and adjust for U-Boot dtsi. + +Example: + dmc: dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + reg = <0x0 0xffa80000 0x0 0x0800 + 0x0 0xffa80800 0x0 0x1800 + 0x0 0xffa82000 0x0 0x2000 + 0x0 0xffa84000 0x0 0x1000 + 0x0 0xffa88000 0x0 0x0800 + 0x0 0xffa88800 0x0 0x1800 + 0x0 0xffa8a000 0x0 0x2000 + 0x0 0xffa8c000 0x0 0x1000>; + }; + + &dmc { + rockchip,sdram-params = < + 0x2 + 0xa + 0x3 + ... + >; + }; diff --git a/doc/device-tree-bindings/clock/st,stm32-rcc.txt b/doc/device-tree-bindings/clock/st,stm32-rcc.txt new file mode 100644 index 0000000000..0532d815da --- /dev/null +++ b/doc/device-tree-bindings/clock/st,stm32-rcc.txt @@ -0,0 +1,95 @@ +STMicroelectronics STM32 Reset and Clock Controller +=================================================== + +The RCC IP is both a reset and a clock controller. + +Please refer to clock-bindings.txt for common clock controller binding usage. +Please also refer to reset.txt for common reset controller binding usage. + +Required properties: +- compatible: Should be: + "st,stm32f42xx-rcc" + "st,stm32f469-rcc" +- reg: should be register base and length as documented in the + datasheet +- #reset-cells: 1, see below +- #clock-cells: 2, device nodes should specify the clock in their "clocks" + property, containing a phandle to the clock device node, an index selecting + between gated clocks and other clocks and an index specifying the clock to + use. + +Example: + + rcc: rcc@40023800 { + #reset-cells = <1>; + #clock-cells = <2> + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + }; + +Specifying gated clocks +======================= + +The primary index must be set to 0. + +The secondary index is the bit number within the RCC register bank, starting +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). + +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). + +To simplify the usage and to share bit definition with the reset and clock +drivers of the RCC IP, macros are available to generate the index in +human-readble format. + +For STM32F4 series, the macro are available here: + - include/dt-bindings/mfd/stm32f4-rcc.h + +Example: + + /* Gated clock, AHB1 bit 0 (GPIOA) */ + ... { + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)> + }; + + /* Gated clock, AHB2 bit 4 (CRYP) */ + ... { + clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)> + }; + +Specifying other clocks +======================= + +The primary index must be set to 1. + +The secondary index is bound with the following magic numbers: + + 0 SYSTICK + 1 FCLK + +Example: + + /* Misc clock, FCLK */ + ... { + clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)> + }; + + +Specifying softreset control of devices +======================================= + +Device nodes should specify the reset channel required in their "resets" +property, containing a phandle to the reset device node and an index specifying +which channel to use. +The index is the bit number within the RCC registers bank, starting from RCC +base address. +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register. +For example, for CRC reset: + crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 + +example: + + timer2 { + resets = <&rcc STM32F4_APB1_RESET(TIM2)>; + }; diff --git a/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt b/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt new file mode 100644 index 0000000000..c41ae91f7a --- /dev/null +++ b/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt @@ -0,0 +1,133 @@ +* STM32 GPIO and Pin Mux/Config controller + +STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware +controller. It controls the input/output settings on the available pins and +also provides ability to multiplex and configure the output of various on-chip +controllers onto these pads. + +Pin controller node: +Required properies: + - compatible: value should be one of the following: + (a) "st,stm32f429-pinctrl" + (b) "st,stm32f746-pinctrl" + - #address-cells: The value of this property must be 1 + - #size-cells : The value of this property must be 1 + - ranges : defines mapping between pin controller node (parent) to + gpio-bank node (children). + - pins-are-numbered: Specify the subnodes are using numbered pinmux to + specify pins. + +GPIO controller/bank node: +Required properties: + - gpio-controller : Indicates this device is a GPIO controller + - #gpio-cells : Should be two. + The first cell is the pin number + The second one is the polarity: + - 0 for active high + - 1 for active low + - reg : The gpio address range, relative to the pinctrl range + - clocks : clock that drives this bank + - st,bank-name : Should be a name string for this bank as specified in + the datasheet + +Optional properties: + - reset: : Reference to the reset controller + - interrupt-parent: phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node + which includes IRQ mux selection register, and the offset of the IRQ mux + selection register. + +Example: +#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +... + + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOA"; + }; + ... + pin-functions nodes follow... + }; + +Contents of function subnode node: +---------------------------------- +Subnode format +A pinctrl node should contain at least one subnode representing the +pinctrl group available on the machine. Each subnode will list the +pins it needs, and how they should be configured, with regard to muxer +configuration, pullups, drive, output high/low and output speed. + + node { + pinmux = <PIN_NUMBER_PINMUX>; + GENERIC_PINCONFIG; + }; + +Required properties: +- pinmux: integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined in + dt-bindings/pinctrl/<soc>-pinfunc.h directly. + These defines are calculated as: + ((port * 16 + line) << 8) | function + With: + - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) + - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) + - function: The function number, can be: + * 0 : GPIO IN + * 1 : Alternate Function 0 + * 2 : Alternate Function 1 + * 3 : Alternate Function 2 + * ... + * 16 : Alternate Function 15 + * 17 : Analog + * 18 : GPIO OUT + +Optional properties: +- GENERIC_PINCONFIG: is the generic pinconfig options to use. + Available options are: + - bias-disable, + - bias-pull-down, + - bias-pull-up, + - drive-push-pull, + - drive-open-drain, + - output-low + - output-high + - slew-rate = <x>, with x being: + < 0 > : Low speed + < 1 > : Medium speed + < 2 > : Fast speed + < 3 > : High speed + +Example: + +pin-controller { +... + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt index fea324e25e..0853477578 100644 --- a/doc/driver-model/README.txt +++ b/doc/driver-model/README.txt @@ -825,6 +825,10 @@ drivers marked with DM_FLAG_PRE_RELOC or the device tree 'u-boot,dm-pre-reloc' flag are initialised prior to relocation. This helps to reduce the driver model overhead. +It is possible to limit this to specific relocation steps, by using +the more specialized 'u-boot,dm-spl' and 'u-boot,dm-tpl' flags +in the devicetree. + Then post relocation we throw that away and re-init driver model again. For drivers which require some sort of continuity between pre- and post-relocation devices, we can provide access to the pre-relocation diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 335ef9e1d7..5ca958c007 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -28,6 +28,14 @@ config CLK_BOSTON help Enable this to support the clocks +config CLK_ZYNQ + bool "Enable clock driver support for Zynq" + depends on CLK && ARCH_ZYNQ + default y + help + This clock driver adds support for clock realted settings for + Zynq platform. + config CLK_ZYNQMP bool "Enable clock driver support for ZynqMP" depends on ARCH_ZYNQMP diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 884c21c68b..01a8cd641e 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o +obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o obj-y += tegra/ @@ -17,5 +18,5 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o - obj-$(CONFIG_ARCH_ASPEED) += aspeed/ +obj-$(CONFIG_STM32F7) += clk_stm32f7.o diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index c73156a0df..fcd693a2f6 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -10,6 +10,7 @@ #include <dm/device.h> #include <dm/lists.h> #include <dm/root.h> +#include <dm/util.h> #include "pmc.h" DECLARE_GLOBAL_DATA_PTR; @@ -56,7 +57,7 @@ int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name) offset > 0; offset = fdt_next_subnode(fdt, offset)) { if (pre_reloc_only && - !fdt_getprop(fdt, offset, "u-boot,dm-pre-reloc", NULL)) + !dm_fdt_pre_reloc(fdt, offset)) continue; /* * If this node has "compatible" property, this is not diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/drivers/clk/clk_stm32f7.c index e1ee1731f7..0d86395d47 100644 --- a/arch/arm/mach-stm32/stm32f7/clock.c +++ b/drivers/clk/clk_stm32f7.c @@ -1,11 +1,12 @@ /* - * (C) Copyright 2016 + * (C) Copyright 2017 * Vikas Manocha, <vikas.manocha@st.com> * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> +#include <clk-uclass.h> +#include <dm.h> #include <asm/io.h> #include <asm/arch/rcc.h> #include <asm/arch/stm32.h> @@ -212,13 +213,21 @@ unsigned long clock_get(enum clock clck) } } +static int stm32_clk_enable(struct clk *clk) +{ + u32 offset = clk->id / 32; + u32 bit_index = clk->id % 32; + + debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", + __func__, clk->id, offset, bit_index); + setbits_le32(&STM32_RCC->ahb1enr + offset, BIT(bit_index)); + + return 0; +} void clock_setup(int peripheral) { switch (peripheral) { - case USART1_CLOCK_CFG: - setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_USART1EN); - break; case GPIO_A_CLOCK_CFG: setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN); break; @@ -273,3 +282,48 @@ void clock_setup(int peripheral) break; } } + +static int stm32_clk_probe(struct udevice *dev) +{ + debug("%s: stm32_clk_probe\n", __func__); + configure_clocks(); + + return 0; +} + +static int stm32_clk_of_xlate(struct clk *clk, + struct fdtdec_phandle_args *args) +{ + debug("%s(clk=%p)\n", __func__, clk); + + if (args->args_count != 2) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args_count) + clk->id = args->args[1]; + else + clk->id = 0; + + return 0; +} + +static struct clk_ops stm32_clk_ops = { + .of_xlate = stm32_clk_of_xlate, + .enable = stm32_clk_enable, +}; + +static const struct udevice_id stm32_clk_ids[] = { + { .compatible = "st,stm32f42xx-rcc"}, + {} +}; + +U_BOOT_DRIVER(stm32f7_clk) = { + .name = "stm32f7_clk", + .id = UCLASS_CLK, + .of_match = stm32_clk_ids, + .ops = &stm32_clk_ops, + .probe = stm32_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c new file mode 100644 index 0000000000..6edc4dc6ca --- /dev/null +++ b/drivers/clk/clk_zynq.c @@ -0,0 +1,488 @@ +/* + * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG + * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> + * + * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com> + * Copyright (C) 2013 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/clk.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> + +/* Register bitfield defines */ +#define PLLCTRL_FBDIV_MASK 0x7f000 +#define PLLCTRL_FBDIV_SHIFT 12 +#define PLLCTRL_BPFORCE_MASK (1 << 4) +#define PLLCTRL_PWRDWN_MASK 2 +#define PLLCTRL_PWRDWN_SHIFT 1 +#define PLLCTRL_RESET_MASK 1 +#define PLLCTRL_RESET_SHIFT 0 + +#define ZYNQ_CLK_MAXDIV 0x3f +#define CLK_CTRL_DIV1_SHIFT 20 +#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT) +#define CLK_CTRL_DIV0_SHIFT 8 +#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) +#define CLK_CTRL_SRCSEL_SHIFT 4 +#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT) + +#define CLK_CTRL_DIV2X_SHIFT 26 +#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT) +#define CLK_CTRL_DIV3X_SHIFT 20 +#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT) + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SPL_BUILD +enum zynq_clk_rclk {mio_clk, emio_clk}; +#endif + +struct zynq_clk_priv { + ulong ps_clk_freq; +#ifndef CONFIG_SPL_BUILD + struct clk gem_emio_clk[2]; +#endif +}; + +static void *zynq_clk_get_register(enum zynq_clk id) +{ + switch (id) { + case armpll_clk: + return &slcr_base->arm_pll_ctrl; + case ddrpll_clk: + return &slcr_base->ddr_pll_ctrl; + case iopll_clk: + return &slcr_base->io_pll_ctrl; + case lqspi_clk: + return &slcr_base->lqspi_clk_ctrl; + case smc_clk: + return &slcr_base->smc_clk_ctrl; + case pcap_clk: + return &slcr_base->pcap_clk_ctrl; + case sdio0_clk ... sdio1_clk: + return &slcr_base->sdio_clk_ctrl; + case uart0_clk ... uart1_clk: + return &slcr_base->uart_clk_ctrl; + case spi0_clk ... spi1_clk: + return &slcr_base->spi_clk_ctrl; +#ifndef CONFIG_SPL_BUILD + case dci_clk: + return &slcr_base->dci_clk_ctrl; + case gem0_clk: + return &slcr_base->gem0_clk_ctrl; + case gem1_clk: + return &slcr_base->gem1_clk_ctrl; + case fclk0_clk: + return &slcr_base->fpga0_clk_ctrl; + case fclk1_clk: + return &slcr_base->fpga1_clk_ctrl; + case fclk2_clk: + return &slcr_base->fpga2_clk_ctrl; + case fclk3_clk: + return &slcr_base->fpga3_clk_ctrl; + case can0_clk ... can1_clk: + return &slcr_base->can_clk_ctrl; + case dbg_trc_clk ... dbg_apb_clk: + /* fall through */ +#endif + default: + return &slcr_base->dbg_clk_ctrl; + } +} + +static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl) +{ + u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + + switch (srcsel) { + case 2: + return ddrpll_clk; + case 3: + return iopll_clk; + case 0 ... 1: + default: + return armpll_clk; + } +} + +static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl) +{ + u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + + switch (srcsel) { + case 2: + return armpll_clk; + case 3: + return ddrpll_clk; + case 0 ... 1: + default: + return iopll_clk; + } +} + +static ulong zynq_clk_get_pll_rate(struct zynq_clk_priv *priv, enum zynq_clk id) +{ + u32 clk_ctrl, reset, pwrdwn, mul, bypass; + + clk_ctrl = readl(zynq_clk_get_register(id)); + + reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; + pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT; + if (reset || pwrdwn) + return 0; + + bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK; + if (bypass) + mul = 1; + else + mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; + + return priv->ps_clk_freq * mul; +} + +#ifndef CONFIG_SPL_BUILD +static enum zynq_clk_rclk zynq_clk_get_gem_rclk(enum zynq_clk id) +{ + u32 clk_ctrl, srcsel; + + if (id == gem0_clk) + clk_ctrl = readl(&slcr_base->gem0_rclk_ctrl); + else + clk_ctrl = readl(&slcr_base->gem1_rclk_ctrl); + + srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + if (srcsel) + return emio_clk; + else + return mio_clk; +} +#endif + +static ulong zynq_clk_get_cpu_rate(struct zynq_clk_priv *priv, enum zynq_clk id) +{ + u32 clk_621, clk_ctrl, div; + enum zynq_clk pll; + + clk_ctrl = readl(&slcr_base->arm_clk_ctrl); + + div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + + switch (id) { + case cpu_1x_clk: + div *= 2; + /* fall through */ + case cpu_2x_clk: + clk_621 = readl(&slcr_base->clk_621_true) & 1; + div *= 2 + clk_621; + break; + case cpu_3or2x_clk: + div *= 2; + /* fall through */ + case cpu_6or4x_clk: + break; + default: + return 0; + } + + pll = zynq_clk_get_cpu_pll(clk_ctrl); + + return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, pll), div); +} + +#ifndef CONFIG_SPL_BUILD +static ulong zynq_clk_get_ddr2x_rate(struct zynq_clk_priv *priv) +{ + u32 clk_ctrl, div; + + clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); + + div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT; + + return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div); +} +#endif + +static ulong zynq_clk_get_ddr3x_rate(struct zynq_clk_priv *priv) +{ + u32 clk_ctrl, div; + + clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); + + div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT; + + return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div); +} + +#ifndef CONFIG_SPL_BUILD +static ulong zynq_clk_get_dci_rate(struct zynq_clk_priv *priv) +{ + u32 clk_ctrl, div0, div1; + + clk_ctrl = readl(&slcr_base->dci_clk_ctrl); + + div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; + + return DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST( + zynq_clk_get_pll_rate(priv, ddrpll_clk), div0), div1); +} +#endif + +static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv, + enum zynq_clk id, bool two_divs) +{ + enum zynq_clk pll; + u32 clk_ctrl, div0; + u32 div1 = 1; + + clk_ctrl = readl(zynq_clk_get_register(id)); + + div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + if (!div0) + div0 = 1; + +#ifndef CONFIG_SPL_BUILD + if (two_divs) { + div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; + if (!div1) + div1 = 1; + } +#endif + + pll = zynq_clk_get_peripheral_pll(clk_ctrl); + + return + DIV_ROUND_CLOSEST( + DIV_ROUND_CLOSEST( + zynq_clk_get_pll_rate(priv, pll), div0), + div1); +} + +#ifndef CONFIG_SPL_BUILD +static ulong zynq_clk_get_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id) +{ + struct clk *parent; + + if (zynq_clk_get_gem_rclk(id) == mio_clk) + return zynq_clk_get_peripheral_rate(priv, id, true); + + parent = &priv->gem_emio_clk[id - gem0_clk]; + if (parent->dev) + return clk_get_rate(parent); + + debug("%s: gem%d emio rx clock source unknown\n", __func__, + id - gem0_clk); + + return -ENOSYS; +} + +static unsigned long zynq_clk_calc_peripheral_two_divs(ulong rate, + ulong pll_rate, + u32 *div0, u32 *div1) +{ + long new_err, best_err = (long)(~0UL >> 1); + ulong new_rate, best_rate = 0; + u32 d0, d1; + + for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) { + for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) { + new_rate = DIV_ROUND_CLOSEST( + DIV_ROUND_CLOSEST(pll_rate, d0), d1); + new_err = abs(new_rate - rate); + + if (new_err < best_err) { + *div0 = d0; + *div1 = d1; + best_err = new_err; + best_rate = new_rate; + } + } + } + + return best_rate; +} + +static ulong zynq_clk_set_peripheral_rate(struct zynq_clk_priv *priv, + enum zynq_clk id, ulong rate, + bool two_divs) +{ + enum zynq_clk pll; + u32 clk_ctrl, div0 = 0, div1 = 0; + ulong pll_rate, new_rate; + u32 *reg; + + reg = zynq_clk_get_register(id); + clk_ctrl = readl(reg); + + pll = zynq_clk_get_peripheral_pll(clk_ctrl); + pll_rate = zynq_clk_get_pll_rate(priv, pll); + clk_ctrl &= ~CLK_CTRL_DIV0_MASK; + if (two_divs) { + clk_ctrl &= ~CLK_CTRL_DIV1_MASK; + new_rate = zynq_clk_calc_peripheral_two_divs(rate, pll_rate, + &div0, &div1); + clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; + } else { + div0 = DIV_ROUND_CLOSEST(pll_rate, rate); + if (div0 > ZYNQ_CLK_MAXDIV) + div0 = ZYNQ_CLK_MAXDIV; + new_rate = DIV_ROUND_CLOSEST(rate, div0); + } + clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; + + zynq_slcr_unlock(); + writel(clk_ctrl, reg); + zynq_slcr_lock(); + + return new_rate; +} + +static ulong zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id, + ulong rate) +{ + struct clk *parent; + + if (zynq_clk_get_gem_rclk(id) == mio_clk) + return zynq_clk_set_peripheral_rate(priv, id, rate, true); + + parent = &priv->gem_emio_clk[id - gem0_clk]; + if (parent->dev) + return clk_set_rate(parent, rate); + + debug("%s: gem%d emio rx clock source unknown\n", __func__, + id - gem0_clk); + + return -ENOSYS; +} +#endif + +#ifndef CONFIG_SPL_BUILD +static ulong zynq_clk_get_rate(struct clk *clk) +{ + struct zynq_clk_priv *priv = dev_get_priv(clk->dev); + enum zynq_clk id = clk->id; + bool two_divs = false; + + switch (id) { + case armpll_clk ... iopll_clk: + return zynq_clk_get_pll_rate(priv, id); + case cpu_6or4x_clk ... cpu_1x_clk: + return zynq_clk_get_cpu_rate(priv, id); + case ddr2x_clk: + return zynq_clk_get_ddr2x_rate(priv); + case ddr3x_clk: + return zynq_clk_get_ddr3x_rate(priv); + case dci_clk: + return zynq_clk_get_dci_rate(priv); + case gem0_clk ... gem1_clk: + return zynq_clk_get_gem_rate(priv, id); + case fclk0_clk ... can1_clk: + two_divs = true; + /* fall through */ + case dbg_trc_clk ... dbg_apb_clk: + case lqspi_clk ... pcap_clk: + case sdio0_clk ... spi1_clk: + return zynq_clk_get_peripheral_rate(priv, id, two_divs); + case dma_clk: + return zynq_clk_get_cpu_rate(priv, cpu_2x_clk); + case usb0_aper_clk ... smc_aper_clk: + return zynq_clk_get_cpu_rate(priv, cpu_1x_clk); + default: + return -ENXIO; + } +} + +static ulong zynq_clk_set_rate(struct clk *clk, ulong rate) +{ + struct zynq_clk_priv *priv = dev_get_priv(clk->dev); + enum zynq_clk id = clk->id; + bool two_divs = false; + + switch (id) { + case gem0_clk ... gem1_clk: + return zynq_clk_set_gem_rate(priv, id, rate); + case fclk0_clk ... can1_clk: + two_divs = true; + /* fall through */ + case lqspi_clk ... pcap_clk: + case sdio0_clk ... spi1_clk: + case dbg_trc_clk ... dbg_apb_clk: + return zynq_clk_set_peripheral_rate(priv, id, rate, two_divs); + default: + return -ENXIO; + } +} +#else +static ulong zynq_clk_get_rate(struct clk *clk) +{ + struct zynq_clk_priv *priv = dev_get_priv(clk->dev); + enum zynq_clk id = clk->id; + + switch (id) { + case cpu_6or4x_clk ... cpu_1x_clk: + return zynq_clk_get_cpu_rate(priv, id); + case ddr3x_clk: + return zynq_clk_get_ddr3x_rate(priv); + case lqspi_clk ... pcap_clk: + case sdio0_clk ... spi1_clk: + return zynq_clk_get_peripheral_rate(priv, id, 0); + default: + return -ENXIO; + } +} +#endif + +static struct clk_ops zynq_clk_ops = { + .get_rate = zynq_clk_get_rate, +#ifndef CONFIG_SPL_BUILD + .set_rate = zynq_clk_set_rate, +#endif +}; + +static int zynq_clk_probe(struct udevice *dev) +{ + struct zynq_clk_priv *priv = dev_get_priv(dev); +#ifndef CONFIG_SPL_BUILD + unsigned int i; + char name[16]; + int ret; + + for (i = 0; i < 2; i++) { + sprintf(name, "gem%d_emio_clk", i); + ret = clk_get_by_name(dev, name, &priv->gem_emio_clk[i]); + if (ret < 0 && ret != -FDT_ERR_NOTFOUND) { + dev_err(dev, "failed to get %s clock\n", name); + return ret; + } + } +#endif + + priv->ps_clk_freq = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "ps-clk-frequency", 33333333UL); + + return 0; +} + +static const struct udevice_id zynq_clk_ids[] = { + { .compatible = "xlnx,ps7-clkc"}, + {} +}; + +U_BOOT_DRIVER(zynq_clk) = { + .name = "zynq_clk", + .id = UCLASS_CLK, + .of_match = zynq_clk_ids, + .flags = DM_FLAG_PRE_RELOC, + .ops = &zynq_clk_ops, + .priv_auto_alloc_size = sizeof(struct zynq_clk_priv), + .probe = zynq_clk_probe, +}; diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 1f8e41739d..1091a76f05 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -5,5 +5,7 @@ # obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c new file mode 100644 index 0000000000..459649f724 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -0,0 +1,527 @@ +/* + * (C) Copyright 2015 Google, Inc + * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dt-structs.h> +#include <errno.h> +#include <mapmem.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3188.h> +#include <asm/arch/grf_rk3188.h> +#include <asm/arch/hardware.h> +#include <dt-bindings/clock/rk3188-cru.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/uclass-internal.h> +#include <linux/log2.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum rk3188_clk_type { + RK3188_CRU, + RK3188A_CRU, +}; + +struct rk3188_clk_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3188_cru dtd; +#endif +}; + +struct pll_div { + u32 nr; + u32 nf; + u32 no; +}; + +enum { + VCO_MAX_HZ = 2200U * 1000000, + VCO_MIN_HZ = 440 * 1000000, + OUTPUT_MAX_HZ = 2200U * 1000000, + OUTPUT_MIN_HZ = 30 * 1000000, + FREF_MAX_HZ = 2200U * 1000000, + FREF_MIN_HZ = 30 * 1000, +}; + +enum { + /* PLL CON0 */ + PLL_OD_MASK = 0x0f, + + /* PLL CON1 */ + PLL_NF_MASK = 0x1fff, + + /* PLL CON2 */ + PLL_BWADJ_MASK = 0x0fff, + + /* PLL CON3 */ + PLL_RESET_SHIFT = 5, + + /* GRF_SOC_STATUS0 */ + SOCSTS_DPLL_LOCK = 1 << 5, + SOCSTS_APLL_LOCK = 1 << 6, + SOCSTS_CPLL_LOCK = 1 << 7, + SOCSTS_GPLL_LOCK = 1 << 8, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _nr, _no) {\ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* Keep divisors as low as possible to reduce jitter and power usage */ +#ifdef CONFIG_SPL_BUILD +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); +#endif + +static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div, bool has_bwadj) +{ + int pll_id = rk_pll_id(clk_id); + struct rk3188_pll *pll = &cru->pll[pll_id]; + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; + uint output_hz = vco_hz / div->no; + + debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", + (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && + (div->no == 1 || !(div->no % 2))); + + /* enter reset */ + rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); + + rk_clrsetreg(&pll->con0, + CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK, + ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); + rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); + + if (has_bwadj) + rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); + + udelay(10); + + /* return from reset */ + rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); + + return 0; +} + +static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, + unsigned int hz, bool has_bwadj) +{ + static const struct pll_div dpll_cfg[] = { + {.nf = 25, .nr = 2, .no = 1}, + {.nf = 400, .nr = 9, .no = 2}, + {.nf = 500, .nr = 9, .no = 2}, + {.nf = 100, .nr = 3, .no = 1}, + }; + int cfg; + + switch (hz) { + case 300000000: + cfg = 0; + break; + case 533000000: /* actually 533.3P MHz */ + cfg = 1; + break; + case 666000000: /* actually 666.6P MHz */ + cfg = 2; + break; + case 800000000: + cfg = 3; + break; + default: + debug("Unsupported SDRAM frequency"); + return -EINVAL; + } + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW << DPLL_MODE_SHIFT); + + rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); + + /* wait for pll lock */ + while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) + udelay(1); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); + + return 0; +} + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t nr, no, nf; + uint32_t con; + int pll_id = rk_pll_id(clk_id); + struct rk3188_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, + GPLL_MODE_SHIFT + }; + uint shift; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + switch ((con >> shift) & APLL_MODE_MASK) { + case APLL_MODE_SLOW: + return OSC_HZ; + case APLL_MODE_NORMAL: + /* normal mode */ + con = readl(&pll->con0); + no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; + nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; + con = readl(&pll->con1); + nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; + + return (24 * nf / (nr * no)) * 1000000; + case APLL_MODE_DEEP: + default: + return 32768; + } +} + +static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph) +{ + uint div; + u32 con; + + switch (periph) { + case HCLK_EMMC: + con = readl(&cru->cru_clksel_con[12]); + div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + break; + case HCLK_SDMMC: + con = readl(&cru->cru_clksel_con[11]); + div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + break; + case HCLK_SDIO: + con = readl(&cru->cru_clksel_con[12]); + div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK; + break; + default: + return -EINVAL; + } + + return DIV_TO_RATE(gclk_rate, div); +} + +static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph, uint freq) +{ + int src_clk_div; + + debug("%s: gclk_rate=%u\n", __func__, gclk_rate); + src_clk_div = RATE_TO_DIV(gclk_rate, freq); + assert(src_clk_div <= 0x3f); + + switch (periph) { + case HCLK_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_DIV_MASK << EMMC_DIV_SHIFT, + src_clk_div << EMMC_DIV_SHIFT); + break; + case HCLK_SDMMC: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_DIV_MASK << MMC0_DIV_SHIFT, + src_clk_div << MMC0_DIV_SHIFT); + break; + case HCLK_SDIO: + rk_clrsetreg(&cru->cru_clksel_con[12], + SDIO_DIV_MASK << SDIO_DIV_SHIFT, + src_clk_div << SDIO_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_mmc_get_clk(cru, gclk_rate, periph); +} + +static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph) +{ + uint div; + u32 con; + + switch (periph) { + case SCLK_SPI0: + con = readl(&cru->cru_clksel_con[25]); + div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK; + break; + case SCLK_SPI1: + con = readl(&cru->cru_clksel_con[25]); + div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK; + break; + default: + return -EINVAL; + } + + return DIV_TO_RATE(gclk_rate, div); +} + +static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph, uint freq) +{ + int src_clk_div = RATE_TO_DIV(gclk_rate, freq); + + switch (periph) { + case SCLK_SPI0: + assert(src_clk_div <= SPI0_DIV_MASK); + rk_clrsetreg(&cru->cru_clksel_con[25], + SPI0_DIV_MASK << SPI0_DIV_SHIFT, + src_clk_div << SPI0_DIV_SHIFT); + break; + case SCLK_SPI1: + assert(src_clk_div <= SPI1_DIV_MASK); + rk_clrsetreg(&cru->cru_clksel_con[25], + SPI1_DIV_MASK << SPI1_DIV_SHIFT, + src_clk_div << SPI1_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_spi_get_clk(cru, gclk_rate, periph); +} + +#ifdef CONFIG_SPL_BUILD +static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf, + bool has_bwadj) +{ + u32 aclk_div, hclk_div, pclk_div, h2p_div; + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | + CPLL_MODE_SLOW << CPLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj); + rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj); + + /* waiting for pll lock */ + while ((readl(&grf->soc_status0) & + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) + udelay(1); + + /* + * cpu clock pll source selection and + * reparent aclk_cpu_pre from apll to gpll + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ); + assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT | + A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT, + CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT | + aclk_div << A9_CPU_DIV_SHIFT); + + hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ); + assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3); + pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ); + assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4); + h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ); + assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[1], + AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT | + CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT | + CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT, + h2p_div << AHB2APB_DIV_SHIFT | + pclk_div << CPU_PCLK_DIV_SHIFT | + hclk_div << CPU_HCLK_DIV_SHIFT); + + /* + * peri clock pll source selection and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && (pclk_div < 0x4)); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | + PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | + PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | + CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); + + rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000); +} +#endif + +static ulong rk3188_clk_get_rate(struct clk *clk) +{ + struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate, gclk_rate; + + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); + switch (clk->id) { + case 1 ... 4: + new_rate = rkclk_pll_get_rate(priv->cru, clk->id); + break; + case HCLK_EMMC: + case HCLK_SDMMC: + case HCLK_SDIO: + new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, + clk->id); + break; + case SCLK_SPI0: + case SCLK_SPI1: + new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ, + clk->id); + break; + case PCLK_I2C0: + case PCLK_I2C1: + case PCLK_I2C2: + case PCLK_I2C3: + case PCLK_I2C4: + return gclk_rate; + default: + return -ENOENT; + } + + return new_rate; +} + +static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3188_cru *cru = priv->cru; + ulong new_rate; + + switch (clk->id) { + case CLK_DDR: + new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, + priv->has_bwadj); + break; + case HCLK_EMMC: + case HCLK_SDMMC: + case HCLK_SDIO: + new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, + clk->id, rate); + break; + case SCLK_SPI0: + case SCLK_SPI1: + new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ, + clk->id, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static struct clk_ops rk3188_clk_ops = { + .get_rate = rk3188_clk_get_rate, + .set_rate = rk3188_clk_set_rate, +}; + +static int rk3188_clk_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3188_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk3188_cru *)dev_get_addr(dev); +#endif + + return 0; +} + +static int rk3188_clk_probe(struct udevice *dev) +{ + struct rk3188_clk_priv *priv = dev_get_priv(dev); + enum rk3188_clk_type type = dev_get_driver_data(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->grf)) + return PTR_ERR(priv->grf); + priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0; + +#ifdef CONFIG_SPL_BUILD +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3188_clk_plat *plat = dev_get_platdata(dev); + + priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); +#endif + + rkclk_init(priv->cru, priv->grf, priv->has_bwadj); +#endif + + return 0; +} + +static int rk3188_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3188_sysreset", "reset", &dev); + if (ret) + debug("Warning: No rk3188 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rk3188_clk_ids[] = { + { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU }, + { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3188_cru) = { + .name = "rockchip_rk3188_cru", + .id = UCLASS_CLK, + .of_match = rk3188_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3188_clk_priv), + .platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat), + .ops = &rk3188_clk_ops, + .bind = rk3188_clk_bind, + .ofdata_to_platdata = rk3188_clk_ofdata_to_platdata, + .probe = rk3188_clk_probe, +}; diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index d15504c3aa..78356766a7 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -131,8 +131,10 @@ enum { /* Keep divisors as low as possible to reduce jitter and power usage */ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); +#ifdef CONFIG_SPL_BUILD static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); +#endif static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c new file mode 100644 index 0000000000..0ff1e30bb5 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -0,0 +1,581 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3328.h> +#include <asm/arch/hardware.h> +#include <asm/io.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rk3328-cru.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; + +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1); + +static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1); +static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1); + +static const struct pll_div *apll_cfgs[] = { + [APLL_816_MHZ] = &apll_816_cfg, + [APLL_600_MHZ] = &apll_600_cfg, +}; + +enum { + /* PLL_CON0 */ + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLL_CON1 */ + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_INTEGER_MODE = 1, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* PLL_CON2 */ + PLL_FRACDIV_SHIFT = 0, + PLL_FRACDIV_MASK = 0xffffff, + + /* MODE_CON */ + APLL_MODE_SHIFT = 0, + NPLL_MODE_SHIFT = 1, + DPLL_MODE_SHIFT = 4, + CPLL_MODE_SHIFT = 8, + GPLL_MODE_SHIFT = 12, + PLL_MODE_SLOW = 0, + PLL_MODE_NORM, + + /* CLKSEL_CON0 */ + CLK_CORE_PLL_SEL_APLL = 0, + CLK_CORE_PLL_SEL_GPLL, + CLK_CORE_PLL_SEL_DPLL, + CLK_CORE_PLL_SEL_NPLL, + CLK_CORE_PLL_SEL_SHIFT = 6, + CLK_CORE_PLL_SEL_MASK = 3 << CLK_CORE_PLL_SEL_SHIFT, + CLK_CORE_DIV_SHIFT = 0, + CLK_CORE_DIV_MASK = 0x1f, + + /* CLKSEL_CON1 */ + ACLKM_CORE_DIV_SHIFT = 4, + ACLKM_CORE_DIV_MASK = 0x7 << ACLKM_CORE_DIV_SHIFT, + PCLK_DBG_DIV_SHIFT = 0, + PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT, + + /* CLKSEL_CON28 */ + ACLK_PERIHP_PLL_SEL_CPLL = 0, + ACLK_PERIHP_PLL_SEL_GPLL, + ACLK_PERIHP_PLL_SEL_HDMIPHY, + ACLK_PERIHP_PLL_SEL_SHIFT = 6, + ACLK_PERIHP_PLL_SEL_MASK = 3 << ACLK_PERIHP_PLL_SEL_SHIFT, + ACLK_PERIHP_DIV_CON_SHIFT = 0, + ACLK_PERIHP_DIV_CON_MASK = 0x1f, + + /* CLKSEL_CON29 */ + PCLK_PERIHP_DIV_CON_SHIFT = 4, + PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, + HCLK_PERIHP_DIV_CON_SHIFT = 0, + HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, + + /* CLKSEL_CON22 */ + CLK_TSADC_DIV_CON_SHIFT = 0, + CLK_TSADC_DIV_CON_MASK = 0x3ff, + + /* CLKSEL_CON23 */ + CLK_SARADC_DIV_CON_SHIFT = 0, + CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT, + + /* CLKSEL_CON24 */ + CLK_PWM_PLL_SEL_CPLL = 0, + CLK_PWM_PLL_SEL_GPLL, + CLK_PWM_PLL_SEL_SHIFT = 15, + CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT, + CLK_PWM_DIV_CON_SHIFT = 8, + CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, + + CLK_SPI_PLL_SEL_CPLL = 0, + CLK_SPI_PLL_SEL_GPLL, + CLK_SPI_PLL_SEL_SHIFT = 7, + CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT, + CLK_SPI_DIV_CON_SHIFT = 0, + CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, + + /* CLKSEL_CON30 */ + CLK_SDMMC_PLL_SEL_CPLL = 0, + CLK_SDMMC_PLL_SEL_GPLL, + CLK_SDMMC_PLL_SEL_24M, + CLK_SDMMC_PLL_SEL_USBPHY, + CLK_SDMMC_PLL_SHIFT = 8, + CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT, + CLK_SDMMC_DIV_CON_SHIFT = 0, + CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT, + + /* CLKSEL_CON32 */ + CLK_EMMC_PLL_SEL_CPLL = 0, + CLK_EMMC_PLL_SEL_GPLL, + CLK_EMMC_PLL_SEL_24M, + CLK_EMMC_PLL_SEL_USBPHY, + CLK_EMMC_PLL_SHIFT = 8, + CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT, + CLK_EMMC_DIV_CON_SHIFT = 0, + CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT, + + /* CLKSEL_CON34 */ + CLK_I2C_PLL_SEL_CPLL = 0, + CLK_I2C_PLL_SEL_GPLL, + CLK_I2C_DIV_CON_MASK = 0x7f, + CLK_I2C_PLL_SEL_MASK = 1, + CLK_I2C1_PLL_SEL_SHIFT = 15, + CLK_I2C1_DIV_CON_SHIFT = 8, + CLK_I2C0_PLL_SEL_SHIFT = 7, + CLK_I2C0_DIV_CON_SHIFT = 0, + + /* CLKSEL_CON35 */ + CLK_I2C3_PLL_SEL_SHIFT = 15, + CLK_I2C3_DIV_CON_SHIFT = 8, + CLK_I2C2_PLL_SEL_SHIFT = 7, + CLK_I2C2_DIV_CON_SHIFT = 0, +}; + +#define VCO_MAX_KHZ (3200 * (MHz / KHz)) +#define VCO_MIN_KHZ (800 * (MHz / KHz)) +#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) +#define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) + +/* + * the div restructions of pll in integer mode, these are defined in + * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 + */ +#define PLL_DIV_MIN 16 +#define PLL_DIV_MAX 3200 + +/* + * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): + * Formulas also embedded within the Fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = Fractional PLL non-divided output frequency + * FOUTPOSTDIV = Fractional PLL divided output frequency + * (output of second post divider) + * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) + * REFDIV = Fractional PLL input reference clock divider + * FBDIV = Integer value programmed into feedback divide + * + */ +static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +{ + u32 *pll_con; + u32 mode_shift, mode_mask; + + pll_con = NULL; + mode_shift = 0; + switch (clk_id) { + case CLK_ARM: + pll_con = cru->apll_con; + mode_shift = APLL_MODE_SHIFT; + break; + case CLK_DDR: + pll_con = cru->dpll_con; + mode_shift = DPLL_MODE_SHIFT; + break; + case CLK_CODEC: + pll_con = cru->cpll_con; + mode_shift = CPLL_MODE_SHIFT; + break; + case CLK_GENERAL: + pll_con = cru->gpll_con; + mode_shift = GPLL_MODE_SHIFT; + break; + case CLK_NEW: + pll_con = cru->npll_con; + mode_shift = NPLL_MODE_SHIFT; + break; + default: + break; + } + mode_mask = 1 << mode_shift; + + /* All 8 PLLs have same VCO and output frequency range restrictions. */ + u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; + u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; + + debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \ + postdiv2=%d, vco=%u khz, output=%u khz\n", + pll_con, div->fbdiv, div->refdiv, div->postdiv1, + div->postdiv2, vco_khz, output_khz); + assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && + output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && + div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); + + /* + * When power on or changing PLL setting, + * we must force PLL into slow mode to ensure output stable clock. + */ + rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift); + + /* use integer mode */ + rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK, + PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); + + rk_clrsetreg(&pll_con[0], + PLL_FBDIV_MASK | PLL_POSTDIV1_MASK, + (div->fbdiv << PLL_FBDIV_SHIFT) | + (div->postdiv1 << PLL_POSTDIV1_SHIFT)); + rk_clrsetreg(&pll_con[1], + PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (div->postdiv2 << PLL_POSTDIV2_SHIFT) | + (div->refdiv << PLL_REFDIV_SHIFT)); + + /* waiting for pll lock */ + while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT))) + udelay(1); + + /* pll enter normal mode */ + rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); +} + +static void rkclk_init(struct rk3328_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + /* configure gpll cpll */ + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); + + /* configure perihp aclk, hclk, pclk */ + aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; + hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; + pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; + + rk_clrsetreg(&cru->clksel_con[28], + ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, + ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | + aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); + rk_clrsetreg(&cru->clksel_con[29], + PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK, + pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | + hclk_div << HCLK_PERIHP_DIV_CON_SHIFT); +} + +void rk3328_configure_cpu(struct rk3328_cru *cru, + enum apll_frequencies apll_freq) +{ + u32 clk_core_div; + u32 aclkm_div; + u32 pclk_dbg_div; + + rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]); + + clk_core_div = APLL_HZ / CLK_CORE_HZ - 1; + aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1; + pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1; + + rk_clrsetreg(&cru->clksel_con[0], + CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK, + CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT | + clk_core_div << CLK_CORE_DIV_SHIFT); + + rk_clrsetreg(&cru->clksel_con[1], + PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK, + pclk_dbg_div << PCLK_DBG_DIV_SHIFT | + aclkm_div << ACLKM_CORE_DIV_SHIFT); +} + + +static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id) +{ + u32 div, con; + + switch (clk_id) { + case SCLK_I2C0: + con = readl(&cru->clksel_con[34]); + div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; + break; + case SCLK_I2C1: + con = readl(&cru->clksel_con[34]); + div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; + break; + case SCLK_I2C2: + con = readl(&cru->clksel_con[35]); + div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; + break; + case SCLK_I2C3: + con = readl(&cru->clksel_con[35]); + div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; + break; + default: + printf("do not support this i2c bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz) +{ + int src_clk_div; + + src_clk_div = GPLL_HZ / hz; + assert(src_clk_div - 1 < 127); + + switch (clk_id) { + case SCLK_I2C0: + rk_clrsetreg(&cru->clksel_con[34], + CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT, + (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT); + break; + case SCLK_I2C1: + rk_clrsetreg(&cru->clksel_con[34], + CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT, + (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT); + break; + case SCLK_I2C2: + rk_clrsetreg(&cru->clksel_con[35], + CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT, + (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT); + break; + case SCLK_I2C3: + rk_clrsetreg(&cru->clksel_con[35], + CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT, + (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | + CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT); + break; + default: + printf("do not support this i2c bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(GPLL_HZ, src_clk_div); +} + +static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id) +{ + u32 div, con, con_id; + + switch (clk_id) { + case HCLK_SDMMC: + con_id = 30; + break; + case HCLK_EMMC: + con_id = 32; + break; + default: + return -EINVAL; + } + con = readl(&cru->clksel_con[con_id]); + div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; + + if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT + == CLK_EMMC_PLL_SEL_24M) + return DIV_TO_RATE(OSC_HZ, div); + else + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru, + ulong clk_id, ulong set_rate) +{ + int src_clk_div; + u32 con_id; + + switch (clk_id) { + case HCLK_SDMMC: + con_id = 30; + break; + case HCLK_EMMC: + con_id = 32; + break; + default: + return -EINVAL; + } + /* Select clk_sdmmc/emmc source from GPLL by default */ + src_clk_div = GPLL_HZ / set_rate; + + if (src_clk_div > 127) { + /* use 24MHz source for 400KHz clock */ + src_clk_div = OSC_HZ / set_rate; + rk_clrsetreg(&cru->clksel_con[con_id], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + } + + return rk3328_mmc_get_clk(cru, clk_id); +} + +static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru) +{ + u32 div, con; + + con = readl(&cru->clksel_con[24]); + div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT; + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz) +{ + u32 div = GPLL_HZ / hz; + + rk_clrsetreg(&cru->clksel_con[24], + CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK, + CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT | + (div - 1) << CLK_PWM_DIV_CON_SHIFT); + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3328_clk_get_rate(struct clk *clk) +{ + struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + switch (clk->id) { + case 0 ... 29: + return 0; + case HCLK_SDMMC: + case HCLK_EMMC: + rate = rk3328_mmc_get_clk(priv->cru, clk->id); + break; + case SCLK_I2C0: + case SCLK_I2C1: + case SCLK_I2C2: + case SCLK_I2C3: + rate = rk3328_i2c_get_clk(priv->cru, clk->id); + break; + case SCLK_PWM: + rate = rk3328_pwm_get_clk(priv->cru); + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + switch (clk->id) { + case 0 ... 29: + return 0; + case HCLK_SDMMC: + case HCLK_EMMC: + ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate); + break; + case SCLK_I2C0: + case SCLK_I2C1: + case SCLK_I2C2: + case SCLK_I2C3: + ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate); + break; + case SCLK_PWM: + ret = rk3328_pwm_set_clk(priv->cru, rate); + break; + default: + return -ENOENT; + } + + return ret; +} + +static struct clk_ops rk3328_clk_ops = { + .get_rate = rk3328_clk_get_rate, + .set_rate = rk3328_clk_set_rate, +}; + +static int rk3328_clk_probe(struct udevice *dev) +{ + struct rk3328_clk_priv *priv = dev_get_priv(dev); + + rkclk_init(priv->cru); + + return 0; +} + +static int rk3328_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk3328_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk3328_cru *)dev_get_addr(dev); + + return 0; +} + +static int rk3328_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3328_sysreset", "reset", &dev); + if (ret) + printf("Warning: No RK3328 reset driver: ret=%d\n", ret); + + return ret; +} + +static const struct udevice_id rk3328_clk_ids[] = { + { .compatible = "rockchip,rk3328-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3328_cru) = { + .name = "rockchip_rk3328_cru", + .id = UCLASS_CLK, + .of_match = rk3328_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv), + .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata, + .ops = &rk3328_clk_ops, + .bind = rk3328_clk_bind, + .probe = rk3328_clk_probe, +}; diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 2e87e4b62d..922ce7e549 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -7,7 +7,9 @@ #include <common.h> #include <clk-uclass.h> #include <dm.h> +#include <dt-structs.h> #include <errno.h> +#include <mapmem.h> #include <syscon.h> #include <asm/io.h> #include <asm/arch/clock.h> @@ -18,10 +20,16 @@ DECLARE_GLOBAL_DATA_PTR; -struct rk3399_pmuclk_priv { - struct rk3399_pmucru *pmucru; +#if CONFIG_IS_ENABLED(OF_PLATDATA) +struct rk3399_clk_plat { + struct dtd_rockchip_rk3399_cru dtd; }; +struct rk3399_pmuclk_plat { + struct dtd_rockchip_rk3399_pmucru dtd; +}; +#endif + struct pll_div { u32 refdiv; u32 fbdiv; @@ -381,6 +389,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return 0; } +#ifdef CONFIG_SPL_BUILD static void rkclk_init(struct rk3399_cru *cru) { u32 aclk_div; @@ -456,6 +465,7 @@ static void rkclk_init(struct rk3399_cru *cru) hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); } +#endif void rk3399_configure_cpu(struct rk3399_cru *cru, enum apll_l_frequencies apll_l_freq) @@ -709,6 +719,44 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, return rk3399_mmc_get_clk(cru, clk_id); } +#define PMUSGRF_DDR_RGN_CON16 0xff330040 +static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, + ulong set_rate) +{ + struct pll_div dpll_cfg; + + /* IC ECO bug, need to set this register */ + writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); + + /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ + switch (set_rate) { + case 200*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; + break; + case 300*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; + break; + case 666*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; + break; + case 800*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; + break; + case 933*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; + break; + default: + error("Unsupported SDRAM frequency!,%ld\n", set_rate); + } + rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); + + return set_rate; +} static ulong rk3399_clk_get_rate(struct clk *clk) { struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); @@ -763,6 +811,9 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); break; + case SCLK_DDRCLK: + ret = rk3399_ddr_set_clk(priv->cru, rate); + break; default: return -ENOENT; } @@ -777,19 +828,26 @@ static struct clk_ops rk3399_clk_ops = { static int rk3399_clk_probe(struct udevice *dev) { +#ifdef CONFIG_SPL_BUILD struct rk3399_clk_priv *priv = dev_get_priv(dev); - rkclk_init(priv->cru); +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3399_clk_plat *plat = dev_get_platdata(dev); + priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]); +#endif + rkclk_init(priv->cru); +#endif return 0; } static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_clk_priv *priv = dev_get_priv(dev); priv->cru = (struct rk3399_cru *)dev_get_addr(dev); - +#endif return 0; } @@ -811,7 +869,7 @@ static const struct udevice_id rk3399_clk_ids[] = { }; U_BOOT_DRIVER(clk_rk3399) = { - .name = "clk_rk3399", + .name = "rockchip_rk3399_cru", .id = UCLASS_CLK, .of_match = rk3399_clk_ids, .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), @@ -819,6 +877,9 @@ U_BOOT_DRIVER(clk_rk3399) = { .ops = &rk3399_clk_ops, .bind = rk3399_clk_bind, .probe = rk3399_clk_probe, +#if CONFIG_IS_ENABLED(OF_PLATDATA) + .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), +#endif }; static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) @@ -930,6 +991,7 @@ static struct clk_ops rk3399_pmuclk_ops = { .set_rate = rk3399_pmuclk_set_rate, }; +#ifndef CONFIG_SPL_BUILD static void pmuclk_init(struct rk3399_pmucru *pmucru) { u32 pclk_div; @@ -939,27 +1001,35 @@ static void pmuclk_init(struct rk3399_pmucru *pmucru) /* configure pmu pclk */ pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; - assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f); rk_clrsetreg(&pmucru->pmucru_clksel[0], PMU_PCLK_DIV_CON_MASK, pclk_div << PMU_PCLK_DIV_CON_SHIFT); } +#endif static int rk3399_pmuclk_probe(struct udevice *dev) { struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); - pmuclk_init(priv->pmucru); +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); + + priv->pmucru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]); +#endif +#ifndef CONFIG_SPL_BUILD + pmuclk_init(priv->pmucru); +#endif return 0; } static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev); - +#endif return 0; } @@ -969,11 +1039,14 @@ static const struct udevice_id rk3399_pmuclk_ids[] = { }; U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { - .name = "pmuclk_rk3399", + .name = "rockchip_rk3399_pmucru", .id = UCLASS_CLK, .of_match = rk3399_pmuclk_ids, .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, .ops = &rk3399_pmuclk_ops, .probe = rk3399_pmuclk_probe, +#if CONFIG_IS_ENABLED(OF_PLATDATA) + .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), +#endif }; diff --git a/drivers/core/root.c b/drivers/core/root.c index 175fd3fb25..93ab568296 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -205,7 +205,7 @@ int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset, offset > 0; offset = fdt_next_subnode(blob, offset)) { if (pre_reloc_only && - !fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL)) + !dm_fdt_pre_reloc(blob, offset)) continue; if (!fdtdec_get_is_enabled(blob, offset)) { dm_dbg(" - ignoring disabled device\n"); diff --git a/drivers/core/util.c b/drivers/core/util.c index e01dd06d28..5ceac8bbb1 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <libfdt.h> #include <vsprintf.h> void dm_warn(const char *fmt, ...) @@ -35,3 +36,27 @@ int list_count_items(struct list_head *head) return count; } + +bool dm_fdt_pre_reloc(const void *blob, int offset) +{ + if (fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL)) + return true; + +#ifdef CONFIG_TPL_BUILD + if (fdt_getprop(blob, offset, "u-boot,dm-tpl", NULL)) + return true; +#elif defined(CONFIG_SPL_BUILD) + if (fdt_getprop(blob, offset, "u-boot,dm-spl", NULL)) + return true; +#else + /* + * In regular builds individual spl and tpl handling both + * count as handled pre-relocation for later second init. + */ + if (fdt_getprop(blob, offset, "u-boot,dm-spl", NULL) || + fdt_getprop(blob, offset, "u-boot,dm-tpl", NULL)) + return true; +#endif + + return false; +} diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index bd91f91758..bdde831ffd 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -8,9 +8,11 @@ #include <common.h> #include <dm.h> +#include <dt-structs.h> #include <fdtdec.h> #include <libfdt.h> #include <malloc.h> +#include <mapmem.h> #include <sdhci.h> #include <clk.h> @@ -19,6 +21,9 @@ DECLARE_GLOBAL_DATA_PTR; #define EMMC_MIN_FREQ 400000 struct rockchip_sdhc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3399_sdhci_5_1 dtplat; +#endif struct mmc_config cfg; struct mmc mmc; }; @@ -37,10 +42,18 @@ static int arasan_sdhci_probe(struct udevice *dev) int max_frequency, ret; struct clk clk; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat; + host->name = dev->name; + host->ioaddr = map_sysmem(dtplat->reg[1], dtplat->reg[3]); + max_frequency = dtplat->max_frequency; + ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk); +#else max_frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "max-frequency", 0); ret = clk_get_by_index(dev, 0, &clk); +#endif if (!ret) { ret = clk_set_rate(&clk, max_frequency); if (IS_ERR_VALUE(ret)) @@ -66,10 +79,12 @@ static int arasan_sdhci_probe(struct udevice *dev) static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct sdhci_host *host = dev_get_priv(dev); host->name = dev->name; host->ioaddr = dev_get_addr_ptr(dev); +#endif return 0; } @@ -87,7 +102,7 @@ static const struct udevice_id arasan_sdhci_ids[] = { }; U_BOOT_DRIVER(arasan_sdhci_drv) = { - .name = "arasan_sdhci", + .name = "rockchip_rk3399_sdhci_5_1", .id = UCLASS_MMC, .of_match = arasan_sdhci_ids, .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 69efa3857a..28cedf0c46 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -6,6 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <clk.h> #include <common.h> #include <dm.h> #include <fdtdec.h> @@ -13,6 +14,8 @@ #include <malloc.h> #include <sdhci.h> +DECLARE_GLOBAL_DATA_PTR; + #ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ # define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0 #endif @@ -20,6 +23,7 @@ struct arasan_sdhci_plat { struct mmc_config cfg; struct mmc mmc; + unsigned int f_max; }; static int arasan_sdhci_probe(struct udevice *dev) @@ -27,8 +31,29 @@ static int arasan_sdhci_probe(struct udevice *dev) struct arasan_sdhci_plat *plat = dev_get_platdata(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_host *host = dev_get_priv(dev); + struct clk clk; + unsigned long clock; int ret; + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return clock; + } + debug("%s: CLK %ld\n", __func__, clock); + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; @@ -36,9 +61,9 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; #endif - host->max_clk = CONFIG_ZYNQ_SDHCI_MAX_FREQ; + host->max_clk = clock; - ret = sdhci_setup_cfg(&plat->cfg, host, 0, + ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, CONFIG_ZYNQ_SDHCI_MIN_FREQ); host->mmc = &plat->mmc; if (ret) @@ -52,11 +77,15 @@ static int arasan_sdhci_probe(struct udevice *dev) static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) { + struct arasan_sdhci_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev); host->name = dev->name; host->ioaddr = (void *)dev_get_addr(dev); + plat->f_max = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ); + return 0; } diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 079082a26f..9f69d75a89 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -154,48 +154,6 @@ int parse_mc_firmware_fit_image(u64 mc_fw_addr, } #endif -/* - * Calculates the values to be used to specify the address range - * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers. - * It returns the highest 512MB-aligned address within the given - * address range, in '*aligned_base_addr', and the number of 256 MiB - * blocks in it, in 'num_256mb_blocks'. - */ -static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr, - size_t mc_ram_size, - u64 *aligned_base_addr, - u8 *num_256mb_blocks) -{ - u64 addr; - u16 num_blocks; - - if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) { - printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", - mc_ram_size); - return -EINVAL; - } - - num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; - if (num_blocks < 1 || num_blocks > 0xff) { - printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", - mc_ram_size); - return -EINVAL; - } - - addr = (mc_private_ram_start_addr + mc_ram_size - 1) & - MC_RAM_BASE_ADDR_ALIGNMENT_MASK; - - if (addr < mc_private_ram_start_addr) { - printf("fsl-mc: ERROR: bad start address %#llx\n", - mc_private_ram_start_addr); - return -EFAULT; - } - - *aligned_base_addr = addr; - *num_256mb_blocks = num_blocks; - return 0; -} - static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id, struct eth_device *eth_dev) { @@ -550,17 +508,16 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) size_t raw_image_size = 0; #endif struct mc_version mc_ver_info; - u64 mc_ram_aligned_base_addr; u8 mc_ram_num_256mb_blocks; size_t mc_ram_size = mc_get_dram_block_size(); - - error = calculate_mc_private_ram_params(mc_ram_addr, - mc_ram_size, - &mc_ram_aligned_base_addr, - &mc_ram_num_256mb_blocks); - if (error != 0) + mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; + if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) { + error = -EINVAL; + printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", + mc_ram_size); goto out; + } /* * Management Complex cores should be held at reset out of POR. @@ -602,11 +559,11 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) /* * Tell MC what is the address range of the DRAM block assigned to it: */ - reg_mcfbalr = (u32)mc_ram_aligned_base_addr | + reg_mcfbalr = (u32)mc_ram_addr | (mc_ram_num_256mb_blocks - 1); out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr); out_le32(&mc_ccsr_regs->reg_mcfbahr, - (u32)(mc_ram_aligned_base_addr >> 32)); + (u32)(mc_ram_addr >> 32)); out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ); /* @@ -714,21 +671,7 @@ int get_dpl_apply_status(void) */ u64 mc_get_dram_addr(void) { - u64 mc_ram_addr; - - /* - * The MC private DRAM block was already carved at the end of DRAM - * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: - */ - if (gd->bd->bi_dram[1].start) { - mc_ram_addr = - gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; - } else { - mc_ram_addr = - gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; - } - - return mc_ram_addr; + return gd->arch.resv_ram; } /** diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index a160564439..357f8c2917 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -175,16 +175,13 @@ struct zynq_gem_priv { u32 rxbd_current; u32 rx_first_buf; int phyaddr; - u32 emio; int init; struct zynq_gem_regs *iobase; phy_interface_t interface; struct phy_device *phydev; int phy_of_handle; struct mii_dev *bus; -#ifdef CONFIG_CLK_ZYNQMP struct clk clk; -#endif }; static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, @@ -457,16 +454,17 @@ static int zynq_gem_init(struct udevice *dev) break; } - /* Change the rclk and clk only not using EMIO interface */ - if (!priv->emio) -#ifndef CONFIG_CLK_ZYNQMP - zynq_slcr_gem_clk_setup((ulong)priv->iobase != - ZYNQ_GEM_BASEADDR0, clk_rate); -#else - ret = clk_set_rate(&priv->clk, clk_rate); - if (IS_ERR_VALUE(ret)) - return -1; -#endif + ret = clk_set_rate(&priv->clk, clk_rate); + if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { + dev_err(dev, "failed to set tx clock rate\n"); + return ret; + } + + ret = clk_enable(&priv->clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable tx clock\n"); + return ret; + } setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); @@ -639,13 +637,11 @@ static int zynq_gem_probe(struct udevice *dev) priv->tx_bd = (struct emac_bd *)bd_space; priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); -#ifdef CONFIG_CLK_ZYNQMP ret = clk_get_by_name(dev, "tx_clk", &priv->clk); if (ret < 0) { dev_err(dev, "failed to get clock\n"); return -EINVAL; } -#endif priv->bus = mdio_alloc(); priv->bus->read = zynq_gem_miiphy_read; @@ -690,7 +686,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) pdata->iobase = (phys_addr_t)dev_get_addr(dev); priv->iobase = (struct zynq_gem_regs *)pdata->iobase; /* Hardcode for now */ - priv->emio = 0; priv->phyaddr = -1; priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, @@ -708,8 +703,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) } priv->interface = pdata->phy_interface; - priv->emio = fdtdec_get_bool(gd->fdt_blob, node, "xlnx,emio"); - printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, priv->phyaddr, phy_string_for_interface(priv->interface)); diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 0c832e187d..f3e3072ccc 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -132,6 +132,15 @@ config ROCKCHIP_RK3036_PINCTRL definitions and pin control functions for each available multiplex function. +config ROCKCHIP_RK3188_PINCTRL + bool "Rockchip pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3188 SoCs. The driver + is controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config ROCKCHIP_RK3288_PINCTRL bool "Rockchip pin control driver" depends on DM @@ -148,6 +157,15 @@ config PINCTRL_AT91PIO4 This option is to enable the AT91 pinctrl driver for AT91 PIO4 controller which is available on SAMA5D2 SoC. +config ROCKCHIP_RK3328_PINCTRL + bool "Rockchip pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3328 SoCs. The driver + is controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config ROCKCHIP_RK3399_PINCTRL bool "Rockchip pin control driver" depends on DM @@ -185,6 +203,15 @@ config PINCTRL_STI the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_STM32 + bool "ST STM32 pin control driver" + depends on DM + help + Supports pin multiplexing control on stm32 SoCs. The driver is + controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + endif source "drivers/pinctrl/meson/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index a2f810156b..b04ca86e1d 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/ obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o +obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index 49afe91c24..9efad0623a 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -12,6 +12,7 @@ #include <dm/lists.h> #include <dm/pinctrl.h> #include <dm/uclass.h> +#include <dm/util.h> DECLARE_GLOBAL_DATA_PTR; @@ -131,7 +132,7 @@ static int pinconfig_post_bind(struct udevice *dev) offset > 0; offset = fdt_next_subnode(fdt, offset)) { if (pre_reloc_only && - !fdt_getprop(fdt, offset, "u-boot,dm-pre-reloc", NULL)) + !dm_fdt_pre_reloc(fdt, offset)) continue; /* * If this node has "compatible" property, this is not diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c new file mode 100644 index 0000000000..aa2c440b14 --- /dev/null +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -0,0 +1,117 @@ +#include <common.h> +#include <asm/arch/gpio.h> +#include <dm.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin) +{ + gpio_dsc->port = (port_pin & 0xF000) >> 12; + gpio_dsc->pin = (port_pin & 0x0F00) >> 8; + debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port, + gpio_dsc->pin); + + return 0; +} + +static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node) +{ + gpio_fn &= 0x00FF; + + switch (gpio_fn) { + case 0: + gpio_ctl->mode = STM32_GPIO_MODE_IN; + break; + case 1 ... 16: + gpio_ctl->mode = STM32_GPIO_MODE_AF; + gpio_ctl->af = gpio_fn - 1; + break; + case 17: + gpio_ctl->mode = STM32_GPIO_MODE_AN; + break; + default: + gpio_ctl->mode = STM32_GPIO_MODE_OUT; + break; + } + + gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0); + + if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain")) + gpio_ctl->otype = STM32_GPIO_OTYPE_OD; + else + gpio_ctl->otype = STM32_GPIO_OTYPE_PP; + + if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up")) + gpio_ctl->pupd = STM32_GPIO_PUPD_UP; + else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down")) + gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN; + else + gpio_ctl->pupd = STM32_GPIO_PUPD_NO; + + debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n", + __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype, + gpio_ctl->pupd); + + return 0; +} + +static int stm32_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + u32 pin_mux[50]; + struct fdtdec_phandle_args args; + int rv, len; + + /* Get node pinctrl-0 */ + rv = fdtdec_parse_phandle_with_args(gd->fdt_blob, periph->of_offset, + "pinctrl-0", 0, 0, 0, &args); + if (rv) + return rv; + /* + * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for + * usart1) of pin controller phandle "pinctrl-0" + * */ + fdt_for_each_subnode(args.node, gd->fdt_blob, args.node) { + struct stm32_gpio_dsc gpio_dsc; + struct stm32_gpio_ctl gpio_ctl; + int i; + + len = fdtdec_get_int_array_count(gd->fdt_blob, args.node, + "pinmux", pin_mux, + ARRAY_SIZE(pin_mux)); + debug("%s: periph->name = %s, no of pinmux entries= %d\n", + __func__, periph->name, len); + if (len < 0) + return -EINVAL; + for (i = 0; i < len; i++) { + debug("%s: pinmux = %x\n", __func__, *(pin_mux + i)); + prep_gpio_dsc(&gpio_dsc, *(pin_mux + i)); + prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), args.node); + + rv = stm32_gpio_config(&gpio_dsc, &gpio_ctl); + debug("%s: rv = %d\n\n", __func__, rv); + if (rv) + return rv; + } + } + + return 0; +} + +static struct pinctrl_ops stm32_pinctrl_ops = { + .set_state_simple = stm32_pinctrl_set_state_simple, +}; + +static const struct udevice_id stm32_pinctrl_ids[] = { + { .compatible = "st,stm32f746-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_stm32) = { + .name = "pinctrl_stm32", + .id = UCLASS_PINCTRL, + .of_match = stm32_pinctrl_ids, + .ops = &stm32_pinctrl_ops, + .bind = dm_scan_fdt_dev, +}; diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 805c833ec9..b0b698ac04 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -6,5 +6,7 @@ # obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3188_PINCTRL) += pinctrl_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3328_PINCTRL) += pinctrl_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3399_PINCTRL) += pinctrl_rk3399.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c new file mode 100644 index 0000000000..ef94dab210 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3188.c @@ -0,0 +1,611 @@ +/* + * Pinctrl driver for Rockchip RK3188 SoCs + * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3188.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <asm/arch/pmu_rk3188.h> +#include <dm/pinctrl.h> +#include <dm/root.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3188_pinctrl_priv { + struct rk3188_grf *grf; + struct rk3188_pmu *pmu; + int num_banks; +}; + +/** + * Encode variants of iomux registers into a type variable + */ +#define IOMUX_GPIO_ONLY BIT(0) + +/** + * @type: iomux variant using IOMUX_* constants + * @offset: if initialized to -1 it will be autocalculated, by specifying + * an initial offset value the relevant source offset can be reset + * to a new value for autocalculating the following iomux registers. + */ +struct rockchip_iomux { + u8 type; + s16 offset; +}; + +/** + * @reg: register offset of the gpio bank + * @nr_pins: number of pins in this bank + * @bank_num: number of the bank, to account for holes + * @name: name of the bank + * @iomux: array describing the 4 iomux sources of the bank + */ +struct rockchip_pin_bank { + u16 reg; + u8 nr_pins; + u8 bank_num; + char *name; + struct rockchip_iomux iomux[4]; +}; + +#define PIN_BANK(id, pins, label) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + }, \ + } + +#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = -1 }, \ + { .type = iom1, .offset = -1 }, \ + { .type = iom2, .offset = -1 }, \ + { .type = iom3, .offset = -1 }, \ + }, \ + } + +#ifndef CONFIG_SPL_BUILD +static struct rockchip_pin_bank rk3188_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; +#endif + +static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id) +{ + switch (pwm_id) { + case PERIPH_ID_PWM0: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT, + GPIO3D3_PWM_0 << GPIO3D3_SHIFT); + break; + case PERIPH_ID_PWM1: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT, + GPIO3D4_PWM_1 << GPIO3D4_SHIFT); + break; + case PERIPH_ID_PWM2: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT, + GPIO3D5_PWM_2 << GPIO3D5_SHIFT); + break; + case PERIPH_ID_PWM3: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT, + GPIO3D6_PWM_3 << GPIO3D6_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf, + struct rk3188_pmu *pmu, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D1_MASK << GPIO1D1_SHIFT | + GPIO1D0_MASK << GPIO1D0_SHIFT, + GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT | + GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT); + /* enable new i2c controller */ + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT, + 1 << RKI2C0_SEL_SHIFT); + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D3_MASK << GPIO1D3_SHIFT | + GPIO1D2_MASK << GPIO1D2_SHIFT, + GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT | + GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT, + 1 << RKI2C1_SEL_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D5_MASK << GPIO1D5_SHIFT | + GPIO1D4_MASK << GPIO1D4_SHIFT, + GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT | + GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT, + 1 << RKI2C2_SEL_SHIFT); + break; + case PERIPH_ID_I2C3: + rk_clrsetreg(&grf->gpio3b_iomux, + GPIO3B7_MASK << GPIO3B7_SHIFT | + GPIO3B6_MASK << GPIO3B6_SHIFT, + GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT | + GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT, + 1 << RKI2C3_SEL_SHIFT); + break; + case PERIPH_ID_I2C4: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D7_MASK << GPIO1D7_SHIFT | + GPIO1D6_MASK << GPIO1D6_SHIFT, + GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT | + GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT, + 1 << RKI2C4_SEL_SHIFT); + break; + default: + debug("i2c id = %d iomux error!\n", i2c_id); + break; + } +} + +static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf, + enum periph_id spi_id, int cs) +{ + switch (spi_id) { + case PERIPH_ID_SPI0: + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A7_MASK << GPIO1A7_SHIFT, + GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B7_MASK << GPIO1B7_SHIFT, + GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT); + break; + default: + goto err; + } + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A4_MASK << GPIO1A4_SHIFT | + GPIO1A5_MASK << GPIO1A5_SHIFT | + GPIO1A6_MASK << GPIO1A6_SHIFT, + GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT | + GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT | + GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT); + break; + case PERIPH_ID_SPI1: + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D7_MASK << GPIO0D7_SHIFT, + GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B6_MASK << GPIO1B6_SHIFT, + GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT); + break; + default: + goto err; + } + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D4_MASK << GPIO0D4_SHIFT | + GPIO0D5_MASK << GPIO0D5_SHIFT | + GPIO0D6_MASK << GPIO0D6_SHIFT, + GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT | + GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT | + GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT); + break; + default: + goto err; + } + + return 0; +err: + debug("rkspi: periph%d cs=%d not supported", spi_id, cs); + return -ENOENT; +} + +static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART0: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A3_MASK << GPIO1A3_SHIFT | + GPIO1A2_MASK << GPIO1A2_SHIFT | + GPIO1A1_MASK << GPIO1A1_SHIFT | + GPIO1A0_MASK << GPIO1A0_SHIFT, + GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT | + GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT | + GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT | + GPIO1A0_UART0_SIN << GPIO1A0_SHIFT); + break; + case PERIPH_ID_UART1: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A7_MASK << GPIO1A7_SHIFT | + GPIO1A6_MASK << GPIO1A6_SHIFT | + GPIO1A5_MASK << GPIO1A5_SHIFT | + GPIO1A4_MASK << GPIO1A4_SHIFT, + GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT | + GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT | + GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT | + GPIO1A4_UART1_SIN << GPIO1A4_SHIFT); + break; + case PERIPH_ID_UART2: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK << GPIO1B1_SHIFT | + GPIO1B0_MASK << GPIO1B0_SHIFT, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); + break; + case PERIPH_ID_UART3: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B5_MASK << GPIO1B5_SHIFT | + GPIO1B4_MASK << GPIO1B4_SHIFT | + GPIO1B3_MASK << GPIO1B3_SHIFT | + GPIO1B2_MASK << GPIO1B2_SHIFT, + GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT | + GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT | + GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT | + GPIO1B2_UART3_SIN << GPIO1B2_SHIFT); + break; + default: + debug("uart id = %d iomux error!\n", uart_id); + break; + } +} + +static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT, + 1 << EMMC_FLASH_SEL_SHIFT); + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D2_MASK << GPIO0D2_SHIFT | + GPIO0D0_MASK << GPIO0D0_SHIFT, + GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT | + GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio3b_iomux, + GPIO3B0_MASK << GPIO3B0_SHIFT, + GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT); + rk_clrsetreg(&grf->gpio3a_iomux, + GPIO3A7_MASK << GPIO3A7_SHIFT | + GPIO3A6_MASK << GPIO3A6_SHIFT | + GPIO3A5_MASK << GPIO3A5_SHIFT | + GPIO3A4_MASK << GPIO3A4_SHIFT | + GPIO3A3_MASK << GPIO3A3_SHIFT | + GPIO3A3_MASK << GPIO3A2_SHIFT, + GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT | + GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT | + GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT | + GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT | + GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT | + GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT); + break; + default: + debug("mmc id = %d iomux error!\n", mmc_id); + break; + } +} + +static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + pinctrl_rk3188_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func); + break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + pinctrl_rk3188_spi_config(priv->grf, func, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + pinctrl_rk3188_uart_config(priv->grf, func); + break; + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk3188_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3188_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 44: + return PERIPH_ID_SPI0; + case 45: + return PERIPH_ID_SPI1; + case 46: + return PERIPH_ID_SPI2; + case 60: + return PERIPH_ID_I2C0; + case 62: /* Note strange order */ + return PERIPH_ID_I2C1; + case 61: + return PERIPH_ID_I2C2; + case 63: + return PERIPH_ID_I2C3; + case 64: + return PERIPH_ID_I2C4; + case 65: + return PERIPH_ID_I2C5; + } +#endif + + return -ENOENT; +} + +static int rk3188_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3188_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return rk3188_pinctrl_request(dev, func, 0); +} + +#ifndef CONFIG_SPL_BUILD +int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv, + int banknum, int ind, u32 **addrp, uint *shiftp, + uint *maskp) +{ + struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum]; + uint muxnum; + u32 *addr; + + for (muxnum = 0; muxnum < 4; muxnum++) { + struct rockchip_iomux *mux = &bank->iomux[muxnum]; + + if (ind >= 8) { + ind -= 8; + continue; + } + + addr = &priv->grf->gpio0c_iomux - 2; + addr += mux->offset; + *shiftp = ind & 7; + *maskp = 3; + *shiftp *= 2; + + debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr, + *maskp, *shiftp); + *addrp = addr; + return 0; + } + + return -EINVAL; +} + +static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, + int index) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + uint shift; + uint mask; + u32 *addr; + int ret; + + ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift, + &mask); + if (ret) + return ret; + return (readl(addr) & mask) >> shift; +} + +static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index, + int muxval, int flags) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + uint shift, ind = index; + uint mask; + u32 *addr; + int ret; + + debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags); + ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift, + &mask); + if (ret) + return ret; + rk_clrsetreg(addr, mask << shift, muxval << shift); + + /* Handle pullup/pulldown */ + if (flags) { + uint val = 0; + + if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP)) + val = 1; + else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) + val = 2; + + ind = index >> 3; + + if (banknum == 0 && index < 12) { + addr = &priv->pmu->gpio0_p[ind]; + shift = (index & 7) * 2; + } else if (banknum == 0 && index >= 12) { + addr = &priv->grf->gpio0_p[ind - 1]; + /* + * The bits in the grf-registers have an inverse + * ordering with the lowest pin being in bits 15:14 + * and the highest pin in bits 1:0 . + */ + shift = (7 - (index & 7)) * 2; + } else { + addr = &priv->grf->gpio1_p[banknum - 1][ind]; + shift = (7 - (index & 7)) * 2; + } + debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val, + shift); + rk_clrsetreg(addr, 3 << shift, val << shift); + } + + return 0; +} + +static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + const void *blob = gd->fdt_blob; + int pcfg_node, ret, flags, count, i; + u32 cell[60], *ptr; + + debug("%s: %s %s\n", __func__, dev->name, config->name); + ret = fdtdec_get_int_array_count(blob, config->of_offset, + "rockchip,pins", cell, + ARRAY_SIZE(cell)); + if (ret < 0) { + debug("%s: bad array %d\n", __func__, ret); + return -EINVAL; + } + count = ret; + for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) { + pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]); + if (pcfg_node < 0) + return -EINVAL; + flags = pinctrl_decode_pin_config(blob, pcfg_node); + if (flags < 0) + return flags; + + ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2], + flags); + if (ret) + return ret; + } + + return 0; +} +#endif + +static struct pinctrl_ops rk3188_pinctrl_ops = { +#ifndef CONFIG_SPL_BUILD + .set_state = rk3188_pinctrl_set_state, + .get_gpio_mux = rk3188_pinctrl_get_gpio_mux, +#endif + .set_state_simple = rk3188_pinctrl_set_state_simple, + .request = rk3188_pinctrl_request, + .get_periph_id = rk3188_pinctrl_get_periph_id, +}; + +#ifndef CONFIG_SPL_BUILD +static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv, + struct rockchip_pin_bank *banks, + int count) +{ + struct rockchip_pin_bank *bank; + uint reg, muxnum, banknum; + + reg = 0; + for (banknum = 0; banknum < count; banknum++) { + bank = &banks[banknum]; + bank->reg = reg; + debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4); + for (muxnum = 0; muxnum < 4; muxnum++) { + struct rockchip_iomux *mux = &bank->iomux[muxnum]; + + mux->offset = reg; + reg += 1; + } + } + + return 0; +} +#endif + +static int rk3188_pinctrl_probe(struct udevice *dev) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu); +#ifndef CONFIG_SPL_BUILD + ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks, + ARRAY_SIZE(rk3188_pin_banks)); +#endif + + return ret; +} + +static const struct udevice_id rk3188_pinctrl_ids[] = { + { .compatible = "rockchip,rk3188-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3188) = { + .name = "rockchip_rk3188_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3188_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv), + .ops = &rk3188_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rk3188_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c new file mode 100644 index 0000000000..5ca6782ccc --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -0,0 +1,419 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> +#include <asm/arch/grf_rk3328.h> +#include <asm/arch/periph.h> +#include <asm/io.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3328_pinctrl_priv { + struct rk3328_grf_regs *grf; +}; + +enum { + /* GRF_GPIO0A_IOMUX */ + GRF_GPIO0A5_SEL_SHIFT = 10, + GRF_GPIO0A5_SEL_MASK = 3 << GRF_GPIO0A5_SEL_SHIFT, + GRF_I2C3_SCL = 2, + + GRF_GPIO0A6_SEL_SHIFT = 12, + GRF_GPIO0A6_SEL_MASK = 3 << GRF_GPIO0A6_SEL_SHIFT, + GRF_I2C3_SDA = 2, + + GRF_GPIO0A7_SEL_SHIFT = 14, + GRF_GPIO0A7_SEL_MASK = 3 << GRF_GPIO0A7_SEL_SHIFT, + GRF_EMMC_DATA0 = 2, + + /* GRF_GPIO1A_IOMUX */ + GRF_GPIO1A0_SEL_SHIFT = 0, + GRF_GPIO1A0_SEL_MASK = 0x3fff << GRF_GPIO1A0_SEL_SHIFT, + GRF_CARD_DATA_CLK_CMD_DETN = 0x1555, + + /* GRF_GPIO2A_IOMUX */ + GRF_GPIO2A0_SEL_SHIFT = 0, + GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT, + GRF_UART2_TX_M1 = 1, + + GRF_GPIO2A1_SEL_SHIFT = 2, + GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT, + GRF_UART2_RX_M1 = 1, + + GRF_GPIO2A2_SEL_SHIFT = 4, + GRF_GPIO2A2_SEL_MASK = 3 << GRF_GPIO2A2_SEL_SHIFT, + GRF_PWM_IR = 1, + + GRF_GPIO2A4_SEL_SHIFT = 8, + GRF_GPIO2A4_SEL_MASK = 3 << GRF_GPIO2A4_SEL_SHIFT, + GRF_PWM_0 = 1, + GRF_I2C1_SDA, + + GRF_GPIO2A5_SEL_SHIFT = 10, + GRF_GPIO2A5_SEL_MASK = 3 << GRF_GPIO2A5_SEL_SHIFT, + GRF_PWM_1 = 1, + GRF_I2C1_SCL, + + GRF_GPIO2A6_SEL_SHIFT = 12, + GRF_GPIO2A6_SEL_MASK = 3 << GRF_GPIO2A6_SEL_SHIFT, + GRF_PWM_2 = 1, + + GRF_GPIO2A7_SEL_SHIFT = 14, + GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT, + GRF_CARD_PWR_EN_M0 = 1, + + /* GRF_GPIO2BL_IOMUX */ + GRF_GPIO2BL0_SEL_SHIFT = 0, + GRF_GPIO2BL0_SEL_MASK = 0x3f << GRF_GPIO2BL0_SEL_SHIFT, + GRF_SPI_CLK_TX_RX_M0 = 0x15, + + GRF_GPIO2BL3_SEL_SHIFT = 6, + GRF_GPIO2BL3_SEL_MASK = 3 << GRF_GPIO2BL3_SEL_SHIFT, + GRF_SPI_CSN0_M0 = 1, + + GRF_GPIO2BL4_SEL_SHIFT = 8, + GRF_GPIO2BL4_SEL_MASK = 3 << GRF_GPIO2BL4_SEL_SHIFT, + GRF_SPI_CSN1_M0 = 1, + + GRF_GPIO2BL5_SEL_SHIFT = 10, + GRF_GPIO2BL5_SEL_MASK = 3 << GRF_GPIO2BL5_SEL_SHIFT, + GRF_I2C2_SDA = 1, + + GRF_GPIO2BL6_SEL_SHIFT = 12, + GRF_GPIO2BL6_SEL_MASK = 3 << GRF_GPIO2BL6_SEL_SHIFT, + GRF_I2C2_SCL = 1, + + /* GRF_GPIO2D_IOMUX */ + GRF_GPIO2D0_SEL_SHIFT = 0, + GRF_GPIO2D0_SEL_MASK = 3 << GRF_GPIO2D0_SEL_SHIFT, + GRF_I2C0_SCL = 1, + + GRF_GPIO2D1_SEL_SHIFT = 2, + GRF_GPIO2D1_SEL_MASK = 3 << GRF_GPIO2D1_SEL_SHIFT, + GRF_I2C0_SDA = 1, + + GRF_GPIO2D4_SEL_SHIFT = 8, + GRF_GPIO2D4_SEL_MASK = 0xff << GRF_GPIO2D4_SEL_SHIFT, + GRF_EMMC_DATA123 = 0xaa, + + /* GRF_GPIO3C_IOMUX */ + GRF_GPIO3C0_SEL_SHIFT = 0, + GRF_GPIO3C0_SEL_MASK = 0x3fff << GRF_GPIO3C0_SEL_SHIFT, + GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, + + /* GRF_COM_IOMUX */ + GRF_UART2_IOMUX_SEL_SHIFT = 0, + GRF_UART2_IOMUX_SEL_MASK = 3 << GRF_UART2_IOMUX_SEL_SHIFT, + GRF_UART2_IOMUX_SEL_M0 = 0, + GRF_UART2_IOMUX_SEL_M1, + + GRF_SPI_IOMUX_SEL_SHIFT = 4, + GRF_SPI_IOMUX_SEL_MASK = 3 << GRF_SPI_IOMUX_SEL_SHIFT, + GRF_SPI_IOMUX_SEL_M0 = 0, + GRF_SPI_IOMUX_SEL_M1, + GRF_SPI_IOMUX_SEL_M2, + + GRF_CARD_IOMUX_SEL_SHIFT = 7, + GRF_CARD_IOMUX_SEL_MASK = 1 << GRF_CARD_IOMUX_SEL_SHIFT, + GRF_CARD_IOMUX_SEL_M0 = 0, + GRF_CARD_IOMUX_SEL_M1, +}; + +static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id) +{ + switch (pwm_id) { + case PERIPH_ID_PWM0: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A4_SEL_MASK, + GRF_PWM_0 << GRF_GPIO2A4_SEL_SHIFT); + break; + case PERIPH_ID_PWM1: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A5_SEL_MASK, + GRF_PWM_1 << GRF_GPIO2A5_SEL_SHIFT); + break; + case PERIPH_ID_PWM2: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A6_SEL_MASK, + GRF_PWM_2 << GRF_GPIO2A6_SEL_SHIFT); + break; + case PERIPH_ID_PWM3: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A2_SEL_MASK, + GRF_PWM_IR << GRF_GPIO2A2_SEL_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio2d_iomux, + GRF_GPIO2D0_SEL_MASK | GRF_GPIO2D1_SEL_MASK, + GRF_I2C0_SCL << GRF_GPIO2D0_SEL_SHIFT + | GRF_I2C0_SDA << GRF_GPIO2D1_SEL_SHIFT); + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A4_SEL_MASK | GRF_GPIO2A5_SEL_MASK, + GRF_I2C1_SCL << GRF_GPIO2A5_SEL_SHIFT + | GRF_I2C1_SDA << GRF_GPIO2A4_SEL_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio2bl_iomux, + GRF_GPIO2BL5_SEL_MASK | GRF_GPIO2BL6_SEL_MASK, + GRF_I2C2_SCL << GRF_GPIO2BL6_SEL_SHIFT + | GRF_I2C2_SDA << GRF_GPIO2BL6_SEL_SHIFT); + break; + case PERIPH_ID_I2C3: + rk_clrsetreg(&grf->gpio0a_iomux, + GRF_GPIO0A5_SEL_MASK | GRF_GPIO0A6_SEL_MASK, + GRF_I2C3_SCL << GRF_GPIO0A5_SEL_SHIFT + | GRF_I2C3_SDA << GRF_GPIO0A6_SEL_SHIFT); + break; + default: + debug("i2c id = %d iomux error!\n", i2c_id); + break; + } +} + +static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id) +{ + switch (lcd_id) { + case PERIPH_ID_LCDC0: + break; + default: + debug("lcdc id = %d iomux error!\n", lcd_id); + break; + } +} + +static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf, + enum periph_id spi_id, int cs) +{ + rk_clrsetreg(&grf->com_iomux, + GRF_SPI_IOMUX_SEL_MASK, + GRF_SPI_IOMUX_SEL_M0 << GRF_SPI_IOMUX_SEL_SHIFT); + + switch (spi_id) { + case PERIPH_ID_SPI0: + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio2bl_iomux, + GRF_GPIO2BL3_SEL_MASK, + GRF_SPI_CSN0_M0 << GRF_GPIO2BL3_SEL_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio2bl_iomux, + GRF_GPIO2BL4_SEL_MASK, + GRF_SPI_CSN1_M0 << GRF_GPIO2BL4_SEL_SHIFT); + break; + default: + goto err; + } + rk_clrsetreg(&grf->gpio2bl_iomux, + GRF_GPIO2BL0_SEL_MASK, + GRF_SPI_CLK_TX_RX_M0 << GRF_GPIO2BL0_SEL_SHIFT); + break; + default: + goto err; + } + + return 0; +err: + debug("rkspi: periph%d cs=%d not supported", spi_id, cs); + return -ENOENT; +} + +static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART2: + break; + /* uart2 iomux select m1 */ + rk_clrsetreg(&grf->com_iomux, + GRF_UART2_IOMUX_SEL_MASK, + GRF_UART2_IOMUX_SEL_M1 + << GRF_UART2_IOMUX_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A0_SEL_MASK | GRF_GPIO2A1_SEL_MASK, + GRF_UART2_TX_M1 << GRF_GPIO2A0_SEL_SHIFT | + GRF_UART2_RX_M1 << GRF_GPIO2A1_SEL_SHIFT); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + default: + debug("uart id = %d iomux error!\n", uart_id); + break; + } +} + +static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, + int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->gpio0a_iomux, + GRF_GPIO0A7_SEL_MASK, + GRF_EMMC_DATA0 << GRF_GPIO0A7_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2d_iomux, + GRF_GPIO2D4_SEL_MASK, + GRF_EMMC_DATA123 << GRF_GPIO2D4_SEL_SHIFT); + rk_clrsetreg(&grf->gpio3c_iomux, + GRF_GPIO3C0_SEL_MASK, + GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD + << GRF_GPIO3C0_SEL_SHIFT); + break; + case PERIPH_ID_SDCARD: + /* sdcard iomux select m0 */ + rk_clrsetreg(&grf->com_iomux, + GRF_CARD_IOMUX_SEL_MASK, + GRF_CARD_IOMUX_SEL_M0 << GRF_CARD_IOMUX_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A7_SEL_MASK, + GRF_CARD_PWR_EN_M0 << GRF_GPIO2A7_SEL_SHIFT); + rk_clrsetreg(&grf->gpio1a_iomux, + GRF_GPIO1A0_SEL_MASK, + GRF_CARD_DATA_CLK_CMD_DETN + << GRF_GPIO1A0_SEL_SHIFT); + break; + default: + debug("mmc id = %d iomux error!\n", mmc_id); + break; + } +} + +static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + pinctrl_rk3328_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + pinctrl_rk3328_i2c_config(priv->grf, func); + break; + case PERIPH_ID_SPI0: + pinctrl_rk3328_spi_config(priv->grf, func, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + pinctrl_rk3328_uart_config(priv->grf, func); + break; + case PERIPH_ID_LCDC0: + case PERIPH_ID_LCDC1: + pinctrl_rk3328_lcdc_config(priv->grf, func); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk3328_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3328_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 49: + return PERIPH_ID_SPI0; + case 50: + return PERIPH_ID_PWM0; + case 36: + return PERIPH_ID_I2C0; + case 37: /* Note strange order */ + return PERIPH_ID_I2C1; + case 38: + return PERIPH_ID_I2C2; + case 39: + return PERIPH_ID_I2C3; + case 12: + return PERIPH_ID_SDCARD; + case 14: + return PERIPH_ID_EMMC; + } + + return -ENOENT; +} + +static int rk3328_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3328_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + + return rk3328_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk3328_pinctrl_ops = { + .set_state_simple = rk3328_pinctrl_set_state_simple, + .request = rk3328_pinctrl_request, + .get_periph_id = rk3328_pinctrl_get_periph_id, +}; + +static int rk3328_pinctrl_probe(struct udevice *dev) +{ + struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + + return ret; +} + +static const struct udevice_id rk3328_pinctrl_ids[] = { + { .compatible = "rockchip,rk3328-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3328) = { + .name = "rockchip_rk3328_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3328_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv), + .ops = &rk3328_pinctrl_ops, + .bind = dm_scan_fdt_dev, + .probe = rk3328_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index da301544c9..a74793aa48 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -22,112 +22,6 @@ struct rk3399_pinctrl_priv { struct rk3399_pmugrf_regs *pmugrf; }; -enum { - /* GRF_GPIO2B_IOMUX */ - GRF_GPIO2B1_SEL_SHIFT = 0, - GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT, - GRF_SPI2TPM_RXD = 1, - GRF_GPIO2B2_SEL_SHIFT = 2, - GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT, - GRF_SPI2TPM_TXD = 1, - GRF_GPIO2B3_SEL_SHIFT = 6, - GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT, - GRF_SPI2TPM_CLK = 1, - GRF_GPIO2B4_SEL_SHIFT = 8, - GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT, - GRF_SPI2TPM_CSN0 = 1, - - /* GRF_GPIO3A_IOMUX */ - GRF_GPIO3A4_SEL_SHIFT = 8, - GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, - GRF_SPI0NORCODEC_RXD = 2, - GRF_GPIO3A5_SEL_SHIFT = 10, - GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, - GRF_SPI0NORCODEC_TXD = 2, - GRF_GPIO3A6_SEL_SHIFT = 12, - GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, - GRF_SPI0NORCODEC_CLK = 2, - GRF_GPIO3A7_SEL_SHIFT = 14, - GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, - GRF_SPI0NORCODEC_CSN0 = 2, - - /* GRF_GPIO3B_IOMUX */ - GRF_GPIO3B0_SEL_SHIFT = 0, - GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, - GRF_SPI0NORCODEC_CSN1 = 2, - - /* GRF_GPIO4B_IOMUX */ - GRF_GPIO4B0_SEL_SHIFT = 0, - GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT, - GRF_SDMMC_DATA0 = 1, - GRF_UART2DBGA_SIN = 2, - GRF_GPIO4B1_SEL_SHIFT = 2, - GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT, - GRF_SDMMC_DATA1 = 1, - GRF_UART2DBGA_SOUT = 2, - GRF_GPIO4B2_SEL_SHIFT = 4, - GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT, - GRF_SDMMC_DATA2 = 1, - GRF_GPIO4B3_SEL_SHIFT = 6, - GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT, - GRF_SDMMC_DATA3 = 1, - GRF_GPIO4B4_SEL_SHIFT = 8, - GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT, - GRF_SDMMC_CLKOUT = 1, - GRF_GPIO4B5_SEL_SHIFT = 10, - GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT, - GRF_SDMMC_CMD = 1, - - /* GRF_GPIO4C_IOMUX */ - GRF_GPIO4C2_SEL_SHIFT = 4, - GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, - GRF_PWM_0 = 1, - GRF_GPIO4C3_SEL_SHIFT = 6, - GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, - GRF_UART2DGBC_SIN = 1, - GRF_GPIO4C4_SEL_SHIFT = 8, - GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, - GRF_UART2DBGC_SOUT = 1, - GRF_GPIO4C6_SEL_SHIFT = 12, - GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT, - GRF_PWM_1 = 1, - - /* PMUGRF_GPIO0A_IOMUX */ - PMUGRF_GPIO0A6_SEL_SHIFT = 12, - PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, - PMUGRF_PWM_3A = 1, - - /* PMUGRF_GPIO1A_IOMUX */ - PMUGRF_GPIO1A7_SEL_SHIFT = 14, - PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT, - PMUGRF_SPI1EC_RXD = 2, - - /* PMUGRF_GPIO1B_IOMUX */ - PMUGRF_GPIO1B0_SEL_SHIFT = 0, - PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT, - PMUGRF_SPI1EC_TXD = 2, - PMUGRF_GPIO1B1_SEL_SHIFT = 2, - PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT, - PMUGRF_SPI1EC_CLK = 2, - PMUGRF_GPIO1B2_SEL_SHIFT = 4, - PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT, - PMUGRF_SPI1EC_CSN0 = 2, - PMUGRF_GPIO1B6_SEL_SHIFT = 12, - PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT, - PMUGRF_PWM_3B = 1, - PMUGRF_GPIO1B7_SEL_SHIFT = 14, - PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT, - PMUGRF_I2C0PMU_SDA = 2, - - /* PMUGRF_GPIO1C_IOMUX */ - PMUGRF_GPIO1C0_SEL_SHIFT = 0, - PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT, - PMUGRF_I2C0PMU_SCL = 2, - PMUGRF_GPIO1C3_SEL_SHIFT = 6, - PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT, - PMUGRF_PWM_2 = 1, - -}; static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, struct rk3399_pmugrf_regs *pmugrf, int pwm_id) { @@ -359,6 +253,7 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) static int rk3399_pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) u32 cell[3]; int ret; @@ -389,7 +284,7 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev, case 65: return PERIPH_ID_SDMMC1; } - +#endif return -ENOENT; } @@ -434,6 +329,8 @@ U_BOOT_DRIVER(pinctrl_rk3399) = { .of_match = rk3399_pinctrl_ids, .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv), .ops = &rk3399_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) .bind = dm_scan_fdt_dev, +#endif .probe = rk3399_pinctrl_probe, }; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 7cb0eaab73..ca56a7e604 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -4,6 +4,15 @@ menu "Serial drivers" +config BAUDRATE + int "Default baudrate" + default 115200 + help + Select a default baudrate, where "default" has a driver-specific + meaning of either setting the baudrate for the early debug UART + in the SPL stage (most drivers) or for choosing a default baudrate + in the absence of an environment setting (serial_mxc.c). + config REQUIRE_SERIAL_CONSOLE bool "Require a serial port for console" # Running without a serial console is not supported by the diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index c06afc58f7..734cee2ba4 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -12,12 +12,19 @@ #include <serial.h> #include <asm/arch/clock.h> +#if defined(CONFIG_ROCKCHIP_RK3188) +struct rockchip_uart_platdata { + struct dtd_rockchip_rk3188_uart dtplat; + struct ns16550_platdata plat; +}; +struct dtd_rockchip_rk3188_uart *dtplat, s_dtplat; +#elif defined(CONFIG_ROCKCHIP_RK3288) struct rockchip_uart_platdata { struct dtd_rockchip_rk3288_uart dtplat; struct ns16550_platdata plat; }; - struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat; +#endif static int rockchip_serial_probe(struct udevice *dev) { @@ -33,6 +40,16 @@ static int rockchip_serial_probe(struct udevice *dev) return ns16550_serial_probe(dev); } +U_BOOT_DRIVER(rockchip_rk3188_uart) = { + .name = "rockchip_rk3188_uart", + .id = UCLASS_SERIAL, + .priv_auto_alloc_size = sizeof(struct NS16550), + .platdata_auto_alloc_size = sizeof(struct rockchip_uart_platdata), + .probe = rockchip_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + U_BOOT_DRIVER(rockchip_rk3288_uart) = { .name = "rockchip_rk3288_uart", .id = UCLASS_SERIAL, diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c index 592c0bde36..1907cef5b3 100644 --- a/drivers/serial/serial_stm32x7.c +++ b/drivers/serial/serial_stm32x7.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <clk.h> #include <dm.h> #include <asm/io.h> #include <serial.h> @@ -76,11 +77,49 @@ static int stm32_serial_probe(struct udevice *dev) { struct stm32x7_serial_platdata *plat = dev->platdata; struct stm32_usart *const usart = plat->base; + +#ifdef CONFIG_CLK + int ret; + struct clk clk; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } +#endif + setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); return 0; } +#if CONFIG_IS_ENABLED(OF_CONTROL) +static const struct udevice_id stm32_serial_id[] = { + {.compatible = "st,stm32-usart"}, + {.compatible = "st,stm32-uart"}, + {} +}; + +static int stm32_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct stm32x7_serial_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = (struct stm32_usart *)addr; + + return 0; +} +#endif + static const struct dm_serial_ops stm32_serial_ops = { .putc = stm32_serial_putc, .pending = stm32_serial_pending, @@ -91,6 +130,9 @@ static const struct dm_serial_ops stm32_serial_ops = { U_BOOT_DRIVER(serial_stm32) = { .name = "serial_stm32x7", .id = UCLASS_SERIAL, + .of_match = of_match_ptr(stm32_serial_id), + .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata), + .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata), .ops = &stm32_serial_ops, .probe = stm32_serial_probe, .flags = DM_FLAG_PRE_RELOC, diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 4f6e7e442f..a2967c03c7 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -15,7 +15,6 @@ #include <asm/io.h> #include <linux/compiler.h> #include <serial.h> -#include <asm/arch/clk.h> #include <asm/arch/hardware.h> DECLARE_GLOBAL_DATA_PTR; @@ -111,7 +110,6 @@ int zynq_serial_setbrg(struct udevice *dev, int baudrate) struct zynq_uart_priv *priv = dev_get_priv(dev); unsigned long clock; -#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK) int ret; struct clk clk; @@ -133,9 +131,7 @@ int zynq_serial_setbrg(struct udevice *dev, int baudrate) dev_err(dev, "failed to enable clock\n"); return ret; } -#else - clock = get_uart_clk(0); -#endif + _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); return 0; diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 21bcc21627..49b8bb61c6 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -9,7 +9,9 @@ obj-$(CONFIG_SYSRESET) += sysreset-uclass.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o endif +obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o diff --git a/drivers/sysreset/sysreset_rk3188.c b/drivers/sysreset/sysreset_rk3188.c new file mode 100644 index 0000000000..36ae47600a --- /dev/null +++ b/drivers/sysreset/sysreset_rk3188.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3188.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk3188_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + rk_clrreg(&cru->cru_mode_con, 0xffff); + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case SYSRESET_COLD: + rk_clrreg(&cru->cru_mode_con, 0xffff); + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk3188_sysreset = { + .request = rk3188_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk3188) = { + .name = "rk3188_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3188_sysreset, +}; diff --git a/drivers/sysreset/sysreset_rk3328.c b/drivers/sysreset/sysreset_rk3328.c new file mode 100644 index 0000000000..7b9af0925b --- /dev/null +++ b/drivers/sysreset/sysreset_rk3328.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3328.h> +#include <asm/arch/hardware.h> +#include <asm/io.h> +#include <linux/err.h> + +int rk3328_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk3328_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + writel(0xeca8, &cru->glb_srst_snd_value); + break; + case SYSRESET_COLD: + writel(0xfdb9, &cru->glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk3328_sysreset = { + .request = rk3328_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk3328) = { + .name = "rk3328_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3328_sysreset, +}; diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 7b0c43b858..c8608db23c 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -32,37 +32,37 @@ struct rk_hdmi_priv { static const struct tmds_n_cts n_cts_table[] = { { - .tmds = 25175, .n = 6144, .cts = 25175, + .tmds = 25175000, .n = 6144, .cts = 25175, }, { - .tmds = 25200, .n = 6144, .cts = 25200, + .tmds = 25200000, .n = 6144, .cts = 25200, }, { - .tmds = 27000, .n = 6144, .cts = 27000, + .tmds = 27000000, .n = 6144, .cts = 27000, }, { - .tmds = 27027, .n = 6144, .cts = 27027, + .tmds = 27027000, .n = 6144, .cts = 27027, }, { - .tmds = 40000, .n = 6144, .cts = 40000, + .tmds = 40000000, .n = 6144, .cts = 40000, }, { - .tmds = 54000, .n = 6144, .cts = 54000, + .tmds = 54000000, .n = 6144, .cts = 54000, }, { - .tmds = 54054, .n = 6144, .cts = 54054, + .tmds = 54054000, .n = 6144, .cts = 54054, }, { - .tmds = 65000, .n = 6144, .cts = 65000, + .tmds = 65000000, .n = 6144, .cts = 65000, }, { - .tmds = 74176, .n = 11648, .cts = 140625, + .tmds = 74176000, .n = 11648, .cts = 140625, }, { - .tmds = 74250, .n = 6144, .cts = 74250, + .tmds = 74250000, .n = 6144, .cts = 74250, }, { - .tmds = 83500, .n = 6144, .cts = 83500, + .tmds = 83500000, .n = 6144, .cts = 83500, }, { - .tmds = 106500, .n = 6144, .cts = 106500, + .tmds = 106500000, .n = 6144, .cts = 106500, }, { - .tmds = 108000, .n = 6144, .cts = 108000, + .tmds = 108000000, .n = 6144, .cts = 108000, }, { - .tmds = 148352, .n = 5824, .cts = 140625, + .tmds = 148352000, .n = 5824, .cts = 140625, }, { - .tmds = 148500, .n = 6144, .cts = 148500, + .tmds = 148500000, .n = 6144, .cts = 148500, }, { - .tmds = 297000, .n = 5120, .cts = 247500, + .tmds = 297000000, .n = 5120, .cts = 247500, } }; @@ -124,12 +124,6 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { } }; -static const u32 csc_coeff_default[3][4] = { - { 0x2000, 0x0000, 0x0000, 0x0000 }, - { 0x0000, 0x2000, 0x0000, 0x0000 }, - { 0x0000, 0x0000, 0x2000, 0x0000 } -}; - static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts) { uint cts3; @@ -220,37 +214,6 @@ static void hdmi_video_sample(struct rk3288_hdmi *regs) writel(0x0, ®s->tx_bcbdata1); } -static void hdmi_update_csc_coeffs(struct rk3288_hdmi *regs) -{ - u32 i, j; - u32 csc_scale = 1; - - /* the csc registers are sequential, alternating msb then lsb */ - for (i = 0; i < ARRAY_SIZE(csc_coeff_default); i++) { - for (j = 0; j < ARRAY_SIZE(csc_coeff_default[0]); j++) { - u32 coeff = csc_coeff_default[i][j]; - writel(coeff >> 8, ®s->csc_coef[i][j].msb); - writel(coeff && 0xff, ®s->csc_coef[i][j].lsb); - } - } - - clrsetbits_le32(®s->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, - csc_scale); -} - -static void hdmi_video_csc(struct rk3288_hdmi *regs) -{ - u32 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; - u32 interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; - - /* configure the csc registers */ - writel(interpolation, ®s->csc_cfg); - clrsetbits_le32(®s->csc_scale, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); - - hdmi_update_csc_coeffs(regs); -} - static void hdmi_video_packetize(struct rk3288_hdmi *regs) { u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; @@ -467,7 +430,6 @@ static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock) hdmi_phy_enable_tmds(regs, 0); hdmi_phy_enable_power(regs, 0); - /* enable csc */ ret = hdmi_phy_configure(regs, mpixelclock); if (ret) { debug("hdmi phy config failure %d\n", ret); @@ -837,7 +799,6 @@ static int rk_hdmi_enable(struct udevice *dev, int panel_bpp, hdmi_audio_set_samplerate(regs, edid->pixelclock.typ); hdmi_video_packetize(regs); - hdmi_video_csc(regs); hdmi_video_sample(regs); hdmi_clear_overflow(regs); diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e02863dc03..5b356dd231 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -127,5 +127,6 @@ typedef struct global_data { #define GD_FLG_SKIP_RELOC 0x00800 /* Don't relocate */ #define GD_FLG_RECORD 0x01000 /* Record console */ #define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag */ +#define GD_FLG_SPL_EARLY_INIT 0x04000 /* Early SPL init is done */ #endif /* __ASM_GENERIC_GBL_DATA_H */ diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 2cb8f5a09c..ea980e6511 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -17,7 +17,6 @@ /* * SERIAL */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_NS16550_MEM32 /* diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index b9f5439419..65271773f4 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -17,7 +17,6 @@ /* * SERIAL */ -#define CONFIG_BAUDRATE 115200 /* * CFI Flash diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 2a205cdf87..078b215450 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -770,9 +770,6 @@ unsigned long get_board_ddr_clk(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #define __USB_PHY_TYPE ulpi #ifdef CONFIG_ARCH_B4860 diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 282366c976..6f333e75ef 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -365,8 +365,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 969f448299..b23ec8fc8b 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -590,8 +590,6 @@ combinations. this should be removed later #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" -#define CONFIG_BAUDRATE 115200 - #ifdef CONFIG_SDCARD #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" #else diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 3af2425046..f95c3b9eeb 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -485,9 +485,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index ff46020842..bc5fa0394c 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -23,8 +23,6 @@ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ -#define CONFIG_BAUDRATE 9600 - #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 07dac8af21..feabc5fc09 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -28,8 +28,6 @@ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ -#define CONFIG_BAUDRATE 9600 - #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index b426c18b3b..f8b1d4af38 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -16,7 +16,6 @@ */ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 98ccbe3d92..126f889e97 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -22,7 +22,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 006222881a..7247111cf5 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -21,7 +21,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index d61c68ff5d..4ef83f7862 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -22,7 +22,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 273345772a..b1a49b07c3 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -13,7 +13,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG /* disable watchdog */ diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index 5cba541fe3..380221e732 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -14,7 +14,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG /* disable watchdog */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index a8589049fd..0b0e4e60c7 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -21,7 +21,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 1bdacbcdf8..5d324ba5bf 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -27,7 +27,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 62f25e9023..061a632c98 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -21,7 +21,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 03c18da52e..0c18b14c72 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -21,7 +21,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index fabbaf084d..46c50ea1f2 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -21,7 +21,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 8fb16bc294..0204cd5694 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -21,7 +21,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index cfa6c90ea8..cbe0d1ef63 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -22,7 +22,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 6a55e5743e..770472d8e0 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -22,7 +22,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 0eed59e0d6..db80871190 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -22,7 +22,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_WATCHDOG diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index f10c3f0b9f..2c31d99a62 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -21,7 +21,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_HW_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 2ae8d2534e..b9222e40d9 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -21,7 +21,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_HW_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index b59c53ef82..d362197ed5 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -92,7 +92,6 @@ /************************************************************** * Environment definitions **************************************************************/ -#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 4dbc2ba772..b9745f60f4 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -500,8 +500,6 @@ #define CONFIG_HAS_ETH1 #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 64a1467b10..32ca242f35 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -643,7 +643,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 800000 -#define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=" CONFIG_NETDEV "\0" \ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 01fa3aecb5..3093c56ec1 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -590,8 +590,6 @@ #define CONFIG_HAS_ETH1 #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 5226b7e124..d782fc3cf1 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -487,7 +487,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 800000 -#define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=" CONFIG_NETDEV "\0" \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 3aa1cc9f23..716fc3822e 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -561,8 +561,6 @@ #define CONFIG_HAS_ETH1 #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 0e094659d2..70ef1b80b1 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -725,8 +725,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 5f6fc8e5b4..ecad625098 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -356,7 +356,6 @@ boards, we say we have two, but don't display a message if we find only one. */ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CONSOLE ttyS0 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 7c1dcfbd9d..32274750a5 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -644,8 +644,6 @@ extern int board_pci_host_broken(void); #define CONFIG_HAS_ETH1 #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index a49b8115bb..5bd0d52135 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -668,7 +668,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 800000 -#define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=" CONFIG_NETDEV "\0" \ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index b9eab4e382..aeb9f0bbaf 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -674,8 +674,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 8fb16e9dd2..c5d581589a 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -378,8 +378,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 00a18b534a..4509a6d707 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -404,8 +404,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 5d76996865..8f7e056606 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -422,8 +422,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index c241b51487..df50fa3cce 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -523,8 +523,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 6faa2304c9..67093dfa31 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -400,8 +400,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index f27bdee156..8170b9f17d 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -208,8 +208,6 @@ #undef CONFIG_CONS_NONE /* define if console on something else */ #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} @@ -422,8 +420,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyCPM\0" \ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 4296ba7f8b..0bc71d4ae6 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -418,8 +418,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 91e17d9399..81d2d4f931 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -508,8 +508,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 3d4c8a8102..e6aca11e50 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -624,8 +624,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ "netdev=eth0\0" \ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 742714871d..0e9aaf4d66 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -485,8 +485,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #if defined(CONFIG_PCI1) #define PCI_ENV \ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 0e5bbc0012..4b932103a6 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -650,8 +650,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index 75c5af6508..7217426d3a 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -14,7 +14,6 @@ #define CONFIG_CMD_SDRAM -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 05a2360039..97a75709f9 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -793,8 +793,6 @@ extern unsigned long get_sdram_size(void); #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ "netdev=eth0\0" \ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index e601cc64bd..823eaf673f 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -655,9 +655,6 @@ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 58a3507dc1..787b8d206e 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -295,9 +295,6 @@ extern unsigned long get_clock_freq(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - /* Qman/Bman */ #define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 325baa29e3..c3e3fae44f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -652,9 +652,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/PATI.h b/include/configs/PATI.h index cb343e592e..2c048abba6 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -25,8 +25,6 @@ #define CONFIG_5xx_CONS_SCI1 #undef CONFIG_5xx_CONS_SCI2 -#define CONFIG_BAUDRATE 9600 - /* * BOOTP options */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index ab7ac2b122..b00cf8eeb2 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -86,7 +86,6 @@ /************************************************************** * Environment definitions **************************************************************/ -#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 397e933cf5..3fc3bb844a 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -26,8 +26,6 @@ #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ -#define CONFIG_BAUDRATE 9600 - #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 71adc110d8..5c3f56682c 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -18,8 +18,6 @@ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ -#define CONFIG_BAUDRATE 115200 - #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 59ba79e43b..1b059d4f58 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -85,7 +85,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index e850f54cb7..5b4ea141da 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -826,7 +826,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ -#define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 9a4af8021f..c9a848f6b1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -836,7 +836,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ -#define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi #ifdef CONFIG_ARCH_T1024 diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8343f371a7..0d60747dc8 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -716,9 +716,6 @@ unsigned long get_board_ddr_clk(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index bd1cfd4fcc..5107dc342d 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -847,9 +847,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #define __USB_PHY_TYPE utmi #define RAMDISKFILE "t104xrdb/ramdisk.uboot" diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 17daf1dbd1..a32ddeed1d 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -797,7 +797,6 @@ unsigned long get_board_ddr_clk(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index e3d57e6a9f..90ce554035 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -742,7 +742,6 @@ unsigned long get_board_ddr_clk(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index e8ac43c37a..cc1f79940c 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -317,8 +317,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BAUDRATE 115200 - #define CONFIG_HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 495fdc83b9..e5911d0d96 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -45,7 +45,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_BOOTCOUNT_LIMIT 1 diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index bd58247b70..61748ca412 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -32,7 +32,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 9d056cd8fb..4b9ef9f945 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -30,7 +30,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index af19a512a1..42a9f77e7c 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -478,8 +478,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 225b3a82b4..7edfab9050 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -25,7 +25,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index 022a9cab31..3931eba60e 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -25,7 +25,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index aa7704cb26..9b2ec372a9 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -25,7 +25,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 5efd69de66..b1b38e7388 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -25,7 +25,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index b7151b34be..dc2fe30e29 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -25,7 +25,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 9efe5d0f27..06c92851eb 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -25,7 +25,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index dc4dbaf885..aca58b1adf 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -28,7 +28,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 2c0cd827f9..371d19f4fd 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -28,7 +28,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index a7a1aa82d1..2906fcfca4 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -39,7 +39,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index 6722050e98..98cec3d8c9 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -35,7 +35,6 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_SYS_SMC_RXBUFLEN 128 #define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 8082ec5d7c..f1b72a329c 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -555,8 +555,6 @@ #define CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #if defined(CONFIG_DONGLE) #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 760a4bedaf..7e42115540 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ -#define CONFIG_BAUDRATE 9600 - #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index a0306cae55..60158f96d4 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -36,7 +36,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index f6bf931686..e07a782fec 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -32,7 +32,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* define to enable silent console */ #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index a7a6bfeaf5..ee015bb83d 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -312,8 +312,6 @@ #error CONFIG_PSC_CONSOLE must be 3 #endif -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ - #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index a2cdd71fd9..d557c42567 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -84,7 +84,6 @@ */ /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ -#define CONFIG_BAUDRATE 38400 #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index c05ee1cc04..14e9c06fac 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -90,7 +90,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Command definition */ #define CONFIG_CMD_BMODE diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 164beb1966..27126871f7 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -167,7 +167,6 @@ #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 7bf1f3bf59..2b61405345 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -92,7 +92,6 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Ethernet support */ #define CONFIG_PHYLIB diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index f676822404..c100fbc533 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -243,7 +243,6 @@ #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_INDEX 1 /* PMIC support */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index c277450fbc..710dac269c 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -63,7 +63,6 @@ #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 94087593e1..8be49af9f1 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -68,7 +68,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index f1584e4f5c..7490f2b5ea 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -65,7 +65,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 3d8b996054..d545e1b6a5 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -32,7 +32,6 @@ #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_OMAP_ABE_SYSCK diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 7974c53a0f..0f0fe4bedd 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 4a54cb6cb2..4f462d61e0 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -15,7 +15,6 @@ #define CONFIG_MCFTMR #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT 0 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_BOOTCOMMAND "bootm ffc20000" diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 88869fa6f7..8ae3c77942 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -24,7 +24,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 4f3742be2d..a2c31a2fd5 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -28,7 +28,6 @@ * Serial Port */ #define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index 053a184293..1cd4d32c6d 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -16,7 +16,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_IDE -#define CONFIG_BAUDRATE 38400 #define CONFIG_BOOTARGS "console=ttySC2,38400" #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h index c8857445ed..5f5882dc8e 100644 --- a/include/configs/ap_sh4a_4a.h +++ b/include/configs/ap_sh4a_4a.h @@ -19,7 +19,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_ENV -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC4,115200" #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index c5db7f2b6b..c0c575a490 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -10,7 +10,6 @@ #define __CONFIG_H #include "mx6_common.h" -#define CONFIG_SYS_THUMB_BUILD #undef CONFIG_DISPLAY_BOARDINFO #define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ @@ -145,7 +144,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Command definition */ #undef CONFIG_CMD_LOADB diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 513f9ee69f..82898bfa13 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -200,7 +200,6 @@ */ #define CONFIG_MXC_UART #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 #define CONFIG_MXC_UART_BASE UART1_BASE /* diff --git a/include/configs/aria.h b/include/configs/aria.h index d408d545c1..94f6605d46 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -309,7 +309,6 @@ #error CONFIG_PSC_CONSOLE must be 3 #endif -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} @@ -497,8 +496,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 361ada1fc7..7e81c5e349 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -21,7 +21,6 @@ #define BOARD_LATE_INIT -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "" #undef CONFIG_SHOW_BOOT_PROGRESS diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index 93b57d46c0..f786ffae3e 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -43,7 +43,6 @@ /* * NS16550 Configuration */ -#define CONFIG_BAUDRATE 115200 /* * BOOTP options diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index e8dca0b2cc..4e3e5589f9 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -103,8 +103,6 @@ * in u-boot command interface */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (2) #define CONFIG_SYS_UART2_ALT3_GPIO diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 42410a8526..3e979482f6 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -99,8 +99,6 @@ #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_LONGHELP diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 9dc33939ce..53e191a312 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -110,8 +110,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0/* ignored in arm */ -#define CONFIG_BAUDRATE 115200 - /* * Command line configuration. */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index f12e16cc43..379f234463 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -52,7 +52,6 @@ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 /* LED */ #define CONFIG_AT91_LED diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 263e92bd33..0afc92c91d 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -44,7 +44,6 @@ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 /* LCD */ #define LCD_BPP LCD_COLOR8 diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index f9d4043a71..5194131243 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -52,7 +52,6 @@ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 /* LCD */ #define LCD_BPP LCD_COLOR8 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 1ea3231cfb..0708d53662 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -155,8 +155,6 @@ "bootz 0x72000000 - 0x71000000" #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_LONGHELP diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 339f53f558..872d471d05 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -35,7 +35,6 @@ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 /* LCD */ #define LCD_BPP LCD_COLOR16 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 7fbbd54942..8752f1f3b6 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -40,7 +40,6 @@ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 /* LCD */ #define LCD_BPP LCD_COLOR8 diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 730b9807db..c81003e311 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -191,8 +191,6 @@ "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw" #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_LONGHELP diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index d966e1c2a0..708f0320cf 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -54,7 +54,6 @@ #define CONFIG_STACKSIZE (2048) -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index 8a9215e8a8..aa308483a2 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -73,7 +73,6 @@ #define CONFIG_STACKSIZE (2048) -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ "root=mtd:main rootfstype=jffs2" #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index c9a36bc774..771a35ab2b 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -71,7 +71,6 @@ #define CONFIG_STACKSIZE (2048) -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1" diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index c055c1aab6..d60db65fd2 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -52,7 +52,6 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33333333 #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_BAUDRATE 115200 /* * I2C configuration diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 65c4470dc2..37c71bb433 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -228,7 +228,6 @@ #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index fc9dc9c825..d5347e626f 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -329,7 +329,6 @@ DEFAULT_LINUX_BOOT_ENV \ #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h index ce1b89db42..65e9e32f3e 100644 --- a/include/configs/bcm23550_w1d.h +++ b/include/configs/bcm23550_w1d.h @@ -81,8 +81,6 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 0x3e000000 -#define CONFIG_BAUDRATE 115200 - /* must fit into GPT:u-boot-env partition */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index 5001ca6882..2d9b0a878d 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -80,8 +80,6 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 0x3e000000 -#define CONFIG_BAUDRATE 115200 - /* must fit into GPT:u-boot-env partition */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index 09b7351844..868b0a85d4 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -46,8 +46,6 @@ /* Serial Info */ #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_BAUDRATE 115200 - #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_IS_NOWHERE diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index de60bb1035..b96580370d 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -120,7 +120,6 @@ #define CONFIG_LOADADDR 0x800000 #define CONFIG_MISC_INIT_R #define CONFIG_UART_CONSOLE 0 -#define CONFIG_BAUDRATE 115200 #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h index 6cad00fd7c..b517af392c 100644 --- a/include/configs/bf506f-ezkit.h +++ b/include/configs/bf506f-ezkit.h @@ -80,7 +80,6 @@ #define CONFIG_ICACHE_OFF #define CONFIG_DCACHE_OFF #define CONFIG_UART_CONSOLE 0 -#define CONFIG_BAUDRATE 115200 #define CONFIG_BFIN_SERIAL #undef CONFIG_GZIP diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h index b58c1db960..1c1a08f6fc 100644 --- a/include/configs/bf525-ucr2.h +++ b/include/configs/bf525-ucr2.h @@ -78,7 +78,6 @@ */ #define CONFIG_UART_CONSOLE 0 -#define CONFIG_BAUDRATE 115200 #define CONFIG_BFIN_SERIAL #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" #define CONFIG_BOOTCOMMAND "run sfboot" diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index cabbe37121..5d57b80c7b 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -114,7 +114,6 @@ #define CONFIG_CMDLINE_EDITING 1 #define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_BAUDRATE 57600 #define CONFIG_UART_CONSOLE 0 #define CONFIG_BFIN_SERIAL diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index bced1df12c..6d80592dc2 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -135,7 +135,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 4b23aa8ab8..3b69e58dc6 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -114,7 +114,6 @@ #define CONFIG_CMDLINE_EDITING 1 #define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 #define CONFIG_BFIN_SERIAL diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index 3a4631e4fe..bf2d7b6a8b 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -134,7 +134,6 @@ * Misc Settings */ #define CONFIG_UART_CONSOLE 0 -#define CONFIG_BAUDRATE 57600 /* * Pull in common ADI header for remaining command/environment setup diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 5d61f99871..a915b1a2ef 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -75,9 +75,6 @@ #define CONFIG_AUTO_COMPLETE 1 #define CONFIG_LOADS_ECHO 1 #define CONFIG_JTAG_CONSOLE -#ifndef CONFIG_BAUDRATE -# define CONFIG_BAUDRATE 57600 -#endif #ifdef CONFIG_UART_CONSOLE # define CONFIG_BFIN_SERIAL #endif diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index 5044f73b06..4f65a1dec8 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -172,7 +172,6 @@ /* * Console settings */ -#define CONFIG_BAUDRATE 57600 #define CONFIG_LOADS_ECHO 1 #define CONFIG_UART_CONSOLE 0 #define CONFIG_BFIN_SERIAL diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h index 0b8f4c0428..fe823ba4c7 100644 --- a/include/configs/blackvme.h +++ b/include/configs/blackvme.h @@ -160,7 +160,6 @@ /* * Console settings */ -#define CONFIG_BAUDRATE 57600 #define CONFIG_LOADS_ECHO 1 #define CONFIG_UART_CONSOLE 0 #define CONFIG_BFIN_SERIAL diff --git a/include/configs/boston.h b/include/configs/boston.h index aad87c6f37..1915ad5249 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP -#define CONFIG_BAUDRATE 115200 /* * Flash diff --git a/include/configs/br4.h b/include/configs/br4.h index 64b379a979..8a7a359347 100644 --- a/include/configs/br4.h +++ b/include/configs/br4.h @@ -110,7 +110,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 #define CONFIG_BOOTCOMMAND "run nandboot" diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 9a39f488bd..e2da016f47 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -29,7 +29,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_BAUDRATE 115200 /* Network defines */ #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ diff --git a/include/configs/calimain.h b/include/configs/calimain.h index e990dedc9f..a4ff1e8995 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -153,7 +153,6 @@ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_FLASH_CFI_DRIVER diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 684695f788..6cd66f28bd 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -33,7 +33,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index 04ee3a1d3c..c1669fa788 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -120,7 +120,6 @@ #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_BAUDRATE 115200 /* PMIC support */ #define CONFIG_POWER_TPS65217 diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h index e1f724bf2e..a4950f39e3 100644 --- a/include/configs/cl-som-am57x.h +++ b/include/configs/cl-som-am57x.h @@ -18,7 +18,6 @@ #define CONSOLEDEV "ttyO2" #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ #define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_OMAP_ABE_SYSCK diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index 0b31dc95d7..3b6f9baa5d 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -109,7 +109,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h index 7039cbaaea..01a3579974 100644 --- a/include/configs/cm-bf533.h +++ b/include/configs/cm-bf533.h @@ -84,7 +84,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 #define CONFIG_BOOTCOMMAND "run flashboot" #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index cc31a30dbb..d9f91b5b9a 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -123,7 +123,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index 282eb4f0b2..af11ebe5f8 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -121,7 +121,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index 02a46cae3d..10e8efde5d 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -101,7 +101,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 1 #define CONFIG_BOOTCOMMAND "run flashboot" diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 3860e0e258..ac1646cf71 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -86,7 +86,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 #define CONFIG_BOOTCOMMAND "run flashboot" #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index b3a98dfa63..51a5f6dce7 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -31,7 +31,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 0dad9c3bd7..45511be282 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -41,7 +41,6 @@ /* Serial console */ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART4_BASE -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} /* Shell */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 2898f47e83..69137bc6e8 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -92,7 +92,6 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_BAUDRATE 115200 /* I2C Configuration */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index e8b79a256b..8e6571b9f0 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -72,7 +72,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index c179a2b5b8..55d4786fd8 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -77,7 +77,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index 952538d5a1..477aa07bd8 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -28,7 +28,6 @@ /* UART setup */ #define CONFIG_CONS_INDEX 4 #define CONFIG_SYS_NS16550_COM4 UART4_BASE -#define CONFIG_BAUDRATE 115200 /* MMC ENV related defines */ #undef CONFIG_ENV_OFFSET diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 0e8d4ac38b..b078e10475 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -52,7 +52,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 19200 /* --- * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 924b40fea5..0b58e5b9f5 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -10,7 +10,6 @@ #define __CONFIG_H #include "mx6_common.h" -#define CONFIG_SYS_THUMB_BUILD #undef CONFIG_DISPLAY_BOARDINFO #define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ @@ -126,7 +125,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Command definition */ #undef CONFIG_CMD_LOADB diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index a0b18d2269..2c9c0142bb 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -14,8 +14,6 @@ #include "mx7_common.h" -#define CONFIG_SYS_THUMB_BUILD - /*#define CONFIG_DBG_MONITOR*/ #define PHYS_SDRAM_SIZE SZ_512M diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 4f05fab440..015f98241e 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -47,7 +47,6 @@ /* * Serial Console Configuration */ -#define CONFIG_BAUDRATE 115200 /* * Bootloader Components Configuration diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 6d05f930d3..888899eacb 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -14,7 +14,6 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_FSL_CLK #define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ @@ -33,7 +32,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -#define CONFIG_BAUDRATE 115200 /* NAND support */ #define CONFIG_CMD_NAND diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 5bd66d8455..1bd3195ff1 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -384,9 +384,6 @@ */ #ifdef CONFIG_TRAILBLAZER - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "mp_holdoff=1\0" @@ -399,9 +396,6 @@ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f810d34848..f42ba795ea 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -663,9 +663,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #ifdef CONFIG_TARGET_P4080DS #define __USB_PHY_TYPE ulpi #else diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 3a01a2b48a..bb1d0d7715 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -127,8 +127,6 @@ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "root=/dev/mtdblock7 rw rootfstype=jffs2" -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 0f0a075508..dfeee513a4 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -479,9 +479,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 42f54ef759..3ce905859e 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -135,7 +135,6 @@ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SPI #define CONFIG_DAVINCI_SPI diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index ad7667eb23..04372962f6 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -35,9 +35,6 @@ #endif #endif - -#define CONFIG_BAUDRATE 115200 - /* valid baudrates */ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 9c7afa5005..6e95064fe1 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -41,7 +41,6 @@ * Serial Driver */ #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ -#define CONFIG_BAUDRATE 115200 /* * DMA diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index d6803c5422..71068a8ae3 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -41,7 +41,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h index 0a7bc8a08b..1690dda519 100644 --- a/include/configs/dnp5370.h +++ b/include/configs/dnp5370.h @@ -101,7 +101,6 @@ #define CONFIG_UART_CONSOLE 0 #define CONFIG_BFIN_SERIAL -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTCOMMAND "bootm 0x20030000" #define CONFIG_BOOTARGS "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2" diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 549439e8b4..43e74a29e9 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_OMAP_ABE_SYSCK diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 7f0742abbb..b97c6c4240 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */ /* UART */ -#define CONFIG_BAUDRATE 115200 /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 19000000 @@ -46,12 +45,8 @@ #define CONFIG_USB_ETHER_MCS7830 #define CONFIG_USB_ETHER_SMSC95XX -/* Libraries */ -#define CONFIG_MD5 - /* Extra Commands */ #define CONFIG_CMD_ENV -#define CONFIG_CMD_MD5SUM /* Enable that for switching of boot partitions */ /* Disabled by default as some sub-commands can brick eMMC */ /*#define CONFIG_SUPPORT_EMMC_BOOT */ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index a9eb6bcb80..a7b2dc82e1 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -59,7 +59,6 @@ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SPI #define CONFIG_DAVINCI_SPI diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index dc08db681f..edd948522e 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -19,7 +19,6 @@ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index 591028eec2..f8fb97b08e 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -31,7 +31,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_ENV -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index 774d3296ab..99f0daece3 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -91,7 +91,6 @@ /* Serial port hardware configuration */ #define CONFIG_PL010_SERIAL #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \ 115200, 230400} #define CONFIG_SYS_SERIAL0 0x808C0000 diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 175adbddc6..f7ac3027dd 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -90,7 +90,6 @@ */ #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 2f4219fff6..afb5b73899 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -55,7 +55,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_MXC_UART_BASE UART2_BASE -#define CONFIG_BAUDRATE 115200 /* Command definition */ diff --git a/include/configs/espt.h b/include/configs/espt.h index 9475740fef..ace71862dd 100644 --- a/include/configs/espt.h +++ b/include/configs/espt.h @@ -28,7 +28,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE 1 -#define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_SCIF0 1 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 55d65ef7e8..b83eb45111 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -77,7 +77,6 @@ /* Serial port */ #define CONFIG_ATMEL_USART #define CONFIG_USART3 /* USART 3 is DBGU */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h new file mode 100644 index 0000000000..3a39a1bffe --- /dev/null +++ b/include/configs/evb_rk3328.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EVB_RK3328_H +#define __EVB_RK3328_H + +#include <configs/rk3328_common.h> + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* + * SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 7a40c98888..b4f75302db 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -34,7 +34,6 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) /* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 /* SD/MMC configuration */ #define CONFIG_BOUNCE_BUFFER diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 12ceb2c266..5411e5ff49 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -40,7 +40,6 @@ #define INFORM3_OFFSET 0x80c /* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 #define CONFIG_CMD_HASH diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index 822654351c..b4b034fb35 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 /* Timer input clock frequency */ #define COUNTER_FREQUENCY 24000000 @@ -49,7 +48,6 @@ #define CONFIG_CORE_COUNT 0x8 /* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) diff --git a/include/configs/flea3.h b/include/configs/flea3.h index fa2fcb1ec7..0ab33953ac 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -59,7 +59,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* * Command definition diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index d8af90d9d0..f86e20caa2 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -113,7 +113,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Command definition */ #define CONFIG_CMD_BMODE diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index c2655552f1..2c8adabc18 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -45,7 +45,6 @@ /* * Serial console configuration */ -#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* Partitions */ diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index 0d513c5519..2edb1b0ed5 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -39,7 +39,6 @@ /* * Serial console configuration */ -#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* Partitions */ diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h index 20eeab33d9..b8ac7d1d78 100644 --- a/include/configs/gr_xc3s_1500.h +++ b/include/configs/gr_xc3s_1500.h @@ -26,7 +26,6 @@ /* * Serial console configuration */ -#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* Partitions */ diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h index b727314c90..d7b9c18c89 100644 --- a/include/configs/grasshopper.h +++ b/include/configs/grasshopper.h @@ -71,8 +71,6 @@ #define CONFIG_STACKSIZE (2048) -#define CONFIG_BAUDRATE 115200 - /* * After booting the board for the first time, new ethernet addresses diff --git a/include/configs/grsim.h b/include/configs/grsim.h index 18b8d3cbcb..4594b131ac 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -37,7 +37,6 @@ /* * Serial console configuration */ -#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* Partitions */ diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index ba570c38a9..ea9e3e8877 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -32,7 +32,6 @@ /* * Serial console configuration */ -#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* Partitions */ diff --git a/include/configs/h2200.h b/include/configs/h2200.h index 0891b02d35..d8724f86a7 100644 --- a/include/configs/h2200.h +++ b/include/configs/h2200.h @@ -107,7 +107,6 @@ #define CONFIG_FFUART #define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 } #define CONFIG_FIT_DISABLE_SHA256 diff --git a/include/configs/highbank.h b/include/configs/highbank.h index b47624ad3f..e15b572e41 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -10,7 +10,6 @@ #include <config_distro_defaults.h> #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_BOOTMAPSZ (16 << 20) @@ -28,8 +27,6 @@ #define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) } #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 - #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_SYS_BOOTCOUNT_SINGLEWORD #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index d3492d5770..4cdb27ccec 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -52,7 +52,6 @@ /* Serial port PL010/PL011 through the device model */ #define CONFIG_PL01X_SERIAL -#define CONFIG_BAUDRATE 115200 #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2 diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 9f5029a122..5574e7715a 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -596,8 +596,6 @@ void fpga_control_clear(unsigned int bus, int pin); #define CONFIG_HAS_ETH0 #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 112e8856b0..e2c2552e7c 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -449,8 +449,6 @@ #define CONFIG_CMD_ENV_FLAGS #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" -#define CONFIG_BAUDRATE 115200 - /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h index e5f682c874..6310423335 100644 --- a/include/configs/imgtec_xilfpga.h +++ b/include/configs/imgtec_xilfpga.h @@ -47,7 +47,6 @@ */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ -#define CONFIG_BAUDRATE 115200 /* ------------------------------------------------- * Environment diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index cbd1dbc9c1..db745b28a7 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -85,7 +85,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ /* * Flash & Environment diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 5d0702f683..ae5009a556 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -44,7 +44,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /*********************************************************** * Command definition diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index c5a035fccf..4598d272d5 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -24,7 +24,6 @@ * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 * or 64KB */ -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x00908000 #define CONFIG_SPL_MAX_SIZE 0x10000 @@ -45,14 +44,12 @@ #if defined(CONFIG_SPL_MMC_SUPPORT) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* SATA support */ #if defined(CONFIG_SPL_SATA_SUPPORT) #define CONFIG_SPL_SATA_BOOT_DEVICE 0 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* Define the payload for FAT/EXT support */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index b2131e88ee..c3e1cae6cb 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -39,7 +39,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index b95851a224..dca60dfddd 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -21,7 +21,6 @@ /* Serial port PL010/PL011 through the device model */ #define CONFIG_PL01X_SERIAL -#define CONFIG_BAUDRATE 38400 #define CONFIG_CONS_INDEX 0 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ diff --git a/include/configs/ip04.h b/include/configs/ip04.h index ff8d432950..1531feb83d 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -116,7 +116,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_UART_CONSOLE 0 #undef CONFIG_SHOW_BOOT_PROGRESS diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h index d0316221b0..41e7dca653 100644 --- a/include/configs/ipam390.h +++ b/include/configs/ipam390.h @@ -134,7 +134,6 @@ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ /* * Flash & Environment diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index 1aeded18f5..a99e928e2e 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -35,7 +35,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 44345ddf8c..0d97317c7f 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -35,7 +35,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* diff --git a/include/configs/kc1.h b/include/configs/kc1.h index cc78a09f6a..85bc0e3fb7 100644 --- a/include/configs/kc1.h +++ b/include/configs/kc1.h @@ -16,8 +16,6 @@ * Build */ -#define CONFIG_SYS_THUMB_BUILD - /* * CPU */ @@ -130,7 +128,6 @@ #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ 115200 } diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 4ab96bf939..24830ee6ee 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_LOADS_ECHO diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index a193688f9d..feb3eec446 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -23,7 +23,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200" #undef CONFIG_SHOW_BOOT_PROGRESS diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 0435124a43..07f42e3496 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -122,7 +122,6 @@ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */ #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SPI #define CONFIG_DAVINCI_SPI diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index e556c925fe..af076725ba 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -81,7 +81,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* Command line configuration */ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 2fc3fe9dce..db29fa2ba1 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_BAUDRATE 115200 /* * I2C diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6b640c4fc1..4fb8b0ca8c 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -365,8 +365,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif -#define CONFIG_BAUDRATE 115200 - /* * I2C */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 7279c89db5..c6438d5ec6 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -133,9 +133,9 @@ * size increases then increase this size in case of secure boot as * it uses raw u-boot image instead of fit image. */ -#define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) #else -#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x100000 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ #endif @@ -264,8 +264,6 @@ #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif -#define CONFIG_BAUDRATE 115200 - /* * I2C */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 9a01e485d8..5a5f9516e3 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* SD boot SPL */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index f3b521d705..6a345c0400 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -38,7 +38,9 @@ unsigned long get_board_ddr_clk(void); #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 +#ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#endif #define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 8fa3bb3a64..f185380ae3 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -29,7 +29,9 @@ #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_FSL_DDR_BIST +#ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#endif #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 8ec12474f6..1ed7517e01 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -41,7 +41,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* SD boot SPL */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index cba22ca2b6..4b3b21eaa1 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -38,7 +38,9 @@ unsigned long get_board_ddr_clk(void); #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 +#ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#endif #define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index a96aa650f7..2141b8299a 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -34,7 +34,9 @@ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +#ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4ba273aeef..5072e20811 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -91,7 +91,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* IFC */ @@ -141,7 +140,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 /* MC firmware */ -#define CONFIG_FSL_MC_ENET /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 @@ -159,7 +157,6 @@ unsigned long long get_qixis_addr(void); */ #ifdef CONFIG_FSL_MC_ENET #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) -#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif /* Command line configuration */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 9bca8ac484..70e75880cf 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -99,7 +99,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 56fb6020f4..a70f041b2d 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -73,7 +73,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* * MMC Driver diff --git a/include/configs/malta.h b/include/configs/malta.h index 103360d248..14298f56b9 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -63,7 +63,6 @@ /* * Serial driver */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_NS16550_PORT_MAPPED /* diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 06c1a9543b..6894c0b4b8 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -72,7 +72,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index dadf438ac8..dbb242696b 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -215,7 +215,6 @@ #if CONFIG_PSC_CONSOLE != 3 #error CONFIG_PSC_CONSOLE must be 3 #endif -#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 63881c5e6f..3a8e82edbf 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -56,7 +56,6 @@ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 /* * BOOTP options diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 370481b8cf..e8fe2f673c 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -32,7 +32,6 @@ #endif /* uart */ -# define CONFIG_BAUDRATE 115200 /* The following table includes the supported baudrates */ # define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index ab1d9f1651..7ebcd03872 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -47,7 +47,6 @@ */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ #define CONFIG_NETCONSOLE 1 /* network console */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* diff --git a/include/configs/mpc5121-common.h b/include/configs/mpc5121-common.h index f06ca9c6af..d252297e89 100644 --- a/include/configs/mpc5121-common.h +++ b/include/configs/mpc5121-common.h @@ -24,7 +24,6 @@ /* * Serial console */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index fe9a703b64..1714a9bec8 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -274,7 +274,6 @@ #if CONFIG_PSC_CONSOLE != 3 #error CONFIG_PSC_CONSOLE must be 3 #endif -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} @@ -503,8 +502,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 76667d7703..b865d9f916 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -465,8 +465,6 @@ #define CONFIG_HAS_ETH1 #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h index 0d37912af7..df8ffe29d0 100644 --- a/include/configs/mpr2.h +++ b/include/configs/mpr2.h @@ -13,7 +13,6 @@ /* Supported commands */ /* Default environment variables */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_BOOTFILE "/boot/zImage" #define CONFIG_LOADADDR 0x8E000000 diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index e074350309..0015be980b 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -16,7 +16,6 @@ #define CONFIG_CMD_PCMCIA #define CONFIG_CMD_IDE -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_BOOTFILE "/boot/zImage" #define CONFIG_LOADADDR 0x8E000000 diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 181d02198d..26472e9474 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -15,7 +15,6 @@ #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_SDRAM -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index dfa03fc4c1..394ce6cd38 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -21,7 +21,6 @@ * Command line configuration. */ #define CONFIG_SCIF_CONSOLE 1 -#define CONFIG_BAUDRATE 38400 #define CONFIG_CONS_SCIF1 1 #define CONFIG_BOOTARGS "console=ttySC0,38400" diff --git a/include/configs/munices.h b/include/configs/munices.h index 5a6d004d07..1679430951 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -37,7 +37,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 25562fa12a..814f0dd7ca 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -53,7 +53,6 @@ */ #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200,230400, 460800, 921600 } /* auto boot */ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index db1ba0de65..a8a9d15b5e 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -24,7 +24,6 @@ /* auto boot */ #define CONFIG_PREBOOT -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } diff --git a/include/configs/mvebu_db-88f3720.h b/include/configs/mvebu_db-88f3720.h index 753ed1e396..6bb78e09b1 100644 --- a/include/configs/mvebu_db-88f3720.h +++ b/include/configs/mvebu_db-88f3720.h @@ -22,7 +22,6 @@ /* auto boot */ #define CONFIG_PREBOOT -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index f787376221..4cee64da96 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -52,7 +52,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ /* No NOR flash present */ #define CONFIG_ENV_OFFSET (6 * 64 * 1024) diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index ce4936d01c..6ab822e58b 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -54,7 +54,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /*********************************************************** * Command definition diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index f0cdebe340..920507007b 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -68,7 +68,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /*********************************************************** * Command definition diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 22d319aceb..9683a6511a 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -69,7 +69,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* * Command definition diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 292fa86162..98c9f9bbf6 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -96,7 +96,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /*********************************************************** * Command definition diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index d67ba851c7..8612614437 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -59,7 +59,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Command definition */ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index a103ee47ab..3094402d15 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -59,7 +59,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Command definition */ #define CONFIG_SUPPORT_RAW_INITRD diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 251b6f0c37..b3519ae7e7 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -65,7 +65,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Command definition */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 7cd750c72a..fed40eb58d 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -73,7 +73,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Command definition */ #define CONFIG_SUPPORT_RAW_INITRD diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index e7c3a1dcc2..e9d570e1d7 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -53,7 +53,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Command definition */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index afe9b9340e..c841ca9115 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -54,7 +54,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Filesystems and image support */ #define CONFIG_SUPPORT_RAW_INITRD diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index b10b7f1b77..5bf8ad74b8 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -35,7 +35,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 12b456b3bd..fdf596f82f 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -114,9 +114,6 @@ #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } #define CONFIG_CONS_INDEX 0 /* Default baudrate can be overridden by board! */ -#ifndef CONFIG_BAUDRATE -#define CONFIG_BAUDRATE 115200 -#endif /* FEC Ethernet on SoC */ #ifdef CONFIG_FEC_MXC diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 5b0cb2ef50..6b128df464 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -87,7 +87,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } /* USB */ diff --git a/include/configs/nsim.h b/include/configs/nsim.h index e8049162e0..0cc55b7bed 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -36,7 +36,6 @@ */ #define CONFIG_ARC_SERIAL #define CONFIG_ARC_UART_BASE 0xC0FC1000 -#define CONFIG_BAUDRATE 115200 /* * Command line configuration diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index 8a414c3b9a..1470c513a3 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -40,7 +40,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400 } diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h index 48f4a68549..117c0e418a 100644 --- a/include/configs/odroid-c2.h +++ b/include/configs/odroid-c2.h @@ -12,7 +12,6 @@ /* Serial setup */ #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 #define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0" diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 2828f070d7..6cc7dd16a2 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -40,7 +40,6 @@ /* select serial console configuration */ #define CONFIG_SERIAL1 -#define CONFIG_BAUDRATE 115200 /* Console configuration */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index a28f9ba8f4..329dc73221 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -148,7 +148,6 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index df60b49c61..533bb02c5e 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -31,7 +31,6 @@ #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 UART3_BASE -#define CONFIG_BAUDRATE 115200 #define CONFIG_MISC_INIT_R /* MMC ENV related defines */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 76d66a0590..6700073aa2 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -127,7 +127,6 @@ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SPI diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 14cf3b43a2..19660db080 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -21,7 +21,6 @@ #define CONFIG_KW88F6281 1 /* SOC Name */ #define CONFIG_MACH_OPENRD_BASE /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_SYS_THUMB_BUILD /* * Commands configuration diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h index 7b2ce789cc..549b33c074 100644 --- a/include/configs/openrisc-generic.h +++ b/include/configs/openrisc-generic.h @@ -35,7 +35,6 @@ # define CONFIG_SYS_NS16550_COM1 (0x90000000) # define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ -#define CONFIG_BAUDRATE CONFIG_SYS_UART_BAUD #define CONFIG_SYS_BAUDRATE_TABLE {CONFIG_BAUDRATE} #define CONSOLE_ARG "console=console=ttyS0,115200\0" diff --git a/include/configs/origen.h b/include/configs/origen.h index 26fe4024b6..6980e9e548 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -34,7 +34,6 @@ /* select serial console configuration */ #define CONFIG_SERIAL2 -#define CONFIG_BAUDRATE 115200 /* Console configuration */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 88876d639e..479f45db02 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -884,8 +884,6 @@ #define CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #ifdef __SW_BOOT_NOR #define __NOR_RST_CMD \ norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index d403f84617..dad0616517 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -446,8 +446,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 10d39e0a29..504ddf729b 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -29,9 +29,6 @@ #endif #endif - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_TIMESTAMP /* Print image info with timestamp */ #undef CONFIG_BOOTARGS diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h index 47ded819c3..87aa9dc988 100644 --- a/include/configs/pcm030.h +++ b/include/configs/pcm030.h @@ -44,7 +44,6 @@ Serial console configuration /*define gps port conf. */ /* register later on to */ /*enable UART function! */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index ba3b9750de..286598d2de 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -11,8 +11,6 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_SYS_THUMB_BUILD - #define CONFIG_SKIP_LOWLEVEL_INIT /* Enable passing of ATAGs */ @@ -23,7 +21,6 @@ /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 /* NAND support */ #define CONFIG_CMD_NAND diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 34f88e51c7..b8fb371827 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -104,7 +104,6 @@ /* NS16550 Configuration: primary UART via FTDI */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 -#define CONFIG_BAUDRATE 115200 /* I2C Configuration */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 6c7539f04a..dacb78ab69 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -59,7 +59,6 @@ /*------------------------------------------------------------ * Console Configuration */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ #define CONFIG_SYS_PBSIZE \ diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h index 762308991e..61c4b98b1d 100644 --- a/include/configs/picosam9g45.h +++ b/include/configs/picosam9g45.h @@ -129,8 +129,6 @@ "bootz 0x22000000 - 0x21000000" #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 79b35d708e..ca1404ae9f 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -319,8 +319,6 @@ #error "Undefined memory device" #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE \ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index ffea8c667b..52791bce55 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -353,8 +353,6 @@ #error "Undefined memory device" #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE \ diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index c3a07f7352..22b3c2e2d1 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -133,8 +133,6 @@ "2M(linux)ro,-(root) rw " \ "rootfstype=jffs2" -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/pr1.h b/include/configs/pr1.h index 500d7156c7..d3fba0d3ff 100644 --- a/include/configs/pr1.h +++ b/include/configs/pr1.h @@ -110,7 +110,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 #define CONFIG_BOOTCOMMAND "run nandboot" diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 6fdf50bd26..be7f4f2487 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -16,9 +16,6 @@ #define CONFIG_MISC_INIT_R - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_TIMESTAMP /* Print image info with timestamp */ #undef CONFIG_BOOTARGS diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 4ad230cb82..39afbff2d8 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -16,9 +16,6 @@ #define CONFIG_MISC_INIT_R - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_TIMESTAMP /* Print image info with timestamp */ #undef CONFIG_BOOTARGS diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 234fc694d9..ffd776f6bf 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -163,8 +163,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BAUDRATE 115200 - #define CONFIG_BOOTCOMMAND \ "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0" diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h index 1ac15e27b7..642572fc95 100644 --- a/include/configs/r0p7734.h +++ b/include/configs/r0p7734.h @@ -19,7 +19,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_ENV -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC3,115200" #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index d37b39d3e8..64fc5b2f03 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -17,7 +17,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE 1 -#define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_SCIF1 1 #define CONFIG_BOOTARGS "console=ttySC0,115200" diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 9322f276fd..2efe36f854 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -25,7 +25,6 @@ #define CONFIG_CMD_IDE #define CONFIG_SCIF_CONSOLE 1 -#define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_SCIF0 1 #define CONFIG_BOOTARGS "console=ttySC0,115200" diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 39c40d3f82..afa37a5779 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -14,8 +14,6 @@ #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM -#define CONFIG_SYS_THUMB_BUILD - /* Support File sytems */ #define CONFIG_FAT_WRITE #define CONFIG_SUPPORT_VFAT @@ -27,7 +25,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING -#define CONFIG_BAUDRATE 38400 #define CONFIG_BOOTARGS "" #undef CONFIG_SHOW_BOOT_PROGRESS diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 5fe06866af..36e07dc73d 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -37,8 +37,6 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_OF_LIBFDT -#define CONFIG_BAUDRATE 115200 - #undef CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 318a52c3ed..2893f80c9f 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -13,11 +13,9 @@ #define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h new file mode 100644 index 0000000000..d7e96ec269 --- /dev/null +++ b/include/configs/rk3188_common.h @@ -0,0 +1,119 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3188_COMMON_H +#define __CONFIG_RK3188_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include <asm/arch/hardware.h> +#include "rockchip-common.h" + +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_THUMB_BUILD + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CONFIG_SYS_TIMER_COUNTS_DOWN + +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SPL_BOARD_INIT + +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x60100000 +#endif +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK31" + +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x10080804 +/* tpl size 1kb - 4byte RK31 header */ +#define CONFIG_SPL_MAX_SIZE (0x400 - 0x4) +#elif defined(CONFIG_SPL_BUILD) +/* spl size 32kb sram - 2kb bootrom - 1kb spl */ +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0xC00) +#define CONFIG_SPL_TEXT_BASE 0x10080C00 +#define CONFIG_SPL_FRAMEWORK 1 +#define CONFIG_SPL_CLK 1 +#define CONFIG_SPL_PINCTRL 1 +#define CONFIG_SPL_REGMAP 1 +#define CONFIG_SPL_SYSCON 1 +#define CONFIG_SPL_RAM 1 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1 +#define CONFIG_ROCKCHIP_SERIAL 1 +#endif + +#define CONFIG_SPL_STACK 0x10087fff + +/* MMC/SD IP block */ +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_FAT_WRITE + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#ifndef CONFIG_SPL_BUILD +/* usb otg */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_ROCKCHIP_USB2_PHY +#define CONFIG_USB_GADGET_VBUS_DRAW 0 + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 +#define CONFIG_G_DNL_PRODUCT_NUM 0x310a + +/* usb host support */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#endif +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include <config_distro_bootcmd.h> + +/* Linux fails to load the fdt if it's loaded above 256M on a Rock board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x6fffffff\0" \ + "initrd_high=0x6fffffff\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_PREBOOT + +#endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index b5606d463c..e7a8f724f1 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -14,10 +14,8 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h new file mode 100644 index 0000000000..b0dcd48209 --- /dev/null +++ b/include/configs/rk3328_common.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3328_COMMON_H +#define __CONFIG_RK3328_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x00200000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_SUPPORT_VFAT +#define CONFIG_FS_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_FS_EXT4 + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +/* FAT sd card locations. */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x04000000\0" + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_DEFAULT \ + BOOTENV + +#endif + +#endif diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index ce64476c2e..4ba81aca6c 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -12,16 +12,26 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_BAUDRATE 1500000 #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_TEXT_BASE 0x00200000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0xff8effff +#define CONFIG_SPL_TEXT_BASE 0xff8c2008 +#define CONFIG_SPL_MAX_SIZE 0x30000 +/* BSS setup */ +#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index e293f2ed31..92eb792989 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -99,7 +99,6 @@ #define CONFIG_PL01X_SERIAL #endif #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Console configuration */ #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h index 913cbc2623..8dc839df96 100644 --- a/include/configs/rsk7203.h +++ b/include/configs/rsk7203.h @@ -15,7 +15,6 @@ #define CONFIG_CMD_SDRAM -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */ diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h index ea60014d89..cc709097c0 100644 --- a/include/configs/rsk7264.h +++ b/include/configs/rsk7264.h @@ -16,7 +16,6 @@ #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC3,115200" #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h index f470954518..12812f9a34 100644 --- a/include/configs/rsk7269.h +++ b/include/configs/rsk7269.h @@ -15,7 +15,6 @@ #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC7,115200" #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h index 33ff6d5749..0b12bf3d55 100644 --- a/include/configs/s32v234evb.h +++ b/include/configs/s32v234evb.h @@ -72,7 +72,6 @@ /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_UART_PORT (1) -#define CONFIG_BAUDRATE 115200 #undef CONFIG_CMD_IMLS diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index e9dc57d647..e49b3d9580 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -44,7 +44,6 @@ * select serial console configuration */ #define CONFIG_SERIAL2 1 /* use SERIAL2 */ -#define CONFIG_BAUDRATE 115200 /* MMC */ #define SDHCI_MAX_HOSTS 4 diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 1bfefe9dff..627a341196 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -26,7 +26,6 @@ /* select serial console configuration */ #define CONFIG_SERIAL2 -#define CONFIG_BAUDRATE 115200 /* Console configuration */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index ac7973ceca..6b3cd18046 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -44,7 +44,6 @@ #define CONFIG_CMD_CBFS #define CONFIG_CMD_CRAMFS #define CONFIG_HOST_MAX_DEVICES 4 -#define CONFIG_CMD_MD5SUM /* * Size of malloc() pool, before and after relocation @@ -87,7 +86,6 @@ #define CONFIG_SYS_MONITOR_BASE 0 #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index dc1978b93b..4d87f5334a 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -636,8 +636,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=sbc8349\0" \ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index f5a5b61940..e872e7f810 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -569,8 +569,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index ebd76ea8ab..33b6d1fb93 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -518,8 +518,6 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index d8189816df..0cfcbab48a 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -16,10 +16,7 @@ #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_MD5SUM -#define CONFIG_MD5 -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index a7d8de4241..58aad05358 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -16,10 +16,7 @@ #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_MD5SUM -#define CONFIG_MD5 -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index c21a5f8fee..e9cd3d749a 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -16,10 +16,7 @@ #define CONFIG_SYS_TEXT_BASE 0x8ef80000 #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_MD5SUM -#define CONFIG_MD5 -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index 61248262f1..69073e8a66 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -28,7 +28,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE 1 -#define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_SCIF2 1 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index 1c3b701fe1..ab30428063 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -16,7 +16,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SH_ZIMAGEBOOT -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/shmin.h b/include/configs/shmin.h index dde6625f04..bc1eba32ff 100644 --- a/include/configs/shmin.h +++ b/include/configs/shmin.h @@ -18,7 +18,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_ENV -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS "console=ttySC0,115200" /* diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 34e124f506..5a9ec02368 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -100,8 +100,6 @@ #define CONFIG_SYS_NS16550_COM1 0x44e09000 #define CONFIG_SYS_NS16550_COM4 0x481a6000 -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SERIAL1 1 #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index f53f5d8ae2..e09dfe6dd3 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -112,7 +112,6 @@ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 /* * Ethernet configuration @@ -270,7 +269,6 @@ #define CONFIG_SYS_AT91_PLLB 0x10483f0e #if defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF #endif diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index a7c43b06ea..ab75504188 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -55,7 +55,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 /*********************************************************** * Command definition diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index a465a0e43f..d3e73f2097 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -82,7 +82,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS #endif -#define CONFIG_BAUDRATE 115200 /* I2C - Bit-bashed */ #define CONFIG_SYS_I2C diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index c637ba1384..952c6f546f 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -81,7 +81,6 @@ /* UARTs/Serial console */ #define CONFIG_ATMEL_USART -#define CONFIG_BAUDRATE 115200 /* Boot options */ #define CONFIG_SYS_LOAD_ADDR 0x23000000 diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 83fa6e053d..6ddb83fccd 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -137,7 +137,6 @@ #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_CONS_INDEX 3 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ 115200 } diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 582b04af3d..8472b52e0a 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -9,8 +9,6 @@ /* Virtual target or real hardware */ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_THUMB_BUILD - /* * High level configuration */ @@ -218,7 +216,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_NS16550_CLK 100000000 #endif #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* * USB diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h index 2278357fc6..c6e8d81be6 100644 --- a/include/configs/socfpga_de1_soc.h +++ b/include/configs/socfpga_de1_soc.h @@ -50,6 +50,4 @@ /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - #endif /* __CONFIG_TERASIC_DE1_SOC_H__ */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 1bc520384c..3f9c34b8f6 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -185,8 +185,6 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 77b80df2a6..75fd27a373 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -80,7 +80,6 @@ #define CONFIG_PL011_SERIAL #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 57600, 115200 } diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 28e2f7f614..6f4070ff43 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -18,13 +18,8 @@ #define CONFIG_SYS_TEXT_BASE 0x7D600000 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */ -/* Libraries */ -#define CONFIG_MD5 - #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 69135ff0f6..a456e458aa 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -8,7 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_STM32F4DISCOVERY #define CONFIG_MISC_INIT_R @@ -69,7 +68,6 @@ #define CONFIG_STACKSIZE (64 << 10) -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index ae3211ab27..55280f203f 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_THUMB_BUILD - #define CONFIG_SYS_FLASH_BASE 0x08000000 #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 #define CONFIG_SYS_TEXT_BASE 0x08000000 @@ -62,7 +60,6 @@ #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define CONFIG_STACKSIZE (256 * 1024) -#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/strider.h b/include/configs/strider.h index f65e602299..1298808b13 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -632,8 +632,6 @@ void fpga_control_clear(unsigned int bus, int pin); #define CONFIG_HAS_ETH0 #endif -#define CONFIG_BAUDRATE 115200 - #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 24dd81856b..2f808c6c72 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) /* serial port (PL011) configuration */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_PL01X_SERIAL /* user interface */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d48bdac07a..05ea172fe3 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -32,13 +32,6 @@ # define CONFIG_MACH_TYPE_COMPAT_REV 1 #endif -/* - * High Level Configuration Options - */ -#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) -#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ -#endif - /* Serial & console */ #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ @@ -163,7 +156,6 @@ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR /* baudrate */ -#define CONFIG_BAUDRATE 115200 /* The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 7803a849bc..55b8e3ebfc 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -286,8 +286,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BAUDRATE 115200 - #define CONFIG_HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 2704319070..b1625b779c 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -66,7 +66,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} /* EHCI */ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index ead8ea76e8..035a9325b3 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -63,7 +63,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 /* GPIO banks */ #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index ba7346c628..4505be8eaf 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -23,7 +23,6 @@ #include <linux/sizes.h> #if defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF #endif @@ -56,7 +55,6 @@ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 /* diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 15d77626e5..b7199430a5 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -35,7 +35,6 @@ */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 166666666 -#define CONFIG_BAUDRATE 115200 /* * Ethernet PHY configuration diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 09a7942650..dc6db17f76 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -12,7 +12,6 @@ #include "mx6_common.h" /* General configuration */ -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_MACH_TYPE 3980 @@ -42,7 +41,6 @@ /* Serial console */ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h index e017ba92ca..7924c8e483 100644 --- a/include/configs/tcm-bf518.h +++ b/include/configs/tcm-bf518.h @@ -99,7 +99,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 #define CONFIG_BOOTCOMMAND "run flashboot" diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 4d1cdb507b..f9d9f84672 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -123,7 +123,6 @@ /* * Misc Settings */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_MISC_INIT_R #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index a96b2b5d57..c0462bce90 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -49,7 +49,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 /* turn on command-line edit/hist/auto */ #define CONFIG_COMMAND_HISTORY diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 0e563fed42..f52fc8225c 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -45,8 +45,6 @@ #define CONFIG_SYS_SERIAL0 0x87e024000000 #define CONFIG_SYS_SERIAL1 0x87e025000000 -#define CONFIG_BAUDRATE 115200 - /* BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_BOOTP_BOOTPATH diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index c0b477d044..319279e4fa 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -135,8 +135,6 @@ #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ -#define CONFIG_BAUDRATE 115200 - /* CPU */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 951b842194..284046740c 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -97,8 +97,6 @@ #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ -#define CONFIG_BAUDRATE 115200 - /* allow overwriting serial config and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index fbe8859eca..a4ec4ce00a 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -175,7 +175,6 @@ * console baudrate of 115200 and use the default baud rate table. */ #define CONFIG_SYS_MALLOC_LEN SZ_32M -#define CONFIG_BAUDRATE 115200 #define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */ #define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ @@ -278,8 +277,6 @@ #define CONFIG_CMD_SPL #endif -#define CONFIG_SYS_THUMB_BUILD - /* General parts of the framework, required. */ #define CONFIG_SPL_BOARD_INIT diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 8e0f9eb964..d07cb9ffb4 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -18,8 +18,6 @@ #define CONFIG_OMAP4430 1 /* which is in a 4430 */ #define CONFIG_MISC_INIT_R -#define CONFIG_SYS_THUMB_BUILD - #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 1 #define CONFIG_SYS_PL310_BASE 0x48242000 diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h index 860eb404fb..c398e072d2 100644 --- a/include/configs/tinker_rk3288.h +++ b/include/configs/tinker_rk3288.h @@ -13,7 +13,7 @@ #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) + func(MMC, mmc, 1) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index 42cfbb06ba..a56ceef85a 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_TOPIC_MIAMI_H #define __CONFIG_TOPIC_MIAMI_H -#define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL - #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_I2C1 diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index d42889878e..d39dd92198 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -29,7 +29,6 @@ * Serial Port */ #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/trats.h b/include/configs/trats.h index f027940c3d..1e68c03242 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -38,7 +38,6 @@ /* select serial console configuration */ #define CONFIG_SERIAL2 -#define CONFIG_BAUDRATE 115200 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 1cd3e14235..722d492518 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -35,7 +35,6 @@ /* select serial console configuration */ #define CONFIG_SERIAL2 -#define CONFIG_BAUDRATE 115200 /* Console configuration */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 2b80352f54..fc70be18df 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -17,7 +17,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER @@ -67,7 +66,6 @@ #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_SERIAL3 3 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h index 5649c18c4f..a65c5f1c71 100644 --- a/include/configs/ts4800.h +++ b/include/configs/ts4800.h @@ -73,7 +73,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */ #define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */ -#define CONFIG_BAUDRATE 115200 /*********************************************************** * Command definition diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 2976d6313c..cdc5b0018a 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -57,7 +57,6 @@ #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 /* serial console configuration */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_LONGHELP /* undef to save memory */ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 1462689244..57e22208c4 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -42,7 +42,6 @@ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -#define CONFIG_BAUDRATE 115200 /* diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 6c888293c1..a67802a160 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -35,7 +35,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* SD/MMC */ #define CONFIG_FSL_ESDHC diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 08359d14d6..dc7186c3cc 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -37,7 +37,6 @@ * Serial console configuration */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } /* diff --git a/include/configs/vct.h b/include/configs/vct.h index c21c12577f..99cb31148a 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_NS16550_COM1 UART_1_BASE #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_CLK 921600 -#define CONFIG_BAUDRATE 115200 /* * SDRAM diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 564607e516..f0e9a2e58d 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -459,8 +459,6 @@ #define CONFIG_HOSTNAME ve8313 #define CONFIG_UBOOTPATH ve8313/u-boot.bin -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=" __stringify(CONFIG_NETDEV) "\0" \ "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 35ac60ac26..ae13246478 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -115,7 +115,6 @@ #endif /* PL011 Serial Configuration */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_CONS_INDEX 0 #define CONFIG_PL01X_SERIAL #define CONFIG_PL011_SERIAL diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 3756e22ffa..0880b627ae 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -145,7 +145,6 @@ (void *)CONFIG_SYS_SERIAL1} #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 38400 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_SERIAL0 V2M_UART0 #define CONFIG_SYS_SERIAL1 V2M_UART1 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index b6407e9471..ee90045cad 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -30,7 +30,6 @@ /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 /* NAND support */ #define CONFIG_CMD_NAND diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 7724eea194..738b13ddfb 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -539,8 +539,6 @@ #undef CONFIG_BOOTARGS /* boot command will set bootargs */ -#define CONFIG_BAUDRATE 9600 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=vme8349\0" \ diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 7fec24c65c..3f837e86fb 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -68,7 +68,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 /* * Command definition diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 6af03644b0..b35ba55d53 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -50,7 +50,6 @@ * Serial Driver */ #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ -#define CONFIG_BAUDRATE 115200 /* * Ethernet Driver diff --git a/include/configs/x600.h b/include/configs/x600.h index 67c70f6e6e..cf68374d1f 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -16,7 +16,6 @@ */ #define CONFIG_SPEAR600 /* SPEAr600 SoC */ #define CONFIG_X600 /* on X600 board */ -#define CONFIG_SYS_THUMB_BUILD #include <asm/arch/hardware.h> @@ -44,7 +43,6 @@ #define CONFIG_PL011_SERIAL #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 57600, 115200 } #define CONFIG_SYS_LOADS_BAUD_CHANGE diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index a6ad18e88a..f7796cf63f 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -56,7 +56,6 @@ /*----------------------------------------------------------------------- * Serial Configuration */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ 9600, 19200, 38400, 115200} #define CONFIG_SYS_NS16550_PORT_MAPPED diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index 58cfe41e86..2afc645b7d 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -87,7 +87,6 @@ #define CONFIG_ENV_IS_NOWHERE #endif -#define CONFIG_BAUDRATE 115200 /* The following table includes the supported baudrates */ # define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index ba799436a1..30b5b34520 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -48,7 +48,6 @@ #define CONFIG_ZYNQ_SERIAL #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index 45436c8ac0..ba8eebe462 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -101,7 +101,6 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} -#define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 0d5b1ff41d..d004148950 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -213,7 +213,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index b88aeb472a..696ac88c3f 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -175,7 +175,6 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 2f133d2b6e..9c48e5eaaa 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -209,7 +209,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 4ac25a6b21..f8a1f4badc 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -201,7 +201,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index c7862be10d..5169504dc7 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -208,7 +208,6 @@ /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /*======================*/ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 3df9a078a8..841cc6dbb2 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -50,7 +50,6 @@ */ #define CONFIG_STUART 1 #define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 /* * Bootloader Components Configuration diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index f669590fb7..c61c353901 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -54,7 +54,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE #define CONFIG_CONS_INDEX 1 /* use UART2 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ /* * Ethernet diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 431d6c49c4..1fa5599865 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) /* Serial drivers */ -#define CONFIG_BAUDRATE 115200 /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index b9ff391458..1488fd8b2f 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -20,9 +20,6 @@ #define CONFIG_DISPLAY #define CONFIG_I2C_EDID -/* Define ZYBO PS Clock Frequency to 50MHz */ -#define CONFIG_ZYNQ_PS_CLK_FREQ 50000000UL - #include <configs/zynq-common.h> #endif /* __CONFIG_ZYNQ_ZYBO_H */ diff --git a/include/dm/util.h b/include/dm/util.h index 15daa3d19f..45529ce0e6 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -48,4 +48,30 @@ static inline void dm_dump_devres(void) } #endif +/** + * Check if a dt node should be or was bound before relocation. + * + * Devicetree nodes can be marked as needed to be bound + * in the loader stages via special devicetree properties. + * + * Before relocation this function can be used to check if nodes + * are required in either SPL or TPL stages. + * + * After relocation and jumping into the real U-Boot binary + * it is possible to determine if a node was bound in one of + * SPL/TPL stages. + * + * There are 3 settings currently in use + * - + * - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL + * Existing platforms only use it to indicate nodes needee in + * SPL. Should probably be replaced by u-boot,dm-spl for + * existing platforms. + * @blob: devicetree + * @offset: node offset + * + * Returns true if node is needed in SPL/TL, false otherwise. + */ +bool dm_fdt_pre_reloc(const void *blob, int offset); + #endif diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h new file mode 100644 index 0000000000..549ae6a3f3 --- /dev/null +++ b/include/dt-bindings/clock/rk3066a-cru.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H + +#include <dt-bindings/clock/rk3188-cru-common.h> + +/* soft-reset indices */ +#define SRST_SRST1 0 +#define SRST_SRST2 1 + +#define SRST_L2MEM 18 +#define SRST_I2S0 23 +#define SRST_I2S1 24 +#define SRST_I2S2 25 +#define SRST_TIMER2 29 + +#define SRST_GPIO4 36 +#define SRST_GPIO6 38 + +#define SRST_TSADC 92 + +#define SRST_HDMI 96 +#define SRST_HDMI_APB 97 +#define SRST_CIF1 111 + +#endif diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h new file mode 100644 index 0000000000..8fc818b1d9 --- /dev/null +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H + +/* core clocks from */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define CORE_PERI 5 +#define CORE_L2C 6 +#define ARMCLK 7 + +/* sclk gates (special clocks) */ +#define SCLK_UART0 64 +#define SCLK_UART1 65 +#define SCLK_UART2 66 +#define SCLK_UART3 67 +#define SCLK_MAC 68 +#define SCLK_SPI0 69 +#define SCLK_SPI1 70 +#define SCLK_SARADC 71 +#define SCLK_SDMMC 72 +#define SCLK_SDIO 73 +#define SCLK_EMMC 74 +#define SCLK_I2S0 75 +#define SCLK_I2S1 76 +#define SCLK_I2S2 77 +#define SCLK_SPDIF 78 +#define SCLK_CIF0 79 +#define SCLK_CIF1 80 +#define SCLK_OTGPHY0 81 +#define SCLK_OTGPHY1 82 +#define SCLK_HSADC 83 +#define SCLK_TIMER0 84 +#define SCLK_TIMER1 85 +#define SCLK_TIMER2 86 +#define SCLK_TIMER3 87 +#define SCLK_TIMER4 88 +#define SCLK_TIMER5 89 +#define SCLK_TIMER6 90 +#define SCLK_JTAG 91 +#define SCLK_SMC 92 +#define SCLK_TSADC 93 + +#define DCLK_LCDC0 190 +#define DCLK_LCDC1 191 + +/* aclk gates */ +#define ACLK_DMA1 192 +#define ACLK_DMA2 193 +#define ACLK_GPS 194 +#define ACLK_LCDC0 195 +#define ACLK_LCDC1 196 +#define ACLK_GPU 197 +#define ACLK_SMC 198 +#define ACLK_CIF 199 +#define ACLK_IPP 200 +#define ACLK_RGA 201 +#define ACLK_CIF0 202 +#define ACLK_CPU 203 +#define ACLK_PERI 204 + +/* pclk gates */ +#define PCLK_GRF 320 +#define PCLK_PMU 321 +#define PCLK_TIMER0 322 +#define PCLK_TIMER1 323 +#define PCLK_TIMER2 324 +#define PCLK_TIMER3 325 +#define PCLK_PWM01 326 +#define PCLK_PWM23 327 +#define PCLK_SPI0 328 +#define PCLK_SPI1 329 +#define PCLK_SARADC 330 +#define PCLK_WDT 331 +#define PCLK_UART0 332 +#define PCLK_UART1 333 +#define PCLK_UART2 334 +#define PCLK_UART3 335 +#define PCLK_I2C0 336 +#define PCLK_I2C1 337 +#define PCLK_I2C2 338 +#define PCLK_I2C3 339 +#define PCLK_I2C4 340 +#define PCLK_GPIO0 341 +#define PCLK_GPIO1 342 +#define PCLK_GPIO2 343 +#define PCLK_GPIO3 344 +#define PCLK_GPIO4 345 +#define PCLK_GPIO6 346 +#define PCLK_EFUSE 347 +#define PCLK_TZPC 348 +#define PCLK_TSADC 349 +#define PCLK_CPU 350 +#define PCLK_PERI 351 +#define PCLK_DDRUPCTL 352 +#define PCLK_PUBL 353 + +/* hclk gates */ +#define HCLK_SDMMC 448 +#define HCLK_SDIO 449 +#define HCLK_EMMC 450 +#define HCLK_OTG0 451 +#define HCLK_EMAC 452 +#define HCLK_SPDIF 453 +#define HCLK_I2S0 454 +#define HCLK_I2S1 455 +#define HCLK_I2S2 456 +#define HCLK_OTG1 457 +#define HCLK_HSIC 458 +#define HCLK_HSADC 459 +#define HCLK_PIDF 460 +#define HCLK_LCDC0 461 +#define HCLK_LCDC1 462 +#define HCLK_ROM 463 +#define HCLK_CIF0 464 +#define HCLK_IPP 465 +#define HCLK_RGA 466 +#define HCLK_NANDC0 467 +#define HCLK_CPU 468 +#define HCLK_PERI 469 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_MCORE 2 +#define SRST_CORE0 3 +#define SRST_CORE1 4 +#define SRST_MCORE_DBG 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE0_WDT 12 +#define SRST_CORE1_WDT 13 +#define SRST_STRC_SYS 14 +#define SRST_L2C 15 + +#define SRST_CPU_AHB 17 +#define SRST_AHB2APB 19 +#define SRST_DMA1 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_SPDIF 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_EFUSE 30 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 + +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_UART3 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 +#define SRST_I2C4 47 + +#define SRST_PWM0 48 +#define SRST_PWM1 49 +#define SRST_DAP_PO 50 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_TPIU_ATB 53 +#define SRST_PMU_APB 54 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERI_AXI 57 +#define SRST_PERI_AHB 58 +#define SRST_PERI_APB 59 +#define SRST_PERI_NIU 60 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_SMC 65 +#define SRST_MAC 66 +#define SRST_NANC0 68 +#define SRST_USBOTG0 69 +#define SRST_USBPHY0 70 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_USBPHY1 73 +#define SRST_OTGC1 74 +#define SRST_HSADC 76 +#define SRST_PIDFILTER 77 +#define SRST_DDR_MSCH 79 + +#define SRST_TZPC 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_SPI1 85 +#define SRST_WDT 86 +#define SRST_SARADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_APB 89 +#define SRST_DDRCTL 90 +#define SRST_DDRCTL_APB 91 +#define SRST_DDRPUB 93 + +#define SRST_VIO0_AXI 98 +#define SRST_VIO0_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_LCDC1_AXI 103 +#define SRST_LCDC1_AHB 104 +#define SRST_LCDC1_DCLK 105 +#define SRST_IPP_AXI 106 +#define SRST_IPP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_CIF0 110 + +#define SRST_VCODEC_AXI 112 +#define SRST_VCODEC_AHB 113 +#define SRST_VIO1_AXI 114 +#define SRST_VCODEC_CPU 115 +#define SRST_VCODEC_NIU 116 +#define SRST_GPU 120 +#define SRST_GPU_NIU 122 +#define SRST_TFUN_ATB 125 +#define SRST_TFUN_APB 126 +#define SRST_CTI4_APB 127 + +#define SRST_TPIU_APB 128 +#define SRST_TRACE 129 +#define SRST_CORE_DBG 130 +#define SRST_DBG_APB 131 +#define SRST_CTI0 132 +#define SRST_CTI0_APB 133 +#define SRST_CTI1 134 +#define SRST_CTI1_APB 135 +#define SRST_PTM_CORE0 136 +#define SRST_PTM_CORE1 137 +#define SRST_PTM0 138 +#define SRST_PTM0_ATB 139 +#define SRST_PTM1 140 +#define SRST_PTM1_ATB 141 +#define SRST_CTM 142 +#define SRST_TS 143 + +#endif diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h new file mode 100644 index 0000000000..b6960b07bc --- /dev/null +++ b/include/dt-bindings/clock/rk3188-cru.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H + +#include <dt-bindings/clock/rk3188-cru-common.h> + +/* soft-reset indices */ +#define SRST_PTM_CORE2 0 +#define SRST_PTM_CORE3 1 +#define SRST_CORE2 5 +#define SRST_CORE3 6 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 + +#define SRST_TIMER2 16 +#define SRST_TIMER4 23 +#define SRST_I2S0 24 +#define SRST_TIMER5 25 +#define SRST_TIMER3 29 +#define SRST_TIMER6 31 + +#define SRST_PTM3 36 +#define SRST_PTM3_ATB 37 + +#define SRST_GPS 67 +#define SRST_HSICPHY 75 +#define SRST_TIMER 78 + +#define SRST_PTM2 92 +#define SRST_CORE2_WDT 94 +#define SRST_CORE3_WDT 95 + +#define SRST_PTM2_ATB 111 + +#define SRST_HSIC 117 +#define SRST_CTI2 118 +#define SRST_CTI2_APB 119 +#define SRST_GPU_BRIDGE 121 +#define SRST_CTI3 123 +#define SRST_CTI3_APB 124 + +#endif diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h new file mode 100644 index 0000000000..6d8bf1330b --- /dev/null +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -0,0 +1,394 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define ARMCLK 6 + +/* sclk gates (special clocks) */ +#define SCLK_RTC32K 30 +#define SCLK_SDMMC_EXT 31 +#define SCLK_SPI 32 +#define SCLK_SDMMC 33 +#define SCLK_SDIO 34 +#define SCLK_EMMC 35 +#define SCLK_TSADC 36 +#define SCLK_SARADC 37 +#define SCLK_UART0 38 +#define SCLK_UART1 39 +#define SCLK_UART2 40 +#define SCLK_I2S0 41 +#define SCLK_I2S1 42 +#define SCLK_I2S2 43 +#define SCLK_I2S1_OUT 44 +#define SCLK_I2S2_OUT 45 +#define SCLK_SPDIF 46 +#define SCLK_TIMER0 47 +#define SCLK_TIMER1 48 +#define SCLK_TIMER2 49 +#define SCLK_TIMER3 50 +#define SCLK_TIMER4 51 +#define SCLK_TIMER5 52 +#define SCLK_WIFI 53 +#define SCLK_CIF_OUT 54 +#define SCLK_I2C0 55 +#define SCLK_I2C1 56 +#define SCLK_I2C2 57 +#define SCLK_I2C3 58 +#define SCLK_CRYPTO 59 +#define SCLK_PWM 60 +#define SCLK_PDM 61 +#define SCLK_EFUSE 62 +#define SCLK_OTP 63 +#define SCLK_DDRCLK 64 +#define SCLK_VDEC_CABAC 65 +#define SCLK_VDEC_CORE 66 +#define SCLK_VENC_DSP 67 +#define SCLK_VENC_CORE 68 +#define SCLK_RGA 69 +#define SCLK_HDMI_SFC 70 +#define SCLK_HDMI_CEC 71 +#define SCLK_USB3_REF 72 +#define SCLK_USB3_SUSPEND 73 +#define SCLK_SDMMC_DRV 74 +#define SCLK_SDIO_DRV 75 +#define SCLK_EMMC_DRV 76 +#define SCLK_SDMMC_EXT_DRV 77 +#define SCLK_SDMMC_SAMPLE 78 +#define SCLK_SDIO_SAMPLE 79 +#define SCLK_EMMC_SAMPLE 80 +#define SCLK_SDMMC_EXT_SAMPLE 81 +#define SCLK_VOP 82 +#define SCLK_MAC2PHY_RXTX 83 +#define SCLK_MAC2PHY_SRC 84 +#define SCLK_MAC2PHY_REF 85 +#define SCLK_MAC2PHY_OUT 86 +#define SCLK_MAC2IO_RX 87 +#define SCLK_MAC2IO_TX 88 +#define SCLK_MAC2IO_REFOUT 89 +#define SCLK_MAC2IO_REF 90 +#define SCLK_MAC2IO_OUT 91 +#define SCLK_TSP 92 +#define SCLK_HSADC_TSP 93 +#define SCLK_USB3PHY_REF 94 +#define SCLK_REF_USB3OTG 95 +#define SCLK_USB3OTG_REF 96 +#define SCLK_USB3OTG_SUSPEND 97 +#define SCLK_REF_USB3OTG_SRC 98 +#define SCLK_MAC2IO_SRC 99 + +/* dclk gates */ +#define DCLK_LCDC 180 +#define DCLK_HDMIPHY 181 +#define HDMIPHY 182 +#define USB480M 183 +#define DCLK_LCDC_SRC 184 + +/* aclk gates */ +#define ACLK_AXISRAM 190 +#define ACLK_VOP_PRE 191 +#define ACLK_USB3OTG 192 +#define ACLK_RGA_PRE 193 +#define ACLK_DMAC 194 +#define ACLK_GPU 195 +#define ACLK_BUS_PRE 196 +#define ACLK_PERI_PRE 197 +#define ACLK_RKVDEC_PRE 198 +#define ACLK_RKVDEC 199 +#define ACLK_RKVENC 200 +#define ACLK_VPU_PRE 201 +#define ACLK_VIO_PRE 202 +#define ACLK_VPU 203 +#define ACLK_VIO 204 +#define ACLK_VOP 205 +#define ACLK_GMAC 206 +#define ACLK_H265 207 +#define ACLK_H264 208 +#define ACLK_MAC2PHY 209 +#define ACLK_MAC2IO 210 +#define ACLK_DCF 211 +#define ACLK_TSP 212 +#define ACLK_PERI 213 +#define ACLK_RGA 214 +#define ACLK_IEP 215 +#define ACLK_CIF 216 +#define ACLK_HDCP 217 + +/* pclk gates */ +#define PCLK_GPIO0 300 +#define PCLK_GPIO1 301 +#define PCLK_GPIO2 302 +#define PCLK_GPIO3 303 +#define PCLK_GRF 304 +#define PCLK_I2C0 305 +#define PCLK_I2C1 306 +#define PCLK_I2C2 307 +#define PCLK_I2C3 308 +#define PCLK_SPI 309 +#define PCLK_UART0 310 +#define PCLK_UART1 311 +#define PCLK_UART2 312 +#define PCLK_TSADC 313 +#define PCLK_PWM 314 +#define PCLK_TIMER 315 +#define PCLK_BUS_PRE 316 +#define PCLK_PERI_PRE 317 +#define PCLK_HDMI_CTRL 318 +#define PCLK_HDMI_PHY 319 +#define PCLK_GMAC 320 +#define PCLK_H265 321 +#define PCLK_MAC2PHY 322 +#define PCLK_MAC2IO 323 +#define PCLK_USB3PHY_OTG 324 +#define PCLK_USB3PHY_PIPE 325 +#define PCLK_USB3_GRF 326 +#define PCLK_USB2_GRF 327 +#define PCLK_HDMIPHY 328 +#define PCLK_DDR 329 +#define PCLK_PERI 330 +#define PCLK_HDMI 331 +#define PCLK_HDCP 332 +#define PCLK_DCF 333 +#define PCLK_SARADC 334 + +/* hclk gates */ +#define HCLK_PERI 408 +#define HCLK_TSP 409 +#define HCLK_GMAC 410 +#define HCLK_I2S0_8CH 411 +#define HCLK_I2S1_8CH 413 +#define HCLK_I2S2_2CH 413 +#define HCLK_SPDIF_8CH 414 +#define HCLK_VOP 415 +#define HCLK_NANDC 416 +#define HCLK_SDMMC 417 +#define HCLK_SDIO 418 +#define HCLK_EMMC 419 +#define HCLK_SDMMC_EXT 420 +#define HCLK_RKVDEC_PRE 421 +#define HCLK_RKVDEC 422 +#define HCLK_RKVENC 423 +#define HCLK_VPU_PRE 424 +#define HCLK_VIO_PRE 425 +#define HCLK_VPU 426 +#define HCLK_VIO 427 +#define HCLK_BUS_PRE 428 +#define HCLK_PERI_PRE 429 +#define HCLK_H264 430 +#define HCLK_CIF 431 +#define HCLK_OTG_PMU 432 +#define HCLK_OTG 433 +#define HCLK_HOST0 434 +#define HCLK_HOST0_ARB 435 +#define HCLK_CRYPTO_MST 436 +#define HCLK_CRYPTO_SLV 437 +#define HCLK_PDM 438 +#define HCLK_IEP 439 +#define HCLK_RGA 440 +#define HCLK_HDCP 441 + +#define CLK_NR_CLKS (HCLK_HDCP + 1) + +#define SCLK_MAC2IO 0 +#define SCLK_MAC2PHY 1 + +#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NIU 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_A53_GIC 18 +#define SRST_DAP 19 +#define SRST_PMU_P 21 +#define SRST_EFUSE 22 +#define SRST_BUSSYS_H 23 +#define SRST_BUSSYS_P 24 +#define SRST_SPDIF 25 +#define SRST_INTMEM 26 +#define SRST_ROM 27 +#define SRST_GPIO0 28 +#define SRST_GPIO1 29 +#define SRST_GPIO2 30 +#define SRST_GPIO3 31 + +#define SRST_I2S0 32 +#define SRST_I2S1 33 +#define SRST_I2S2 34 +#define SRST_I2S0_H 35 +#define SRST_I2S1_H 36 +#define SRST_I2S2_H 37 +#define SRST_UART0 38 +#define SRST_UART1 39 +#define SRST_UART2 40 +#define SRST_UART0_P 41 +#define SRST_UART1_P 42 +#define SRST_UART2_P 43 +#define SRST_I2C0 44 +#define SRST_I2C1 45 +#define SRST_I2C2 46 +#define SRST_I2C3 47 + +#define SRST_I2C0_P 48 +#define SRST_I2C1_P 49 +#define SRST_I2C2_P 50 +#define SRST_I2C3_P 51 +#define SRST_EFUSE_SE_P 52 +#define SRST_EFUSE_NS_P 53 +#define SRST_PWM0 54 +#define SRST_PWM0_P 55 +#define SRST_DMA 56 +#define SRST_TSP_A 57 +#define SRST_TSP_H 58 +#define SRST_TSP 59 +#define SRST_TSP_HSADC 60 +#define SRST_DCF_A 61 +#define SRST_DCF_P 62 + +#define SRST_SCR 64 +#define SRST_SPI 65 +#define SRST_TSADC 66 +#define SRST_TSADC_P 67 +#define SRST_CRYPTO 68 +#define SRST_SGRF 69 +#define SRST_GRF 70 +#define SRST_USB_GRF 71 +#define SRST_TIMER_6CH_P 72 +#define SRST_TIMER0 73 +#define SRST_TIMER1 74 +#define SRST_TIMER2 75 +#define SRST_TIMER3 76 +#define SRST_TIMER4 77 +#define SRST_TIMER5 78 +#define SRST_USB3GRF 79 + +#define SRST_PHYNIU 80 +#define SRST_HDMIPHY 81 +#define SRST_VDAC 82 +#define SRST_ACODEC_p 83 +#define SRST_SARADC 85 +#define SRST_SARADC_P 86 +#define SRST_GRF_DDR 87 +#define SRST_DFIMON 88 +#define SRST_MSCH 89 +#define SRST_DDRMSCH 91 +#define SRST_DDRCTRL 92 +#define SRST_DDRCTRL_P 93 +#define SRST_DDRPHY 94 +#define SRST_DDRPHY_P 95 + +#define SRST_GMAC_NIU_A 96 +#define SRST_GMAC_NIU_P 97 +#define SRST_GMAC2PHY_A 98 +#define SRST_GMAC2IO_A 99 +#define SRST_MACPHY 100 +#define SRST_OTP_PHY 101 +#define SRST_GPU_A 102 +#define SRST_GPU_NIU_A 103 +#define SRST_SDMMCEXT 104 +#define SRST_PERIPH_NIU_A 105 +#define SRST_PERIHP_NIU_H 106 +#define SRST_PERIHP_P 107 +#define SRST_PERIPHSYS_H 108 +#define SRST_MMC0 109 +#define SRST_SDIO 110 +#define SRST_EMMC 111 + +#define SRST_USB2OTG_H 112 +#define SRST_USB2OTG 113 +#define SRST_USB2OTG_ADP 114 +#define SRST_USB2HOST_H 115 +#define SRST_USB2HOST_ARB 116 +#define SRST_USB2HOST_AUX 117 +#define SRST_USB2HOST_EHCIPHY 118 +#define SRST_USB2HOST_UTMI 119 +#define SRST_USB3OTG 120 +#define SRST_USBPOR 121 +#define SRST_USB2OTG_UTMI 122 +#define SRST_USB2HOST_PHY_UTMI 123 +#define SRST_USB3OTG_UTMI 124 +#define SRST_USB3PHY_U2 125 +#define SRST_USB3PHY_U3 126 +#define SRST_USB3PHY_PIPE 127 + +#define SRST_VIO_A 128 +#define SRST_VIO_BUS_H 129 +#define SRST_VIO_H2P_H 130 +#define SRST_VIO_ARBI_H 131 +#define SRST_VOP_NIU_A 132 +#define SRST_VOP_A 133 +#define SRST_VOP_H 134 +#define SRST_VOP_D 135 +#define SRST_RGA 136 +#define SRST_RGA_NIU_A 137 +#define SRST_RGA_A 138 +#define SRST_RGA_H 139 +#define SRST_IEP_A 140 +#define SRST_IEP_H 141 +#define SRST_HDMI 142 +#define SRST_HDMI_P 143 + +#define SRST_HDCP_A 144 +#define SRST_HDCP 145 +#define SRST_HDCP_H 146 +#define SRST_CIF_A 147 +#define SRST_CIF_H 148 +#define SRST_CIF_P 149 +#define SRST_OTP_P 150 +#define SRST_OTP_SBPI 151 +#define SRST_OTP_USER 152 +#define SRST_DDRCTRL_A 153 +#define SRST_DDRSTDY_P 154 +#define SRST_DDRSTDY 155 +#define SRST_PDM_H 156 +#define SRST_PDM 157 +#define SRST_USB3PHY_OTG_P 158 +#define SRST_USB3PHY_PIPE_P 159 + +#define SRST_VCODEC_A 160 +#define SRST_VCODEC_NIU_A 161 +#define SRST_VCODEC_H 162 +#define SRST_VCODEC_NIU_H 163 +#define SRST_VDEC_A 164 +#define SRST_VDEC_NIU_A 165 +#define SRST_VDEC_H 166 +#define SRST_VDEC_NIU_H 167 +#define SRST_VDEC_CORE 168 +#define SRST_VDEC_CABAC 169 +#define SRST_DDRPHYDIV 175 + +#define SRST_RKVENC_NIU_A 176 +#define SRST_RKVENC_NIU_H 177 +#define SRST_RKVENC_H265_A 178 +#define SRST_RKVENC_H265_P 179 +#define SRST_RKVENC_H265_CORE 180 +#define SRST_RKVENC_H265_DSP 181 +#define SRST_RKVENC_H264_A 182 +#define SRST_RKVENC_H264_H 183 +#define SRST_RKVENC_INTMEM 184 + +#endif diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 0a86aec50a..d4bdcc663f 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -122,6 +122,10 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 +#define SCLK_DDRCLK 170 +#define SCLK_TESTOUT2 171 #define DCLK_VOP0 180 #define DCLK_VOP1 181 @@ -589,13 +593,13 @@ #define SRST_P_SPI0 214 #define SRST_P_SPI1 215 #define SRST_P_SPI2 216 -#define SRST_P_SPI3 217 -#define SRST_P_SPI4 218 +#define SRST_P_SPI4 217 +#define SRST_P_SPI5 218 #define SRST_SPI0 219 #define SRST_SPI1 220 #define SRST_SPI2 221 -#define SRST_SPI3 222 -#define SRST_SPI4 223 +#define SRST_SPI4 222 +#define SRST_SPI5 223 /* cru_softrst_con14 */ #define SRST_I2S0_8CH 224 @@ -717,8 +721,8 @@ #define SRST_H_CM0S_NOC 3 #define SRST_DBG_CM0S 4 #define SRST_PO_CM0S 5 -#define SRST_P_SPI6 6 -#define SRST_SPI6 7 +#define SRST_P_SPI3 6 +#define SRST_SPI3 7 #define SRST_P_TIMER_0_1 8 #define SRST_P_TIMER_0 9 #define SRST_P_TIMER_1 10 diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index 56887e14b5..ecb76c7808 100644 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -22,5 +22,7 @@ #define RK_FUNC_2 2 #define RK_FUNC_3 3 #define RK_FUNC_4 4 +#define RK_FUNC_5 5 +#define RK_FUNC_6 6 #endif diff --git a/include/image.h b/include/image.h index 1e686b76d3..2372518960 100644 --- a/include/image.h +++ b/include/image.h @@ -67,7 +67,6 @@ struct lmb; # endif # else # define CONFIG_CRC32 /* FIT images need CRC32 support */ -# define CONFIG_MD5 /* and MD5 */ # define CONFIG_SHA1 /* and SHA1 */ # define CONFIG_SHA256 /* and SHA256 */ # define IMAGE_ENABLE_CRC32 1 diff --git a/include/spl.h b/include/spl.h index bde44374ea..2e5b885c8d 100644 --- a/include/spl.h +++ b/include/spl.h @@ -85,7 +85,7 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image); * This parses the legacy image header information at @header and sets up * @spl_image according to what is found. If no image header is found, then * a raw image or bootz is assumed. If CONFIG_SPL_PANIC_ON_RAW_IMAGE is - * enabled, then this causes a panic. If CONFIG_SPL_ABORT_ON_RAW_IMAGE is + * enabled, then this causes a panic. If CONFIG_SPL_RAW_IMAGE_SUPPORT is not * enabled then U-Boot gives up. Otherwise U-Boot sets up the image using * spl_set_header_raw_uboot(), or possibly the bootz header. * @@ -213,11 +213,29 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image, struct blk_desc *block_dev, int partition); /** - * spl_init() - Set up device tree and driver model in SPL if enabled + * spl_early_init() - Set up device tree and driver model in SPL if enabled * * Call this function in board_init_f() if you want to use device tree and - * driver model early, before board_init_r() is called. This function will - * be called from board_init_r() if not called earlier. + * driver model early, before board_init_r() is called. + * + * If this is not called, then driver model will be inactive in SPL's + * board_init_f(), and no device tree will be available. + */ +int spl_early_init(void); + +/** + * spl_init() - Set up device tree and driver model in SPL if enabled + * + * You can optionally call spl_early_init(), then optionally call spl_init(). + * This function will be called from board_init_r() if not called earlier. + * + * Both spl_early_init() and spl_init() perform a similar function except that + * the latter will not set up the malloc() area if + * CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is enabled, since it is assumed to + * already be done by a calll to spl_relocate_stack_gd() before board_init_r() + * is reached. + * + * This function will be called from board_init_r() if not called earlier. * * If this is not called, then driver model will be inactive in SPL's * board_init_f(), and no device tree will be available. diff --git a/lib/Kconfig b/lib/Kconfig index b16062fbe3..65c01573e1 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -101,6 +101,10 @@ config SHA_PROG_HW_ACCEL SHA1/SHA256 progressive hashing. Data can be streamed in a block at a time and the hashing is performed in hardware. + +config MD5 + bool + endmenu menu "Compression Support" diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 95aa590c8a..db2ae19f59 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -431,11 +431,8 @@ efi_status_t efi_get_memory_map(unsigned long *memory_map_size, return EFI_SUCCESS; } -int efi_memory_init(void) +__weak void efi_add_known_memory(void) { - unsigned long runtime_start, runtime_end, runtime_pages; - unsigned long uboot_start, uboot_pages; - unsigned long uboot_stack_size = 16 * 1024 * 1024; int i; /* Add RAM */ @@ -448,6 +445,15 @@ int efi_memory_init(void) efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, false); } +} + +int efi_memory_init(void) +{ + unsigned long runtime_start, runtime_end, runtime_pages; + unsigned long uboot_start, uboot_pages; + unsigned long uboot_stack_size = 16 * 1024 * 1024; + + efi_add_known_memory(); /* Add U-Boot */ uboot_start = (gd->start_addr_sp - uboot_stack_size) & ~EFI_PAGE_MASK; diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index b52f9963f7..5370648e85 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -215,8 +215,13 @@ $(obj)/$(SPL_BIN)-pad.bin: $(obj)/$(SPL_BIN) # 'u-boot,dm-pre-reloc' property and thus are not needed by SPL. The second # pass removes various unused properties from the remaining nodes. # The output is typically a much smaller device tree file. +ifeq ($(CONFIG_TPL_BUILD),y) +fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-tpl +else +fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-spl +endif quiet_cmd_fdtgrep = FDTGREP $@ - cmd_fdtgrep = $(objtree)/tools/fdtgrep -b u-boot,dm-pre-reloc -RT $< \ + cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -RT $< \ -n /chosen -O dtb | \ $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \ $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS))) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index f38e56cbe3..668f238459 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -509,7 +509,6 @@ CONFIG_CMD_LDRINFO CONFIG_CMD_LOADY CONFIG_CMD_LZMADEC CONFIG_CMD_MAX6957 -CONFIG_CMD_MD5SUM CONFIG_CMD_MEM CONFIG_CMD_MFSL CONFIG_CMD_MMC_SPI @@ -1163,7 +1162,6 @@ CONFIG_FSL_LAYERSCAPE CONFIG_FSL_LBC CONFIG_FSL_LINFLEXUART CONFIG_FSL_MC9SDZ60 -CONFIG_FSL_MC_ENET CONFIG_FSL_MEMAC CONFIG_FSL_NFC_CHIPS CONFIG_FSL_NFC_SPARE_SIZE @@ -1882,8 +1880,6 @@ CONFIG_MCFRTC CONFIG_MCFTMR CONFIG_MCFUART CONFIG_MCLK_DIS -CONFIG_MD5 -CONFIG_MD5SUM_VERIFY CONFIG_MDIO_TIMEOUT CONFIG_MECP5123 CONFIG_MEMSIZE @@ -4976,7 +4972,6 @@ CONFIG_SYS_MCKR_VAL CONFIG_SYS_MCLINK_MAX CONFIG_SYS_MCMEM0_VAL CONFIG_SYS_MCMEM1_VAL -CONFIG_SYS_MC_RSV_MEM_ALIGN CONFIG_SYS_MDC1_PIN CONFIG_SYS_MDCNFG_VAL CONFIG_SYS_MDC_PIN @@ -6850,7 +6845,6 @@ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET CONFIG_ZYNQ_HISPD_BROKEN CONFIG_ZYNQ_I2C0 CONFIG_ZYNQ_I2C1 -CONFIG_ZYNQ_PS_CLK_FREQ CONFIG_ZYNQ_SDHCI0 CONFIG_ZYNQ_SDHCI1 CONFIG_ZYNQ_SDHCI_MAX_FREQ diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py index 6df7b0da13..bf67ec80ca 100755 --- a/tools/dtoc/dtoc.py +++ b/tools/dtoc/dtoc.py @@ -30,6 +30,8 @@ PROP_IGNORE_LIST = [ "status", 'phandle', 'u-boot,dm-pre-reloc', + 'u-boot,dm-tpl', + 'u-boot,dm-spl', ] # C type declarations for the tyues we support diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 0a072aa83c..6595e02c1c 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -46,17 +46,20 @@ struct header0_info { * @imagename: Image name(passed by "mkimage -n") * @spl_hdr: Boot ROM requires a 4-bytes spl header * @spl_size: Spl size(include extra 4-bytes spl header) + * @spl_rc4: RC4 encode the SPL binary (same key as header) */ struct spl_info { const char *imagename; const char *spl_hdr; const uint32_t spl_size; + const bool spl_rc4; }; static struct spl_info spl_infos[] = { - { "rk3036", "RK30", 0x1000 }, - { "rk3288", "RK32", 0x8000 }, - { "rk3399", "RK33", 0x20000 }, + { "rk3036", "RK30", 0x1000, false }, + { "rk3188", "RK31", 0x8000 - 0x800, true }, + { "rk3288", "RK32", 0x8000, false }, + { "rk3399", "RK33", 0x20000, false }, }; static unsigned char rc4_key[16] = { @@ -113,6 +116,16 @@ int rkcommon_get_spl_size(struct image_tool_params *params) return info->spl_size; } +bool rkcommon_need_rc4_spl(struct image_tool_params *params) +{ + struct spl_info *info = rkcommon_get_spl_info(params->imagename); + + /* + * info would not be NULL, because of we checked params before. + */ + return info->spl_rc4; +} + int rkcommon_set_header(void *buf, uint file_size, struct image_tool_params *params) { @@ -124,7 +137,7 @@ int rkcommon_set_header(void *buf, uint file_size, memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE); hdr = (struct header0_info *)buf; hdr->signature = RK_SIGNATURE; - hdr->disable_rc4 = 1; + hdr->disable_rc4 = !rkcommon_need_rc4_spl(params); hdr->init_offset = RK_INIT_OFFSET; hdr->init_size = (file_size + RK_BLK_SIZE - 1) / RK_BLK_SIZE; @@ -135,3 +148,16 @@ int rkcommon_set_header(void *buf, uint file_size, return 0; } + +void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size) +{ + unsigned int remaining = size; + + while (remaining > 0) { + int step = (remaining > RK_BLK_SIZE) ? RK_BLK_SIZE : remaining; + + rc4_encode(buf + offset, step, rc4_key); + offset += RK_BLK_SIZE; + remaining -= step; + } +} diff --git a/tools/rkcommon.h b/tools/rkcommon.h index c69540f5f3..b4f6f327dc 100644 --- a/tools/rkcommon.h +++ b/tools/rkcommon.h @@ -55,4 +55,26 @@ int rkcommon_get_spl_size(struct image_tool_params *params); int rkcommon_set_header(void *buf, uint file_size, struct image_tool_params *params); +/** + * rkcommon_need_rc4_spl() - check if rc4 encoded spl is required + * + * Some socs cannot disable the rc4-encryption of the spl binary. + * rc4 encryption is disabled normally except on socs that cannot + * handle unencrypted binaries. + * @return true or false depending on rc4 being required. + */ +bool rkcommon_need_rc4_spl(struct image_tool_params *params); + +/** + * rkcommon_rc4_encode_spl() - encode the spl binary + * + * Encrypts the SPL binary using the generic rc4 key as required + * by some socs. + * + * @buf: Pointer to the SPL data (header and SPL binary) + * @offset: offset inside buf to start at + * @size: number of bytes to encode + */ +void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size); + #endif diff --git a/tools/rkimage.c b/tools/rkimage.c index ef31cb6944..44d098c775 100644 --- a/tools/rkimage.c +++ b/tools/rkimage.c @@ -28,6 +28,9 @@ static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd, { memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE); + + if (rkcommon_need_rc4_spl(params)) + rkcommon_rc4_encode_spl(buf, 4, params->file_size); } static int rkimage_extract_subimage(void *buf, struct image_tool_params *params) diff --git a/tools/rksd.c b/tools/rksd.c index a2baa74d31..ff2233ff2d 100644 --- a/tools/rksd.c +++ b/tools/rksd.c @@ -41,6 +41,10 @@ static void rksd_set_header(void *buf, struct stat *sbuf, int ifd, memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE); + + if (rkcommon_need_rc4_spl(params)) + rkcommon_rc4_encode_spl(buf, RK_SPL_START - 4, + params->file_size - RK_SPL_START + 4); } static int rksd_extract_subimage(void *buf, struct image_tool_params *params) diff --git a/tools/rkspi.c b/tools/rkspi.c index a0b0051d38..0271d2e817 100644 --- a/tools/rkspi.c +++ b/tools/rkspi.c @@ -48,6 +48,10 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE); + if (rkcommon_need_rc4_spl(params)) + rkcommon_rc4_encode_spl(buf, RK_SPL_START - 4, + params->file_size - RK_SPL_START + 4); + /* * Spread the image out so we only use the first 2KB of each 4KB * region. This is a feature of the SPI format required by the Rockchip |