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-rw-r--r--arch/sandbox/dts/test.dts4
-rw-r--r--drivers/clk/Kconfig10
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/clk_sandbox_ccf.c185
-rw-r--r--include/sandbox-clk.h76
-rw-r--r--test/dm/Makefile2
-rw-r--r--test/dm/clk_ccf.c62
7 files changed, 338 insertions, 2 deletions
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 0dd5e8da5a..9b65adc3f1 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -232,6 +232,10 @@
clock-names = "fixed", "i2c", "spi";
};
+ ccf: clk-ccf {
+ compatible = "sandbox,clk-ccf";
+ };
+
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x10002000 0x1000>;
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9c2b284d02..9399bb79e9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -55,7 +55,7 @@ config SPL_CLK_CCF
config CLK_CCF
bool "Common Clock Framework [CCF] support "
- depends on CLK_IMX6Q
+ depends on CLK_IMX6Q || SANDBOX_CLK_CCF
help
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] code in U-Boot's clock driver.
@@ -138,4 +138,12 @@ config CLK_MPC83XX
help
Support for the clock driver of the MPC83xx series of SoCs.
+config SANDBOX_CLK_CCF
+ bool "Sandbox Common Clock Framework [CCF] support "
+ depends on SANDBOX
+ select CLK_CCF
+ help
+ Enable this option if you want to test the Linux kernel's Common
+ Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
+
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1a45bf3505..37dfd281e9 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -38,5 +38,6 @@ obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
+obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c
new file mode 100644
index 0000000000..edeb0f2cf3
--- /dev/null
+++ b/drivers/clk/clk_sandbox_ccf.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Common Clock Framework [CCF] driver for Sandbox
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <asm/clk.h>
+#include <clk-uclass.h>
+#include <linux/clk-provider.h>
+#include <sandbox-clk.h>
+
+/*
+ * Sandbox implementation of CCF primitives necessary for clk-uclass testing
+ *
+ * --- Sandbox PLLv3 ---
+ */
+struct clk_pllv3 {
+ struct clk clk;
+ u32 div_mask;
+ u32 div_shift;
+};
+
+static ulong clk_pllv3_get_rate(struct clk *clk)
+{
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+
+ return parent_rate * 24;
+}
+
+static const struct clk_ops clk_pllv3_generic_ops = {
+ .get_rate = clk_pllv3_get_rate,
+};
+
+struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base,
+ u32 div_mask)
+{
+ struct clk_pllv3 *pll;
+ struct clk *clk;
+ char *drv_name = "sandbox_clk_pllv3";
+ int ret;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->div_mask = div_mask;
+ clk = &pll->clk;
+
+ ret = clk_register(clk, drv_name, name, parent_name);
+ if (ret) {
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
+ .name = "sandbox_clk_pllv3",
+ .id = UCLASS_CLK,
+ .ops = &clk_pllv3_generic_ops,
+};
+
+/* --- Sandbox PLLv3 --- */
+/* --- Sandbox Gate --- */
+struct clk_gate2 {
+ struct clk clk;
+ bool state;
+};
+
+#define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
+
+static int clk_gate2_enable(struct clk *clk)
+{
+ struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+
+ gate->state = 1;
+ return 0;
+}
+
+static int clk_gate2_disable(struct clk *clk)
+{
+ struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
+
+ gate->state = 0;
+ return 0;
+}
+
+static const struct clk_ops clk_gate2_ops = {
+ .enable = clk_gate2_enable,
+ .disable = clk_gate2_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name,
+ unsigned long flags, void __iomem *reg,
+ u8 bit_idx, u8 cgr_val,
+ u8 clk_gate2_flags)
+{
+ struct clk_gate2 *gate;
+ struct clk *clk;
+ int ret;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ gate->state = 0;
+ clk = &gate->clk;
+
+ ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
+ if (ret) {
+ kfree(gate);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(sandbox_clk_gate2) = {
+ .name = "sandbox_clk_gate2",
+ .id = UCLASS_CLK,
+ .ops = &clk_gate2_ops,
+};
+
+/* --- Sandbox Gate --- */
+/* The CCF core driver itself */
+static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
+ { .compatible = "sandbox,clk-ccf" },
+ { }
+};
+
+static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
+
+static int sandbox_clk_ccf_probe(struct udevice *dev)
+{
+ void *base = NULL;
+ u32 reg;
+
+ clk_dm(SANDBOX_CLK_PLL3,
+ sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
+ base + 0x10, 0x3));
+
+ clk_dm(SANDBOX_CLK_PLL3_60M,
+ sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
+
+ clk_dm(SANDBOX_CLK_PLL3_80M,
+ sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
+
+ /* The HW adds +1 to the divider value (2+1) is the divider */
+ reg = (2 << 19);
+ clk_dm(SANDBOX_CLK_ECSPI_ROOT,
+ sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
+
+ clk_dm(SANDBOX_CLK_ECSPI1,
+ sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
+
+ /* Select 'pll3_60m' */
+ reg = 0;
+ clk_dm(SANDBOX_CLK_USDHC1_SEL,
+ sandbox_clk_mux("usdhc1_sel", &reg, 16, 1, usdhc_sels,
+ ARRAY_SIZE(usdhc_sels)));
+
+ /* Select 'pll3_80m' */
+ reg = BIT(17);
+ clk_dm(SANDBOX_CLK_USDHC2_SEL,
+ sandbox_clk_mux("usdhc2_sel", &reg, 17, 1, usdhc_sels,
+ ARRAY_SIZE(usdhc_sels)));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(sandbox_clk_ccf) = {
+ .name = "sandbox_clk_ccf",
+ .id = UCLASS_CLK,
+ .probe = sandbox_clk_ccf_probe,
+ .of_match = sandbox_clk_ccf_test_ids,
+};
diff --git a/include/sandbox-clk.h b/include/sandbox-clk.h
new file mode 100644
index 0000000000..37c9838f76
--- /dev/null
+++ b/include/sandbox-clk.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#ifndef __SANDBOX_CLK_H__
+#define __SANDBOX_CLK_H__
+
+#include <linux/clk-provider.h>
+
+enum {
+ SANDBOX_CLK_PLL2 = 1,
+ SANDBOX_CLK_PLL3,
+ SANDBOX_CLK_PLL3_60M,
+ SANDBOX_CLK_PLL3_80M,
+ SANDBOX_CLK_ECSPI_ROOT,
+ SANDBOX_CLK_ECSPI0,
+ SANDBOX_CLK_ECSPI1,
+ SANDBOX_CLK_USDHC1_SEL,
+ SANDBOX_CLK_USDHC2_SEL,
+};
+
+enum sandbox_pllv3_type {
+ SANDBOX_PLLV3_GENERIC,
+ SANDBOX_PLLV3_USB,
+};
+
+struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base,
+ u32 div_mask);
+
+static inline struct clk *sandbox_clk_fixed_factor(const char *name,
+ const char *parent,
+ unsigned int mult,
+ unsigned int div)
+{
+ return clk_register_fixed_factor(NULL, name, parent,
+ CLK_SET_RATE_PARENT, mult, div);
+}
+
+static inline struct clk *sandbox_clk_divider(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift,
+ u8 width)
+{
+ return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ reg, shift, width, 0);
+}
+
+struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name,
+ unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 cgr_val, u8 clk_gate_flags);
+
+static inline struct clk *sandbox_clk_gate2(const char *name,
+ const char *parent,
+ void __iomem *reg, u8 shift)
+{
+ return sandbox_clk_register_gate2(NULL, name, parent,
+ CLK_SET_RATE_PARENT, reg, shift,
+ 0x3, 0);
+}
+
+static inline struct clk *sandbox_clk_mux(const char *name, void __iomem *reg,
+ u8 shift, u8 width,
+ const char * const *parents,
+ int num_parents)
+{
+ return clk_register_mux(NULL, name, parents, num_parents,
+ CLK_SET_RATE_NO_REPARENT, reg, shift,
+ width, 0);
+}
+
+#endif /* __SANDBOX_CLK_H__ */
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 6a36cc0a32..9c5e860108 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -17,7 +17,7 @@ obj-$(CONFIG_SOUND) += audio.o
obj-$(CONFIG_BLK) += blk.o
obj-$(CONFIG_BOARD) += board.o
obj-$(CONFIG_DM_BOOTCOUNT) += bootcount.o
-obj-$(CONFIG_CLK) += clk.o
+obj-$(CONFIG_CLK) += clk.o clk_ccf.o
obj-$(CONFIG_DM_ETH) += eth.o
obj-$(CONFIG_FIRMWARE) += firmware.o
obj-$(CONFIG_DM_GPIO) += gpio.o
diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
new file mode 100644
index 0000000000..8d397593a3
--- /dev/null
+++ b/test/dm/clk_ccf.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/clk.h>
+#include <dm/test.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <test/ut.h>
+#include <sandbox-clk.h>
+
+/* Tests for Common Clock Framework driver */
+static int dm_test_clk_ccf(struct unit_test_state *uts)
+{
+ struct clk *clk, *pclk;
+ struct udevice *dev;
+ long long rate;
+ int ret;
+
+ /* Get the device using the clk device */
+ ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
+
+ /* Test for clk_get_by_id() */
+ ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("ecspi_root", clk->dev->name);
+
+ /* Test for clk_get_parent_rate() */
+ ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("ecspi1", clk->dev->name);
+
+ rate = clk_get_parent_rate(clk);
+ ut_asserteq(rate, 20000000);
+
+ /* Test the mux of CCF */
+ ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("usdhc1_sel", clk->dev->name);
+
+ rate = clk_get_parent_rate(clk);
+ ut_asserteq(rate, 60000000);
+
+ ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
+ ut_assertok(ret);
+ ut_asserteq_str("usdhc2_sel", clk->dev->name);
+
+ rate = clk_get_parent_rate(clk);
+ ut_asserteq(rate, 80000000);
+
+ pclk = clk_get_parent(clk);
+ ut_asserteq_str("pll3_80m", pclk->dev->name);
+
+ return 1;
+}
+
+DM_TEST(dm_test_clk_ccf, DM_TESTF_SCAN_FDT);
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