summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi5
-rw-r--r--arch/arm/dts/stm32mp15-pinctrl.dtsi80
-rw-r--r--arch/riscv/dts/k210-maix-bit.dts2
-rw-r--r--board/CZ.NIC/turris_omnia/turris_omnia.c2
-rw-r--r--board/Marvell/db-88f6820-amc/db-88f6820-amc.c1
-rw-r--r--board/Marvell/db-88f6820-gp/db-88f6820-gp.c1
-rw-r--r--board/alliedtelesis/x530/x530.c1
-rw-r--r--board/gdsys/a38x/controlcenterdc.c1
-rw-r--r--board/kobol/helios4/helios4.c1
-rw-r--r--board/samsung/common/misc.c27
-rw-r--r--board/samsung/espresso7420/MAINTAINERS2
-rw-r--r--board/samsung/goni/MAINTAINERS2
-rw-r--r--board/samsung/origen/MAINTAINERS2
-rw-r--r--board/samsung/smdk5250/MAINTAINERS4
-rw-r--r--board/samsung/smdk5420/MAINTAINERS2
-rw-r--r--board/samsung/smdkv310/MAINTAINERS2
-rw-r--r--board/solidrun/clearfog/clearfog.c1
-rw-r--r--cmd/riscv/sbi.c1
-rw-r--r--cmd/sf.c29
-rw-r--r--configs/stm32mp15_basic_defconfig3
-rw-r--r--configs/stm32mp15_trusted_defconfig3
-rw-r--r--configs/turris_mox_defconfig3
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_init.c5
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_training.c5
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_training_db.c3
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_training_ip_def.h2
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c5
-rw-r--r--drivers/ddr/marvell/a38x/ddr_topology_def.h23
-rw-r--r--drivers/ddr/marvell/a38x/mv_ddr_build_message.c2
-rw-r--r--drivers/ddr/marvell/a38x/mv_ddr_plat.c9
-rw-r--r--drivers/ddr/marvell/a38x/mv_ddr_topology.c14
-rw-r--r--drivers/ddr/marvell/a38x/mv_ddr_topology.h2
-rw-r--r--drivers/ddr/marvell/a38x/xor.c6
-rw-r--r--drivers/mtd/nand/spi/gigadevice.c79
-rw-r--r--drivers/mtd/spi/spi-nor-ids.c10
-rw-r--r--drivers/pci/pci-aardvark.c8
-rw-r--r--drivers/pci/pci_mvebu.c76
-rw-r--r--drivers/power/pmic/Makefile2
-rw-r--r--drivers/power/pmic/pmic_max8997.c107
-rw-r--r--drivers/power/pmic/pmic_max8998.c32
-rw-r--r--drivers/serial/Kconfig7
-rw-r--r--drivers/serial/Makefile2
-rw-r--r--drivers/spi/mxc_spi.c5
-rw-r--r--drivers/spi/nxp_fspi.c4
-rw-r--r--include/configs/stm32mp1.h7
-rw-r--r--include/linux/mtd/spi-nor.h22
46 files changed, 281 insertions, 331 deletions
diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
index 1b46797583..af0655daaa 100644
--- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
+++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
@@ -41,10 +41,7 @@
&spi0 {
u-boot,dm-pre-reloc;
- spi-flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
+ spi-nor@0 {
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index dd4bd1e554..20a59e8f7a 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -1971,86 +1971,6 @@
};
};
- uart4_pins_a: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_pins_b: uart4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_pins_c: uart4-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart7_pins_a: uart7-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
- <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
- <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
- bias-disable;
- };
- };
-
- uart7_pins_b: uart7-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
- bias-disable;
- };
- };
-
- uart8_pins_a: uart8-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
- bias-disable;
- };
- };
-
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
index e4dea205b2..902dcfd08a 100644
--- a/arch/riscv/dts/k210-maix-bit.dts
+++ b/arch/riscv/dts/k210-maix-bit.dts
@@ -200,6 +200,8 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
m25p,fast-read;
broken-flash-reset;
};
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 0353d58a36..1d3cefe703 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -286,6 +286,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = {
MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
@@ -308,6 +309,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = {
MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
index 163a1b3de9..122c63d11f 100644
--- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -73,6 +73,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index 06307e582c..1edc1cb651 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -94,6 +94,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index d602092d73..7bcfa828d7 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -68,6 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT_ECC, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ {0} }, /* electrical configuration */
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index ba57a27218..4f1dc3b431 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -71,6 +71,7 @@ static struct mv_ddr_topology_map ddr_topology_map = {
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c
index adb091ce4f..9c5b687b3e 100644
--- a/board/kobol/helios4/helios4.c
+++ b/board/kobol/helios4/helios4.c
@@ -71,6 +71,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT_ECC, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index d48ba7eaf0..b3b1bbcc82 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -117,32 +117,33 @@ void set_board_info(void)
#ifdef CONFIG_LCD_MENU
static int power_key_pressed(u32 reg)
{
-#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
- struct pmic *pmic;
+ struct udevice *dev;
+ int ret;
u32 status;
u32 mask;
- pmic = pmic_get(KEY_PWR_PMIC_NAME);
- if (!pmic) {
- printf("%s: Not found\n", KEY_PWR_PMIC_NAME);
+ if (IS_ENABLED(CONFIG_TARGET_TRATS))
+ ret = pmic_get("max8997-pmic", &dev);
+ else if (IS_ENABLED(CONFIG_TARGET_TRATS2))
+ ret = pmic_get("max77686-pmic", &dev);
+ else if (IS_ENABLED(CONFIG_TARGET_S5PC210_UNIVERSAL))
+ ret = pmic_get("max8998-pmic", &dev);
+ else
return 0;
- }
- if (pmic_probe(pmic))
- return 0;
+ if (ret)
+ return ret;
if (reg == KEY_PWR_STATUS_REG)
mask = KEY_PWR_STATUS_MASK;
else
mask = KEY_PWR_INTERRUPT_MASK;
- if (pmic_reg_read(pmic, reg, &status))
- return 0;
+ status = pmic_reg_read(dev, reg);
+ if (status < 0)
+ return status;
return !!(status & mask);
-#else
- return 0;
-#endif
}
static int key_pressed(int key)
diff --git a/board/samsung/espresso7420/MAINTAINERS b/board/samsung/espresso7420/MAINTAINERS
index e3b2394cce..9145ad45ed 100644
--- a/board/samsung/espresso7420/MAINTAINERS
+++ b/board/samsung/espresso7420/MAINTAINERS
@@ -1,5 +1,5 @@
ESPRESSO7420 Board
-M: Thomas Abraham <thomas.ab@samsung.com>
+M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
F: board/samsung/espresso7420/
F: include/configs/espresso7420.h
diff --git a/board/samsung/goni/MAINTAINERS b/board/samsung/goni/MAINTAINERS
index 248ec3cc0c..7643f9c89e 100644
--- a/board/samsung/goni/MAINTAINERS
+++ b/board/samsung/goni/MAINTAINERS
@@ -1,5 +1,5 @@
GONI BOARD
-M: Robert Baldyga <r.baldyga@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/goni/
F: include/configs/s5p_goni.h
diff --git a/board/samsung/origen/MAINTAINERS b/board/samsung/origen/MAINTAINERS
index 8bf373e05d..8fb8f81151 100644
--- a/board/samsung/origen/MAINTAINERS
+++ b/board/samsung/origen/MAINTAINERS
@@ -1,5 +1,5 @@
ORIGEN BOARD
-M: Chander Kashyap <k.chander@samsung.com>
+M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
F: board/samsung/origen/
F: include/configs/origen.h
diff --git a/board/samsung/smdk5250/MAINTAINERS b/board/samsung/smdk5250/MAINTAINERS
index cde966fdbf..c60b6f81e9 100644
--- a/board/samsung/smdk5250/MAINTAINERS
+++ b/board/samsung/smdk5250/MAINTAINERS
@@ -1,12 +1,12 @@
SMDK5250 BOARD
-M: Chander Kashyap <k.chander@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/smdk5250/
F: include/configs/smdk5250.h
F: configs/smdk5250_defconfig
SNOW BOARD
-M: Akshay Saraswat <akshay.s@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: include/configs/snow.h
F: configs/snow_defconfig
diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS
index 31c00360f2..217ff71e32 100644
--- a/board/samsung/smdk5420/MAINTAINERS
+++ b/board/samsung/smdk5420/MAINTAINERS
@@ -1,5 +1,5 @@
SMDK5420 BOARD
-M: Akshay Saraswat <akshay.s@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/smdk5420/
F: include/configs/peach-pit.h
diff --git a/board/samsung/smdkv310/MAINTAINERS b/board/samsung/smdkv310/MAINTAINERS
index 1e058cb504..4fa1531556 100644
--- a/board/samsung/smdkv310/MAINTAINERS
+++ b/board/samsung/smdkv310/MAINTAINERS
@@ -1,5 +1,5 @@
SMDKV310 BOARD
-M: Chander Kashyap <k.chander@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/smdkv310/
F: include/configs/smdkv310.h
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index 7b2accf01d..c920cf8d6b 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -142,6 +142,7 @@ static struct mv_ddr_topology_map board_topology_map = {
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ {0} }, /* electrical configuration */
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index 2c905f1f8f..90c0811e14 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -43,6 +43,7 @@ static struct sbi_ext extensions[] = {
{ 0x00735049, "IPI Extension" },
{ 0x52464E43, "RFENCE Extension" },
{ 0x0048534D, "Hart State Management Extension" },
+ { 0x53525354, "System Reset Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/cmd/sf.c b/cmd/sf.c
index c0d6a8f8a0..46346fb9d4 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -344,8 +344,11 @@ static int do_spi_flash_erase(int argc, char *const argv[])
}
ret = spi_flash_erase(flash, offset, size);
- printf("SF: %zu bytes @ %#x Erased: %s\n", (size_t)size, (u32)offset,
- ret ? "ERROR" : "OK");
+ printf("SF: %zu bytes @ %#x Erased: ", (size_t)size, (u32)offset);
+ if (ret)
+ printf("ERROR %d\n", ret);
+ else
+ printf("OK\n");
return ret == 0 ? 0 : 1;
}
@@ -442,20 +445,22 @@ static int spi_flash_test(struct spi_flash *flash, uint8_t *buf, ulong len,
ulong offset, uint8_t *vbuf)
{
struct test_info test;
- int i;
+ int err, i;
printf("SPI flash test:\n");
memset(&test, '\0', sizeof(test));
test.base_ms = get_timer(0);
test.bytes = len;
- if (spi_flash_erase(flash, offset, len)) {
- printf("Erase failed\n");
+ err = spi_flash_erase(flash, offset, len);
+ if (err) {
+ printf("Erase failed (err = %d)\n", err);
return -1;
}
spi_test_next_stage(&test);
- if (spi_flash_read(flash, offset, len, vbuf)) {
- printf("Check read failed\n");
+ err = spi_flash_read(flash, offset, len, vbuf);
+ if (err) {
+ printf("Check read failed (err = %d)\n", err);
return -1;
}
for (i = 0; i < len; i++) {
@@ -468,15 +473,17 @@ static int spi_flash_test(struct spi_flash *flash, uint8_t *buf, ulong len,
}
spi_test_next_stage(&test);
- if (spi_flash_write(flash, offset, len, buf)) {
- printf("Write failed\n");
+ err = spi_flash_write(flash, offset, len, buf);
+ if (err) {
+ printf("Write failed (err = %d)\n", err);
return -1;
}
memset(vbuf, '\0', len);
spi_test_next_stage(&test);
- if (spi_flash_read(flash, offset, len, vbuf)) {
- printf("Read failed\n");
+ err = spi_flash_read(flash, offset, len, vbuf);
+ if (err) {
+ printf("Read failed (ret = %d)\n", err);
return -1;
}
spi_test_next_stage(&test);
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index def6a51b40..1c680984b8 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -34,6 +34,7 @@ CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ADC=y
@@ -49,6 +50,7 @@ CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
@@ -164,4 +166,5 @@ CONFIG_BMP_32BPP=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_ERRNO_STR=y
+# CONFIG_HEXDUMP is not set
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index da31b74cde..107041119f 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -17,6 +17,7 @@ CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ADC=y
@@ -32,6 +33,7 @@ CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
@@ -144,4 +146,5 @@ CONFIG_BMP_32BPP=y
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_ERRNO_STR=y
+# CONFIG_HEXDUMP is not set
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index dde7437f24..f938fbb475 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -61,10 +61,10 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
+CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_AARDVARK=y
-# CONFIG_PCI_PNP is not set
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
@@ -78,6 +78,7 @@ CONFIG_MVEBU_A3700_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index a971cc155a..7488770268 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -104,6 +104,7 @@ int ddr3_init(void)
static int mv_ddr_training_params_set(u8 dev_num)
{
struct tune_train_params params;
+ struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
int status;
u32 cs_num;
int ck_delay;
@@ -136,6 +137,10 @@ static int mv_ddr_training_params_set(u8 dev_num)
if (ck_delay > 0)
params.ck_delay = ck_delay;
+ /* Use platform specific override ODT value */
+ if (tm->odt_config)
+ params.g_odt_config = tm->odt_config;
+
status = ddr3_tip_tune_training_params(dev_num, &params);
if (MV_OK != status) {
printf("%s Training Sequence - FAILED\n", ddr_type);
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 34cc170910..2b3af23202 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -143,6 +143,7 @@ static struct reg_data odpg_default_value[] = {
{0x15a4, 0x0, MASK_ALL_BITS},
{0x15a8, 0x0, MASK_ALL_BITS},
{0x15ac, 0x0, MASK_ALL_BITS},
+ {0x1600, 0x0, MASK_ALL_BITS},
{0x1604, 0x0, MASK_ALL_BITS},
{0x1608, 0x0, MASK_ALL_BITS},
{0x160c, 0x0, MASK_ALL_BITS},
@@ -218,7 +219,7 @@ static int ddr3_tip_pad_inv(void)
DDR_PHY_CONTROL,
PHY_CTRL_PHY_REG,
data, data);
-#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 && !A3900 */
+#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */
#pragma message "unknown platform to configure ddr clock swap"
#endif
}
@@ -1569,6 +1570,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
val = ((cl_mask_table[cl_value] & 0x1) << 2) |
((cl_mask_table[cl_value] & 0xe) << 3);
+ cs_mask[0] = 0xc;
+
CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0,
val, (0x7 << 4) | (0x1 << 2)));
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c
index b2f11a8399..6aa7b6069e 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_db.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c
@@ -833,6 +833,9 @@ u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index)
pattern = pattern_table_get_isi_word16(index);
break;
default:
+ if (((int)type == 29) || ((int)type == 30))
+ break;
+
printf("error: %s: unsupported pattern type [%d] found\n",
__func__, (int)type);
pattern = 0;
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
index 2a68669f36..8765df7cfb 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
@@ -80,6 +80,8 @@
#define ADDR_SIZE_2GB 0x10000000
#define ADDR_SIZE_4GB 0x20000000
#define ADDR_SIZE_8GB 0x40000000
+#define ADDR_SIZE_16GB 0x80000000
+
enum hws_edge_compare {
EDGE_PF,
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
index 979f3530b7..5fd9a052fa 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
@@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num)
DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
}
- for (pattern = 0; pattern < PATTERN_LAST; pattern++)
+ for (pattern = 0; pattern < PATTERN_LAST; pattern++) {
+ if (pattern == PATTERN_TEST)
+ continue;
ddr3_tip_load_pattern_to_mem(dev_num, pattern);
+ }
return MV_OK;
}
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 34196b1662..7f2317edfa 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -14,6 +14,11 @@
#define MV_DDR_MAX_BUS_NUM 9
#define MV_DDR_MAX_IFACE_NUM 1
+enum mv_ddr_twin_die {
+ NOT_COMBINED,
+ COMBINED,
+};
+
struct bus_params {
/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
u8 cs_bitmask;
@@ -113,6 +118,9 @@ struct mv_ddr_topology_map {
/* source of ddr configuration data */
enum mv_ddr_cfg_src cfg_src;
+ /* ddr twin-die */
+ enum mv_ddr_twin_die twin_die_combined;
+
/* raw spd data */
union mv_ddr_spd_data spd_data;
@@ -125,6 +133,9 @@ struct mv_ddr_topology_map {
/* electrical parameters */
unsigned int electrical_data[MV_DDR_EDATA_LAST];
+ /* ODT configuration */
+ u32 odt_config;
+
/* Clock enable mask */
u32 clk_enable;
@@ -148,7 +159,13 @@ enum mv_ddr_validation {
MV_DDR_VAL_DIS,
MV_DDR_VAL_RX,
MV_DDR_VAL_TX,
- MV_DDR_VAL_RX_TX
+ MV_DDR_VAL_RX_TX,
+ MV_DDR_MEMORY_CHECK
+};
+
+enum mv_ddr_sscg {
+ SSCG_EN,
+ SSCG_DIS,
};
struct mv_ddr_iface {
@@ -179,8 +196,12 @@ struct mv_ddr_iface {
/* ddr interface validation mode */
enum mv_ddr_validation validation;
+ /* ddr interface validation mode */
+ enum mv_ddr_sscg sscg;
+
/* ddr interface topology map */
struct mv_ddr_topology_map tm;
+
};
struct mv_ddr_iface *mv_ddr_iface_get(void);
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
index cc6234fd40..a2bb8a96a6 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
@@ -1,3 +1,3 @@
// SPDX-License-Identifier: GPL-2.0
const char mv_ddr_build_message[] = "";
-const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2";
+const char mv_ddr_version_string[] = "mv_ddr: 14.0.0";
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 72f0dfbbbb..0d1df189e8 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -4,6 +4,7 @@
*/
#include "ddr3_init.h"
+#include "mv_ddr_common.h"
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
#include "mv_ddr_sys_env_lib.h"
@@ -1016,7 +1017,7 @@ int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size)
return MV_BAD_VALUE;
}
- *cs_size = cs_mem_size << 20; /* write cs size in bytes */
+ *cs_size = cs_mem_size;
return MV_OK;
}
@@ -1025,9 +1026,11 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
{
u32 reg, cs;
uint64_t mem_total_size = 0;
+ uint64_t cs_mem_size_mb = 0;
uint64_t cs_mem_size = 0;
uint64_t mem_total_size_c, cs_mem_size_c;
+
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
u32 physical_mem_size;
u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
@@ -1038,8 +1041,9 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
for (cs = 0; cs < MAX_CS_NUM; cs++) {
if (cs_ena & (1 << cs)) {
/* get CS size */
- if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK)
+ if (ddr3_calc_mem_cs_size(cs, &cs_mem_size_mb) != MV_OK)
return MV_FAIL;
+ cs_mem_size = cs_mem_size_mb * _1M;
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
/*
@@ -1088,6 +1092,7 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
*/
mem_total_size_c = (mem_total_size >> 16) & 0xffffffffffff;
cs_mem_size_c = (cs_mem_size >> 16) & 0xffffffffffff;
+
/* if the sum less than 2 G - calculate the value */
if (mem_total_size_c + cs_mem_size_c < 0x10000)
mem_total_size += cs_mem_size;
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 09840b1e70..2db6283c23 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -127,6 +127,11 @@ int mv_ddr_topology_map_update(void)
speed_bin_index = iface_params->speed_bin_index;
freq = iface_params->memory_freq;
+ if (tm->twin_die_combined == COMBINED) {
+ iface_params->bus_width = MV_DDR_DEV_WIDTH_8BIT;
+ iface_params->memory_size -= 1;
+ }
+
if (iface_params->cas_l == 0)
iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
@@ -144,6 +149,9 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
if (tm->cfg_src == MV_DDR_CFG_SPD) {
+ if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
+ tm->spd_data.byte_fields.byte_13.bit_fields.primary_bus_width = MV_DDR_PRI_BUS_WIDTH_32;
+
enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
@@ -151,7 +159,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
case MV_DDR_PRI_BUS_WIDTH_16:
pri_and_ext_bus_width = BUS_MASK_16BIT;
break;
- case MV_DDR_PRI_BUS_WIDTH_32:
+ case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/
pri_and_ext_bus_width = BUS_MASK_32BIT;
break;
case MV_DDR_PRI_BUS_WIDTH_64:
@@ -245,7 +253,8 @@ static unsigned int mem_size[] = {
ADDR_SIZE_1GB,
ADDR_SIZE_2GB,
ADDR_SIZE_4GB,
- ADDR_SIZE_8GB
+ ADDR_SIZE_8GB,
+ ADDR_SIZE_16GB
/* TODO: add capacity up to 256GB */
};
@@ -277,7 +286,6 @@ unsigned long long mv_ddr_mem_sz_per_cs_get(void)
mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
(unsigned long long)sphys /
(unsigned long long)sphys_per_dunit;
-
return mem_sz_per_cs;
}
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
index 4fca47689f..1cb69ad085 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
@@ -179,7 +179,9 @@ enum mv_ddr_dic_evalue {
/* phy electrical configuration values */
enum mv_ddr_ohm_evalue {
+ MV_DDR_OHM_20 = 20,/*relevant for Synopsys C/A Drive strength only*/
MV_DDR_OHM_30 = 30,
+ MV_DDR_OHM_40 = 40,/*relevant for Synopsys C/A Drive strength only*/
MV_DDR_OHM_48 = 48,
MV_DDR_OHM_60 = 60,
MV_DDR_OHM_80 = 80,
diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c
index 5fb9e216d3..98fb39eaf0 100644
--- a/drivers/ddr/marvell/a38x/xor.c
+++ b/drivers/ddr/marvell/a38x/xor.c
@@ -340,7 +340,7 @@ void ddr3_new_tip_ecc_scrub(void)
{
u32 cs_c, max_cs;
u32 cs_ena = 0;
- uint64_t total_mem_size, cs_mem_size = 0;
+ uint64_t total_mem_size, cs_mem_size_mb = 0, cs_mem_size = 0;
printf("DDR Training Sequence - Start scrubbing\n");
max_cs = mv_ddr_cs_num_get();
@@ -349,9 +349,9 @@ void ddr3_new_tip_ecc_scrub(void)
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
/* all chip-selects are of same size */
- ddr3_calc_mem_cs_size(0, &cs_mem_size);
+ ddr3_calc_mem_cs_size(0, &cs_mem_size_mb);
#endif
-
+ cs_mem_size = cs_mem_size_mb * _1M;
mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
total_mem_size = max_cs * cs_mem_size;
mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef);
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index 0b228dcb5b..a2c93486f4 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -17,9 +17,22 @@
#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
-#define GD5FXGQ4XEXXG_REG_STATUS2 0xf0
+#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4)
+#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4)
-static SPINAND_OP_VARIANTS(read_cache_variants,
+#define GD5FXGQXXEXXG_REG_STATUS2 0xf0
+
+/* Q4 devices, QUADIO: Dummy bytes valid for 1 and 2 GBit variants */
+static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */
+static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
@@ -35,7 +48,7 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
-static int gd5fxgq4xexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
+static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
@@ -47,7 +60,7 @@ static int gd5fxgq4xexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
return 0;
}
-static int gd5fxgq4xexxg_ooblayout_free(struct mtd_info *mtd, int section,
+static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
@@ -64,7 +77,7 @@ static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
u8 status2;
- struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4XEXXG_REG_STATUS2,
+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
&status2);
int ret;
@@ -102,21 +115,67 @@ static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand,
return -EINVAL;
}
-static const struct mtd_ooblayout_ops gd5fxgq4xexxg_ooblayout = {
- .ecc = gd5fxgq4xexxg_ooblayout_ecc,
- .rfree = gd5fxgq4xexxg_ooblayout_free,
+static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ u8 status2;
+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
+ &status2);
+ int ret;
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS:
+ /*
+ * Read status2 register to determine a more fine grained
+ * bit error status
+ */
+ ret = spi_mem_exec_op(spinand->slave, &op);
+ if (ret)
+ return ret;
+
+ /*
+ * 1 ... 4 bits are flipped (and corrected)
+ */
+ /* bits sorted this way (1...0): ECCSE1, ECCSE0 */
+ return ((status2 & STATUS_ECC_MASK) >> 4) + 1;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = {
+ .ecc = gd5fxgqxxexxg_ooblayout_ecc,
+ .rfree = gd5fxgqxxexxg_ooblayout_free,
};
static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ SPINAND_INFO_OP_VARIANTS(&gd5fxgq4_read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
- SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout,
+ SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
gd5fxgq4xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ5UExxG", 0x51,
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
};
static int gigadevice_spinand_detect(struct spinand_device *spinand)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 5bd5dd3003..2b57797954 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -108,6 +108,11 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
+ INFO("gd25lq64c", 0xc86017, 0, 64 * 1024, 128,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -319,7 +324,10 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 8713b88461..b4e1b60240 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -42,6 +42,10 @@
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_TRAINING BIT(5)
#define PCIE_CORE_ERR_CAPCTL_REG 0x118
@@ -534,6 +538,10 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE <<
+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) |
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE <<
+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 235d9bb90c..0c1d7cd770 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -79,7 +79,8 @@ struct mvebu_pcie {
u32 lane;
int devfn;
u32 lane_mask;
- pci_dev_t dev;
+ int first_busno;
+ int local_dev;
char name[16];
unsigned int mem_target;
unsigned int mem_attr;
@@ -144,38 +145,47 @@ static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
return container_of(hose, struct mvebu_pcie, hose);
}
+static int mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, pci_dev_t bdf)
+{
+ /*
+ * There are two devices visible on local bus:
+ * * on slot configured by function mvebu_pcie_set_local_dev_nr()
+ * (by default this register is set to 0) there is a
+ * "Marvell Memory controller", which isn't useful in root complex
+ * mode,
+ * * on all other slots the real PCIe card connected to the PCIe slot.
+ *
+ * We therefore allow access only to the real PCIe card.
+ */
+ if (PCI_BUS(bdf) == pcie->first_busno &&
+ PCI_DEV(bdf) != !pcie->local_dev)
+ return 0;
+
+ return 1;
+}
+
static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,
enum pci_size_t size)
{
struct mvebu_pcie *pcie = dev_get_plat(bus);
- int local_bus = PCI_BUS(pcie->dev);
- int local_dev = PCI_DEV(pcie->dev);
- u32 reg;
u32 data;
- debug("PCIE CFG read: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ",
- local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
- /* Don't access the local host controller via this API */
- if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) {
- debug("- skipping host controller\n");
- *valuep = pci_get_ff(size);
- return 0;
- }
-
- /* If local dev is 0, the first other dev can only be 1 */
- if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) {
+ if (!mvebu_pcie_valid_addr(pcie, bdf)) {
debug("- out of range\n");
*valuep = pci_get_ff(size);
return 0;
}
/* write address */
- reg = PCIE_CONF_ADDR(bdf, offset);
- writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
+ writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
+
+ /* read data */
data = readl(pcie->base + PCIE_CONF_DATA_OFF);
- debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data);
+ debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
*valuep = pci_conv_32_to_size(data, offset, size);
return 0;
@@ -186,27 +196,21 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
enum pci_size_t size)
{
struct mvebu_pcie *pcie = dev_get_plat(bus);
- int local_bus = PCI_BUS(pcie->dev);
- int local_dev = PCI_DEV(pcie->dev);
u32 data;
- debug("PCIE CFG write: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ",
- local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
- debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
-
- /* Don't access the local host controller via this API */
- if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) {
- debug("- skipping host controller\n");
- return 0;
- }
+ debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
- /* If local dev is 0, the first other dev can only be 1 */
- if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) {
+ if (!mvebu_pcie_valid_addr(pcie, bdf)) {
debug("- out of range\n");
return 0;
}
+ /* write address */
writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
+
+ /* write data */
data = pci_conv_size_to_32(0, value, offset, size);
writel(data, pcie->base + PCIE_CONF_DATA_OFF);
@@ -273,7 +277,7 @@ static int mvebu_pcie_probe(struct udevice *dev)
struct mvebu_pcie *pcie = dev_get_plat(dev);
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
- static int bus;
+ int bus = dev_seq(dev);
u32 reg;
debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
@@ -284,9 +288,11 @@ static int mvebu_pcie_probe(struct udevice *dev)
readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
mvebu_pcie_get_local_dev_nr(pcie));
+ pcie->first_busno = bus;
+ pcie->local_dev = 1;
+
mvebu_pcie_set_local_bus_nr(pcie, bus);
- mvebu_pcie_set_local_dev_nr(pcie, 0);
- pcie->dev = PCI_BDF(bus, 0, 0);
+ mvebu_pcie_set_local_dev_nr(pcie, pcie->local_dev);
pcie->mem.start = (u32)mvebu_pcie_membase;
pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
@@ -336,8 +342,6 @@ static int mvebu_pcie_probe(struct udevice *dev)
writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
- bus++;
-
return 0;
}
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 2b2a6ddb56..7b4c0f02c6 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -31,8 +31,6 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
-obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
-obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
diff --git a/drivers/power/pmic/pmic_max8997.c b/drivers/power/pmic/pmic_max8997.c
deleted file mode 100644
index 1d834ff713..0000000000
--- a/drivers/power/pmic/pmic_max8997.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Lukasz Majewski <l.majewski@samsung.com>
- */
-
-#include <common.h>
-#include <log.h>
-#include <power/pmic.h>
-#include <power/max8997_pmic.h>
-#include <i2c.h>
-#include <errno.h>
-
-unsigned char max8997_reg_ldo(int uV)
-{
- unsigned char ret;
- if (uV <= 800000)
- return 0;
- if (uV >= 3950000)
- return MAX8997_LDO_MAX_VAL;
- ret = (uV - 800000) / 50000;
- if (ret > MAX8997_LDO_MAX_VAL) {
- printf("MAX8997 LDO SETTING ERROR (%duV) -> %u\n", uV, ret);
- ret = MAX8997_LDO_MAX_VAL;
- }
-
- return ret;
-}
-
-static int pmic_charger_state(struct pmic *p, int state, int current)
-{
- unsigned char fc;
- u32 val = 0;
-
- if (pmic_probe(p))
- return -ENODEV;
-
- if (state == PMIC_CHARGER_DISABLE) {
- puts("Disable the charger.\n");
- pmic_reg_read(p, MAX8997_REG_MBCCTRL2, &val);
- val &= ~(MBCHOSTEN | VCHGR_FC);
- pmic_reg_write(p, MAX8997_REG_MBCCTRL2, val);
-
- return -ENOTSUPP;
- }
-
- if (current < CHARGER_MIN_CURRENT || current > CHARGER_MAX_CURRENT) {
- printf("%s: Wrong charge current: %d [mA]\n",
- __func__, current);
- return -EINVAL;
- }
-
- fc = (current - CHARGER_MIN_CURRENT) / CHARGER_CURRENT_RESOLUTION;
- fc = fc & 0xf; /* up to 950 mA */
-
- printf("Enable the charger @ %d [mA]\n", fc * CHARGER_CURRENT_RESOLUTION
- + CHARGER_MIN_CURRENT);
-
- val = fc | MBCICHFCSET;
- pmic_reg_write(p, MAX8997_REG_MBCCTRL4, val);
-
- pmic_reg_read(p, MAX8997_REG_MBCCTRL2, &val);
- val = MBCHOSTEN | VCHGR_FC; /* enable charger & fast charge */
- pmic_reg_write(p, MAX8997_REG_MBCCTRL2, val);
-
- return 0;
-}
-
-static int pmic_charger_bat_present(struct pmic *p)
-{
- u32 val;
-
- if (pmic_probe(p))
- return -ENODEV;
-
- pmic_reg_read(p, MAX8997_REG_STATUS4, &val);
-
- return !(val & DETBAT);
-}
-
-static struct power_chrg power_chrg_pmic_ops = {
- .chrg_bat_present = pmic_charger_bat_present,
- .chrg_state = pmic_charger_state,
-};
-
-int pmic_init(unsigned char bus)
-{
- static const char name[] = "MAX8997_PMIC";
- struct pmic *p = pmic_alloc();
-
- if (!p) {
- printf("%s: POWER allocation error!\n", __func__);
- return -ENOMEM;
- }
-
- debug("Board PMIC init\n");
-
- p->name = name;
- p->interface = PMIC_I2C;
- p->number_of_regs = PMIC_NUM_OF_REGS;
- p->hw.i2c.addr = MAX8997_I2C_ADDR;
- p->hw.i2c.tx_num = 1;
- p->bus = bus;
-
- p->chrg = &power_chrg_pmic_ops;
- return 0;
-}
diff --git a/drivers/power/pmic/pmic_max8998.c b/drivers/power/pmic/pmic_max8998.c
deleted file mode 100644
index f058238c92..0000000000
--- a/drivers/power/pmic/pmic_max8998.c
+++ /dev/null
@@ -1,32 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Samsung Electronics
- * Lukasz Majewski <l.majewski@samsung.com>
- */
-
-#include <common.h>
-#include <power/pmic.h>
-#include <power/max8998_pmic.h>
-#include <errno.h>
-
-int pmic_init(unsigned char bus)
-{
- static const char name[] = "MAX8998_PMIC";
- struct pmic *p = pmic_alloc();
-
- if (!p) {
- printf("%s: POWER allocation error!\n", __func__);
- return -ENOMEM;
- }
-
- puts("Board PMIC init\n");
-
- p->name = name;
- p->interface = PMIC_I2C;
- p->number_of_regs = PMIC_NUM_OF_REGS;
- p->hw.i2c.addr = MAX8998_I2C_ADDR;
- p->hw.i2c.tx_num = 1;
- p->bus = bus;
-
- return 0;
-}
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 79ad0a1b34..24413d14f9 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -722,6 +722,13 @@ config ROCKCHIP_SERIAL
This uses the ns16550 driver, converting the platdata from of-platdata
to the ns16550 format.
+config S5P_SERIAL
+ bool "Support for Samsung S5P UART"
+ depends on ARCH_EXYNOS || ARCH_S5PC1XX
+ default y
+ help
+ Select this to enable Samsung S5P UART support.
+
config SANDBOX_SERIAL
bool "Sandbox UART support"
depends on SANDBOX
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 0c3810f5d5..92bcb30b85 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -41,7 +41,7 @@ obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += serial_mcf.o
obj-$(CONFIG_SYS_NS16550) += ns16550.o
-obj-$(CONFIG_S5P) += serial_s5p.o
+obj-$(CONFIG_S5P_SERIAL) += serial_s5p.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index bb68eb90e9..f3dddbdbd7 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -662,7 +662,10 @@ static int mxc_spi_release_bus(struct udevice *dev)
static int mxc_spi_set_speed(struct udevice *bus, uint speed)
{
- /* Nothing to do */
+ struct mxc_spi_slave *mxcs = dev_get_plat(bus);
+
+ mxcs->max_hz = speed;
+
return 0;
}
diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c
index 012f304595..6c5bad4c2c 100644
--- a/drivers/spi/nxp_fspi.c
+++ b/drivers/spi/nxp_fspi.c
@@ -823,7 +823,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
/* the default frequency, we will change it later if necessary. */
ret = clk_set_rate(&f->clk, 20000000);
- if (ret)
+ if (ret < 0)
return ret;
ret = nxp_fspi_clk_prep_enable(f);
@@ -914,7 +914,7 @@ static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
nxp_fspi_clk_disable_unprep(f);
ret = clk_set_rate(&f->clk, speed);
- if (ret)
+ if (ret < 0)
return ret;
ret = nxp_fspi_clk_prep_enable(f);
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index c5539285af..36e400453e 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -102,11 +102,18 @@
#define BOOT_TARGET_UBIFS(func)
#endif
+#ifdef CONFIG_USB
+#define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_USB(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_MMC1(func) \
BOOT_TARGET_UBIFS(func) \
BOOT_TARGET_MMC0(func) \
BOOT_TARGET_MMC2(func) \
+ BOOT_TARGET_USB(func) \
BOOT_TARGET_PXE(func)
/*
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 4a8e19ee4f..c3e38e499e 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -48,13 +48,13 @@
#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
-#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
-#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
+#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
-#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
-#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
+#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
@@ -75,13 +75,13 @@
#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
-#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
-#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
+#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
-#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
-#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
+#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
+#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
@@ -122,8 +122,8 @@
#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
/* Used for Micron flashes only. */
-#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
-#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
+#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
+#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
/* Status Register bits. */
#define SR_WIP BIT(0) /* Write in progress */
@@ -302,8 +302,8 @@ struct spi_flash {
* @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
* @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
* @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
- * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
* completely locked
+ * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
* @priv: the private data
*/
struct spi_nor {