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-rw-r--r--arch/arm/dts/imx53-m53menlo.dts11
-rw-r--r--arch/arm/dts/imxrt1050.dtsi12
-rw-r--r--arch/arm/include/asm/arch-mx7/imx-regs.h1
-rw-r--r--arch/arm/mach-imx/Kconfig2
-rwxr-xr-xarch/arm/mach-imx/mkimage_fit_atf.sh31
-rw-r--r--arch/arm/mach-imx/mx7/ddr.c22
-rw-r--r--board/freescale/imx8mp_evk/README41
-rw-r--r--board/freescale/imx8mp_evk/spl.c28
-rw-r--r--board/menlo/m53menlo/m53menlo.c14
-rw-r--r--configs/display5_defconfig2
-rw-r--r--configs/display5_factory_defconfig2
-rw-r--r--configs/imx8mm_beacon_defconfig1
-rw-r--r--configs/imx8mm_evk_defconfig1
-rw-r--r--configs/imx8mn_ddr4_evk_defconfig1
-rw-r--r--configs/imx8mp_evk_defconfig4
-rw-r--r--configs/m53menlo_defconfig3
-rw-r--r--configs/verdin-imx8mm_defconfig1
-rw-r--r--drivers/power/pmic/Kconfig7
-rw-r--r--include/configs/display5.h7
-rw-r--r--include/configs/imx8mp_evk.h12
20 files changed, 132 insertions, 71 deletions
diff --git a/arch/arm/dts/imx53-m53menlo.dts b/arch/arm/dts/imx53-m53menlo.dts
index a6805eca9d..3767dcaef4 100644
--- a/arch/arm/dts/imx53-m53menlo.dts
+++ b/arch/arm/dts/imx53-m53menlo.dts
@@ -86,8 +86,19 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
+ phy-handle = <&ethphy0>;
phy-mode = "rmii";
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
};
&i2c1 {
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 7cfe5f5c95..a9281001e5 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -147,12 +147,12 @@
};
lcdif: lcdif@402b8000 {
- compatible = "fsl,imxrt-lcdif";
- reg = <0x402b8000 0x10000>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMXRT1050_CLK_LCDIF>;
- clock-names = "per";
- status = "disabled";
+ compatible = "fsl,imxrt-lcdif";
+ reg = <0x402b8000 0x4000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMXRT1050_CLK_LCDIF>;
+ clock-names = "per";
+ status = "disabled";
};
};
};
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 95238dcaa8..f37419c07f 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -274,6 +274,7 @@ struct src {
#define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1
#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1)
+#define SRC_DDRC_RCR_DDRC_PRST_MASK (1 << 0)
/* GPR0 Bit Fields */
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index bed8cc7e88..6c3fedf665 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -23,7 +23,7 @@ config IMX_RDC
config IMX_BOOTAUX
bool "Support boot auxiliary core"
- depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610
+ depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8M
help
bootaux [addr] to boot auxiliary core.
diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh
index dd1ca5ad3f..fe12b7bb4b 100755
--- a/arch/arm/mach-imx/mkimage_fit_atf.sh
+++ b/arch/arm/mach-imx/mkimage_fit_atf.sh
@@ -62,6 +62,23 @@ cat << __HEADER_EOF
compression = "none";
load = <$BL33_LOAD_ADDR>;
};
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+ cat << __FDT_IMAGE_EOF
+ fdt@$cnt {
+ description = "$(basename $dtname .dtb)";
+ data = /incbin/("$dtname");
+ type = "flat_dt";
+ compression = "none";
+ };
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __HEADER_EOF
atf@1 {
description = "ARM Trusted Firmware";
os = "arm-trusted-firmware";
@@ -88,20 +105,6 @@ cat << __HEADER_EOF
__HEADER_EOF
fi
-cnt=1
-for dtname in $*
-do
- cat << __FDT_IMAGE_EOF
- fdt@$cnt {
- description = "$(basename $dtname .dtb)";
- data = /incbin/("$dtname");
- type = "flat_dt";
- compression = "none";
- };
-__FDT_IMAGE_EOF
-cnt=$((cnt+1))
-done
-
cat << __CONF_HEADER_EOF
};
configurations {
diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c
index 9713835bf2..d1e10a6788 100644
--- a/arch/arm/mach-imx/mx7/ddr.c
+++ b/arch/arm/mach-imx/mx7/ddr.c
@@ -13,6 +13,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx7-ddr.h>
#include <common.h>
+#include <linux/delay.h>
/*
* Routine: mx7_dram_cfg
@@ -37,8 +38,23 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
int i;
- /* Assert DDR Controller preset and DDR PHY reset */
- writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr);
+ /*
+ * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
+ * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 ,
+ * aresetn_n = 0, presetn = 0. That means reset everything.
+ */
+ writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK,
+ &src_regs->ddrc_rcr);
+
+ /*
+ * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown).
+ * If we assume this is 30 cycles at 100 MHz (about the rate of a
+ * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty.
+ */
+ udelay(10);
+
+ /* De-assert DDR Controller 'preset' and DDR PHY reset */
+ clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK);
/* DDR controller configuration */
writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
@@ -71,7 +87,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
- /* De-assert DDR Controller preset and DDR PHY reset */
+ /* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */
clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
/* PHY configuration */
diff --git a/board/freescale/imx8mp_evk/README b/board/freescale/imx8mp_evk/README
new file mode 100644
index 0000000000..7dd3a9352a
--- /dev/null
+++ b/board/freescale/imx8mp_evk/README
@@ -0,0 +1,41 @@
+U-Boot for the NXP i.MX8MP EVK board
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get the firmware-imx package
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+Note: $(srctree) is the U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.3_2.0.0
+$ make PLAT=imx8mp bl31
+$ sudo cp build/imx8mp/release/bl31.bin $(srctree)
+
+Get the ddr firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin
+$ chmod +x firmware-imx-8.7.bin
+$ ./firmware-imx-8.7
+$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
+$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
+$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
+$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
+
+Build U-Boot
+============
+$ export CROSS_COMPILE=aarch64-poky-linux-
+$ make imx8mp_evk_defconfig
+$ export ATF_LOAD_ADDR=0x960000
+$ make flash.bin
+
+Burn the flash.bin to the MicroSD card at offset 32KB
+$sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32; sync
+
+Boot
+====
+Set Boot switch to SD boot
+Use /dev/ttyUSB2 for U-Boot console
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index cd5b32c3f8..3b3a854e29 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -29,11 +29,6 @@
#include <mmc.h>
#include <asm/arch/ddr.h>
-#include <dm/uclass.h>
-#include <dm/device.h>
-#include <dm/uclass-internal.h>
-#include <dm/device-internal.h>
-
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
@@ -48,16 +43,7 @@ void spl_dram_init(void)
void spl_board_init(void)
{
- struct udevice *dev;
- int ret;
-
puts("Normal Boot\n");
-
- ret = uclass_get_device_by_name(UCLASS_CLK,
- "clock-controller@30380000",
- &dev);
- if (ret < 0)
- printf("Failed to find clock node. Check device tree\n");
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
@@ -118,6 +104,7 @@ int board_fit_config_name_match(const char *name)
}
#endif
+/* Do not use BSS area in this phase */
void board_init_f(ulong dummy)
{
int ret;
@@ -128,19 +115,14 @@ void board_init_f(ulong dummy)
board_early_init_f();
- timer_init();
-
- preloader_console_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- ret = spl_init();
+ ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
+ preloader_console_init();
+
enable_tzc380();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
@@ -149,6 +131,4 @@ void board_init_f(ulong dummy)
/* DDR initialization */
spl_dram_init();
-
- board_init_r(NULL, 0);
}
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
index 58a564ac31..d4288a2c57 100644
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -353,24 +353,28 @@ int board_late_init(void)
ret = splash_screen_prepare();
if (ret < 0)
- return ret;
+ goto splasherr;
len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
(uchar *)addr, &len);
if (ret) {
printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
- free(dst);
- return ret;
+ goto splasherr;
}
ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
if (ret)
- return ret;
+ goto splasherr;
ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
if (ret)
- return ret;
+ goto splasherr;
+
+ return 0;
+
+splasherr:
+ free(dst);
#endif
return 0;
}
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 78e4627bda..700bdcbd17 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -71,7 +71,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),4m(swu-kernel),16m(swu-initramfs),1m(factory),-(reserved)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),6m(swu-kernel),20m(swu-initramfs),3840k(reserved),1m(factory)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index d453073ddb..39f31687b4 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=02008000.spi.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),4m(swu-kernel),16m(swu-initramfs),1m(factory),-(reserved)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1),64k(env2),6m(swu-kernel),20m(swu-initramfs),3840k(reserved),1m(factory)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_CONTROL=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index b935d72360..a518963f48 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -100,5 +100,4 @@ CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
-# CONFIG_WATCHDOG is not set
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 9a72f46f27..e7abf6b07c 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -85,5 +85,4 @@ CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
-# CONFIG_WATCHDOG is not set
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index bc6014d73a..7fd443f37e 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -79,5 +79,4 @@ CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
-# CONFIG_WATCHDOG is not set
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index 44b2935f69..17452b6214 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -4,7 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
@@ -82,5 +83,4 @@ CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
-# CONFIG_WATCHDOG is not set
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index a65c21a139..5289899601 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -75,6 +75,9 @@ CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index c68b299a95..f5b6e03251 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -99,5 +99,4 @@ CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
-# CONFIG_WATCHDOG is not set
CONFIG_IMX_WATCHDOG=y
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index ef8bf49d49..a62aa38054 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -105,6 +105,13 @@ config DM_PMIC_PFUZE100
This config enables implementation of driver-model pmic uclass features
for PMIC PFUZE100. The driver implements read/write operations.
+config SPL_DM_PMIC_PFUZE100
+ bool "Enable Driver Model for PMIC PFUZE100 in SPL"
+ depends on DM_PMIC
+ ---help---
+ This config enables implementation of driver-model pmic uclass features
+ for PMIC PFUZE100 in SPL. The driver implements read/write operations.
+
config DM_PMIC_MAX77686
bool "Enable Driver Model for PMIC MAX77686"
depends on DM_PMIC
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 2e5dbfedc8..3348ecc7c7 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -28,9 +28,10 @@
* 0x020000 - 0x120000 : SPI.u-boot (1MiB)
* 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB)
* 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB)
- * 0x140000 - 0x540000 : SPI.swupdate-kernel-FIT (4MiB)
- * 0x540000 - 0x1540000 : SPI.swupdate-initramfs (16MiB)
- * 0x1540000 - 0x1640000 : SPI.factory (1MiB)
+ * 0x140000 - 0x740000 : SPI.swupdate-kernel-FIT (6MiB)
+ * 0x740000 - 0x1B40000 : SPI.swupdate-initramfs (20MiB)
+ * 0x1B40000 - 0x1F00000 : SPI.reserved (3840KiB)
+ * 0x1F00000 - 0x2000000 : SPI.factory (1MiB)
*/
/* SPI Flash Configs */
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index b346154fb3..7f38f21c09 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -24,16 +24,14 @@
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
-#define CONFIG_SPL_STACK 0x990000
-#define CONFIG_SPL_BSS_START_ADDR 0x0095e000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
-#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
-#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
+#define CONFIG_SPL_STACK 0x960000
+#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
+#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_MALLOC_F_ADDR 0x940000
-
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#undef CONFIG_DM_MMC
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