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-rw-r--r--arch/x86/cpu/broadwell/cpu.c5
-rw-r--r--arch/x86/cpu/broadwell/cpu_full.c7
-rw-r--r--arch/x86/lib/spl.c5
3 files changed, 12 insertions, 5 deletions
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index bb7c361408..bba8cd1e94 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -67,7 +67,12 @@ int arch_cpu_init(void)
{
post_code(POST_CPU_INIT);
+#ifdef CONFIG_TPL
+ /* Do a mini-init if TPL has already done the full init */
+ return x86_cpu_reinit_f();
+#else
return x86_cpu_init_f();
+#endif
}
int checkcpu(void)
diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c
index d8b8482658..bd0b2037fa 100644
--- a/arch/x86/cpu/broadwell/cpu_full.c
+++ b/arch/x86/cpu/broadwell/cpu_full.c
@@ -81,6 +81,13 @@ static const u8 power_limit_time_msr_to_sec[] = {
[0x11] = 128,
};
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+int arch_cpu_init(void)
+{
+ return 0;
+}
+#endif
+
/*
* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
* the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index a739491303..2baac91383 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -40,12 +40,7 @@ static int x86_spl_init(void)
debug("%s: spl_init() failed\n", __func__);
return ret;
}
-#ifdef CONFIG_TPL
- /* Do a mini-init if TPL has already done the full init */
- ret = x86_cpu_reinit_f();
-#else
ret = arch_cpu_init();
-#endif
if (ret) {
debug("%s: arch_cpu_init() failed\n", __func__);
return ret;