diff options
23 files changed, 37 insertions, 175 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index c3f8ad8506..52473ade7a 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -164,7 +164,7 @@ int serdes_phy_config(void); int ddr3_init(void); /* Auto Voltage Scaling */ -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) +#if defined(CONFIG_ARMADA_38X) void mv_avs_init(void); void mv_rtc_config(void); #else diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index ae2a361104..3b41c7d49b 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -14,11 +14,6 @@ #include "sys_env_lib.h" #include "ctrl_pex.h" -#if defined(CONFIG_ARMADA_38X) -#elif defined(CONFIG_ARMADA_39X) -#else -#error "No device is defined" -#endif /* @@ -79,11 +74,6 @@ u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES] = { { NA, 0x6, NA, NA, 0x4, NA, NA }, /* USB3_HOST0 */ { NA, NA, NA, 0x5, NA, 0x4, NA }, /* USB3_HOST1 */ { NA, NA, NA, 0x6, 0x5, 0x5, NA }, /* USB3_DEVICE */ -#ifdef CONFIG_ARMADA_39X - { NA, NA, 0x5, NA, 0x8, NA, 0x2 }, /* SGMII3 */ - { NA, NA, NA, 0x8, 0x9, 0x8, 0x4 }, /* XAUI */ - { NA, NA, NA, NA, NA, 0x8, 0x4 }, /* RXAUI */ -#endif { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, NA } /* DEFAULT_SERDES */ }; @@ -798,11 +788,9 @@ struct op_params serdes_power_down_params[] = { */ u8 hws_ctrl_serdes_rev_get(void) { -#ifdef CONFIG_ARMADA_38X /* for A38x-Z1 */ if (sys_env_device_rev_get() == MV_88F68XX_Z1_ID) return MV_SERDES_REV_1_2; -#endif /* for A39x-Z1, A38x-A0 */ return MV_SERDES_REV_2_1; @@ -1351,9 +1339,6 @@ enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type, case SGMII0: case SGMII1: case SGMII2: -#ifdef CONFIG_ARMADA_39X - case SGMII3: -#endif if (baud_rate == SERDES_SPEED_1_25_GBPS) seq_id = SGMII_1_25_SPEED_CONFIG_SEQ; else if (baud_rate == SERDES_SPEED_3_125_GBPS) @@ -1362,14 +1347,6 @@ enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type, case QSGMII: seq_id = QSGMII_5_SPEED_CONFIG_SEQ; break; -#ifdef CONFIG_ARMADA_39X - case XAUI: - seq_id = XAUI_3_125_SPEED_CONFIG_SEQ; - break; - case RXAUI: - seq_id = RXAUI_6_25_SPEED_CONFIG_SEQ; - break; -#endif default: return SERDES_LAST_SEQ; } @@ -2054,13 +2031,6 @@ int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type, (serdes_num, PEX_CONFIG_REF_CLOCK_100MHZ_SEQ)); return MV_OK; -#ifdef CONFIG_ARMADA_39X - case REF_CLOCK_40MHZ: - CHECK_STATUS(mv_seq_exec - (serdes_num, - PEX_CONFIG_REF_CLOCK_40MHZ_SEQ)); - return MV_OK; -#endif default: printf ("%s: Error: ref_clock %d for SerDes lane #%d, type %d is not supported\n", @@ -2104,22 +2074,6 @@ int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type, return MV_BAD_PARAM; } break; -#ifdef CONFIG_ARMADA_39X - case SGMII3: - case XAUI: - case RXAUI: - if (ref_clock == REF_CLOCK_25MHZ) { - data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1; - } else if (ref_clock == REF_CLOCK_40MHZ) { - data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL; - } else { - printf - ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n", - serdes_type); - return MV_BAD_PARAM; - } - break; -#endif default: DEBUG_INIT_S("hws_ref_clock_set: not supported serdes type\n"); return MV_BAD_PARAM; diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index 3c4c7e01a1..950680a581 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -12,7 +12,6 @@ #include "seq_exec.h" #include "sys_env_lib.h" -#ifdef CONFIG_ARMADA_38X enum unit_id sys_env_soc_unit_nums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = { /* 6820 6810 6811 6828 */ /* PEX_UNIT_ID */ { 4, 3, 3, 4}, @@ -24,19 +23,6 @@ enum unit_id sys_env_soc_unit_nums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = { /* XAUI_UNIT_ID */ { 0, 0, 0, 0}, /* RXAUI_UNIT_ID */ { 0, 0, 0, 0} }; -#else /* if (CONFIG_ARMADA_39X) */ -enum unit_id sys_env_soc_unit_nums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = { -/* 6920 6928 */ -/* PEX_UNIT_ID */ { 4, 4}, -/* ETH_GIG_UNIT_ID */ { 3, 4}, -/* USB3H_UNIT_ID */ { 1, 2}, -/* USB3D_UNIT_ID */ { 0, 1}, -/* SATA_UNIT_ID */ { 0, 4}, -/* QSGMII_UNIT_ID */ { 0, 1}, -/* XAUI_UNIT_ID */ { 1, 1}, -/* RXAUI_UNIT_ID */ { 1, 1} -}; -#endif u32 g_dev_id = -1; @@ -202,11 +188,7 @@ u16 sys_env_model_get(void) return ctrl_id; default: /* Device ID Default for A38x: 6820 , for A39x: 6920 */ - #ifdef CONFIG_ARMADA_38X default_ctrl_id = MV_6820_DEV_ID; - #else - default_ctrl_id = MV_6920_DEV_ID; - #endif printf("%s: Error retrieving device ID (%x), using default ID = %x\n", __func__, ctrl_id, default_ctrl_id); return default_ctrl_id; @@ -261,9 +243,6 @@ void mv_rtc_config(void) { u32 i, val; - if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X))) - return; - /* Activate pipe0 for read/write transaction, and set XBAR client number #1 */ val = 0x1 << DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS | 0x1 << DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS; @@ -278,9 +257,6 @@ void mv_avs_init(void) { u32 sar_freq; - if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X))) - return; - reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE); reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE); diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 17cd811331..118bf56602 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -118,12 +118,8 @@ /* TWSI addresses */ /* starting from A38x A0, i2c address of EEPROM is 0x57 */ -#ifdef CONFIG_ARMADA_39X -#define EEPROM_I2C_ADDR 0x50 -#else #define EEPROM_I2C_ADDR (sys_env_device_rev_get() == \ MV_88F68XX_Z1_ID ? 0x50 : 0x57) -#endif #define RD_GET_MODE_ADDR 0x4c #define DB_GET_MODE_SLM1363_ADDR 0x25 #define DB_GET_MODE_SLM1364_ADDR 0x24 @@ -216,7 +212,6 @@ #define A39X_MV_MARVELL_BOARD_NUM (A39X_MV_MAX_MARVELL_BOARD_ID - \ A39X_MARVELL_BOARD_ID_BASE) -#ifdef CONFIG_ARMADA_38X #define CUTOMER_BOARD_ID_BASE A38X_CUSTOMER_BOARD_ID_BASE #define CUSTOMER_BOARD_ID0 A38X_CUSTOMER_BOARD_ID0 #define CUSTOMER_BOARD_ID1 A38X_CUSTOMER_BOARD_ID1 @@ -227,18 +222,6 @@ #define MV_MARVELL_BOARD_NUM A38X_MV_MARVELL_BOARD_NUM #define MV_DEFAULT_BOARD_ID DB_68XX_ID #define MV_DEFAULT_DEVICE_ID MV_6811 -#elif defined(CONFIG_ARMADA_39X) -#define CUTOMER_BOARD_ID_BASE A39X_CUSTOMER_BOARD_ID_BASE -#define CUSTOMER_BOARD_ID0 A39X_CUSTOMER_BOARD_ID0 -#define CUSTOMER_BOARD_ID1 A39X_CUSTOMER_BOARD_ID1 -#define MV_MAX_CUSTOMER_BOARD_ID A39X_MV_MAX_CUSTOMER_BOARD_ID -#define MV_CUSTOMER_BOARD_NUM A39X_MV_CUSTOMER_BOARD_NUM -#define MARVELL_BOARD_ID_BASE A39X_MARVELL_BOARD_ID_BASE -#define MV_MAX_MARVELL_BOARD_ID A39X_MV_MAX_MARVELL_BOARD_ID -#define MV_MARVELL_BOARD_NUM A39X_MV_MARVELL_BOARD_NUM -#define MV_DEFAULT_BOARD_ID A39X_DB_69XX_ID -#define MV_DEFAULT_DEVICE_ID MV_6920 -#endif #define MV_INVALID_BOARD_ID 0xffffffff @@ -295,11 +278,7 @@ enum { #define MV_6920_INDEX 0 #define MV_6928_INDEX 1 -#ifdef CONFIG_ARMADA_38X #define MAX_DEV_ID_NUM 4 -#else -#define MAX_DEV_ID_NUM 2 -#endif #define MV_6820_INDEX 0 #define MV_6810_INDEX 1 @@ -340,21 +319,13 @@ enum suspend_wakeup_status { * If suspend to RAM is not supported set '-1' */ #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT -#ifdef CONFIG_ARMADA_38X #define MV_BOARD_WAKEUP_GPIO_INFO { \ {A38X_CUSTOMER_BOARD_ID0, -1 }, \ {A38X_CUSTOMER_BOARD_ID0, -1 }, \ }; -#else -#define MV_BOARD_WAKEUP_GPIO_INFO { \ - {A39X_CUSTOMER_BOARD_ID0, -1 }, \ - {A39X_CUSTOMER_BOARD_ID0, -1 }, \ -}; -#endif /* CONFIG_ARMADA_38X */ #else -#ifdef CONFIG_ARMADA_38X #define MV_BOARD_WAKEUP_GPIO_INFO { \ {RD_NAS_68XX_ID, -2 }, \ {DB_68XX_ID, -1 }, \ @@ -364,12 +335,6 @@ enum suspend_wakeup_status { {DB_BP_6821_ID, -2 }, \ {DB_AMC_6820_ID, -2 }, \ }; -#else -#define MV_BOARD_WAKEUP_GPIO_INFO { \ - {A39X_RD_69XX_ID, -1 }, \ - {A39X_DB_69XX_ID, -1 }, \ -}; -#endif /* CONFIG_ARMADA_38X */ #endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ u32 mv_board_tclk_get(void); diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 4956199ccd..c791f98dfe 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -32,12 +32,14 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SQUASHFS=y +CONFIG_CMD_FS_UUID=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -65,6 +67,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MVNETA=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_AARDVARK=y diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c index 22e0cc4d91..f5fc964d6f 100644 --- a/drivers/ddr/marvell/a38x/ddr3_debug.c +++ b/drivers/ddr/marvell/a38x/ddr3_debug.c @@ -6,7 +6,6 @@ #include "ddr3_init.h" #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" -#include <log.h> u8 is_reg_dump = 0; u8 debug_pbs = DEBUG_LEVEL_ERROR; diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c index 7488770268..f878b4512b 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.c +++ b/drivers/ddr/marvell/a38x/ddr3_init.c @@ -77,9 +77,6 @@ int ddr3_init(void) return status; } -#if defined(CONFIG_PHY_STATIC_PRINT) - mv_ddr_phy_static_print(); -#endif /* Post MC/PHY initializations */ mv_ddr_post_training_soc_config(ddr_type); diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 2b3af23202..2512b58cb7 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -7,8 +7,6 @@ #include "mv_ddr_common.h" #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" -#include <log.h> -#include <linux/delay.h> #define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask]) #define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num]) @@ -207,7 +205,6 @@ static int ddr3_tip_pad_inv(void) if (tm->interface_params[0].as_bus_params[sphy]. is_ck_swap == 1 && sphy == 0) { /* TODO: move this code to per platform one */ -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) /* clock swap for both cs0 and cs1 */ data = (INVERT_PAD << INV_PAD2_OFFS | INVERT_PAD << INV_PAD6_OFFS | @@ -219,9 +216,6 @@ static int ddr3_tip_pad_inv(void) DDR_PHY_CONTROL, PHY_CTRL_PHY_REG, data, data); -#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */ -#pragma message "unknown platform to configure ddr clock swap" -#endif } } @@ -2014,9 +2008,7 @@ int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2) static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) { /* TODO: enable this functionality for other platforms */ -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) struct init_cntr_param init_cntr_prm; -#endif int ret = MV_OK; int adll_bypass_flag = 0; u32 if_id; @@ -2050,7 +2042,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) } /* TODO: enable this functionality for other platforms */ -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) if (is_adll_calib_before_init != 0) { DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("with adll calib before init\n")); @@ -2081,7 +2072,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) return MV_FAIL; } } -#endif ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq); if (ret != MV_OK) { @@ -2905,3 +2895,4 @@ unsigned int mv_ddr_misl_phy_odt_n_get(void) return odt_n; } + diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c index 5fd9a052fa..102f9bd633 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c @@ -6,8 +6,6 @@ #include "ddr3_init.h" #include "mv_ddr_regs.h" #include "ddr_training_ip_db.h" -#include <image.h> -#include <linux/delay.h> #define PATTERN_1 0x55555555 #define PATTERN_2 0xaaaaaaaa @@ -614,9 +612,9 @@ int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type, MASK_ALL_BITS)); } - CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, - ODPG_DATA_BUFFER_OFFS_REG, - load_addr, MASK_ALL_BITS)); + CHECK_STATUS(ddr3_tip_if_write + (dev_num, access_type, if_id, + ODPG_DATA_BUFFER_OFFS_REG, load_addr, MASK_ALL_BITS)); return MV_OK; } diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c index dadb06b318..6523281f2b 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c @@ -7,7 +7,6 @@ #include "mv_ddr_training_db.h" #include "ddr_training_ip_db.h" #include "mv_ddr_regs.h" -#include <linux/delay.h> #define WL_ITERATION_NUM 10 @@ -916,10 +915,8 @@ int ddr3_tip_dynamic_write_leveling(u32 dev_num, int phase_remove) DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("training done failed\n")); } else { /* check for training pass */ reg_data = data_read[0]; -#if defined(CONFIG_ARMADA_38X) /* JIRA #1498 for 16 bit with ECC */ if (tm->bus_act_mask == 0xb) /* set to data to 0 to skip the check */ reg_data = 0; -#endif if (reg_data != PASS) DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("training result failed\n")); diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h index ac9250f74e..7357311965 100644 --- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h +++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h @@ -13,9 +13,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) #define INTER_REGS_BASE SOC_REGS_PHY_BASE -#endif /* * MV_DEBUG_INIT need to be defines, otherwise the output of the diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 0d1df189e8..faafc86ea2 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -8,7 +8,6 @@ #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" #include "mv_ddr_sys_env_lib.h" -#include <linux/delay.h> #define DDR_INTERFACES_NUM 1 #define DDR_INTERFACE_OCTETS_NUM 5 @@ -560,11 +559,7 @@ static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum mv_ddr_freq *freq) static int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr) { -#if defined(CONFIG_ARMADA_39X) - info_ptr->device_id = 0x6900; -#else info_ptr->device_id = 0x6800; -#endif info_ptr->ck_delay = ck_delay; return MV_OK; @@ -667,11 +662,7 @@ static int mv_ddr_sw_db_init(u32 dev_num, u32 board_id) ddr3_tip_dev_attr_set(dev_num, MV_ATTR_TIP_REV, MV_TIP_REV_4); ddr3_tip_dev_attr_set(dev_num, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_POSITIVE); ddr3_tip_dev_attr_set(dev_num, MV_ATTR_OCTET_PER_INTERFACE, DDR_INTERFACE_OCTETS_NUM); -#ifdef CONFIG_ARMADA_39X - ddr3_tip_dev_attr_set(dev_num, MV_ATTR_INTERLEAVE_WA, 1); -#else ddr3_tip_dev_attr_set(dev_num, MV_ATTR_INTERLEAVE_WA, 0); -#endif ca_delay = 0; delay_enable = 1; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h index 281d4c2301..44998847c2 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h @@ -6,6 +6,8 @@ #ifndef _MV_DDR_PLAT_H #define _MV_DDR_PLAT_H +#include <linux/delay.h> + #define MAX_DEVICE_NUM 1 #define MAX_INTERFACE_NUM 1 #define MAX_BUS_NUM 5 diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h index b4bfef3103..6043f11b28 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h @@ -40,7 +40,10 @@ */ union mv_ddr_spd_data { unsigned char all_bytes[MV_DDR_SPD_DATA_BLOCK0_SIZE + - MV_DDR_SPD_DATA_BLOCK1M_SIZE]; + MV_DDR_SPD_DATA_BLOCK1M_SIZE + + MV_DDR_SPD_DATA_BLOCK1H_SIZE + + MV_DDR_SPD_DATA_BLOCK2E_SIZE + + MV_DDR_SPD_DATA_BLOCK2M_SIZE]; struct { /* block 0 */ union { /* num of bytes used/num of bytes in spd device/crc coverage */ @@ -271,6 +274,9 @@ union mv_ddr_spd_data { } bit_fields; } byte_131; unsigned char bytes_132_191[60]; /* reserved; all 0s */ + unsigned char bytes_192_255[MV_DDR_SPD_DATA_BLOCK1H_SIZE]; + unsigned char bytes_256_319[MV_DDR_SPD_DATA_BLOCK2E_SIZE]; + unsigned char bytes_320_383[MV_DDR_SPD_DATA_BLOCK2M_SIZE]; } byte_fields; }; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h b/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h index dc6977c334..10b0d45b35 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h @@ -78,22 +78,7 @@ enum suspend_wakeup_status { * set '-2' * If suspend to RAM is not supported set '-1' */ -#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT -#ifdef CONFIG_ARMADA_38X -#define MV_BOARD_WAKEUP_GPIO_INFO { \ - {A38X_CUSTOMER_BOARD_ID0, -1 }, \ - {A38X_CUSTOMER_BOARD_ID0, -1 }, \ -}; -#else -#define MV_BOARD_WAKEUP_GPIO_INFO { \ - {A39X_CUSTOMER_BOARD_ID0, -1 }, \ - {A39X_CUSTOMER_BOARD_ID0, -1 }, \ -}; -#endif /* CONFIG_ARMADA_38X */ - -#else -#ifdef CONFIG_ARMADA_38X #define MV_BOARD_WAKEUP_GPIO_INFO { \ {RD_NAS_68XX_ID, -2 }, \ {DB_68XX_ID, -1 }, \ @@ -103,13 +88,6 @@ enum suspend_wakeup_status { {DB_BP_6821_ID, -2 }, \ {DB_AMC_6820_ID, -2 }, \ }; -#else -#define MV_BOARD_WAKEUP_GPIO_INFO { \ - {A39X_RD_69XX_ID, -1 }, \ - {A39X_DB_69XX_ID, -1 }, \ -}; -#endif /* CONFIG_ARMADA_38X */ -#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ enum suspend_wakeup_status mv_ddr_sys_env_suspend_wakeup_check(void); u32 mv_ddr_sys_env_get_cs_ena_from_reg(void); diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c index 98fb39eaf0..7bc6268293 100644 --- a/drivers/ddr/marvell/a38x/xor.c +++ b/drivers/ddr/marvell/a38x/xor.c @@ -347,10 +347,8 @@ void ddr3_new_tip_ecc_scrub(void) for (cs_c = 0; cs_c < max_cs; cs_c++) cs_ena |= 1 << cs_c; -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) /* all chip-selects are of same size */ ddr3_calc_mem_cs_size(0, &cs_mem_size_mb); -#endif cs_mem_size = cs_mem_size_mb * _1M; mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); total_mem_size = max_cs * cs_mem_size; diff --git a/drivers/ddr/marvell/axp/ddr3_dfs.c b/drivers/ddr/marvell/axp/ddr3_dfs.c index b58c0fe01e..2a4596680b 100644 --- a/drivers/ddr/marvell/axp/ddr3_dfs.c +++ b/drivers/ddr/marvell/axp/ddr3_dfs.c @@ -42,8 +42,8 @@ extern u8 div_ratio[CLK_VCO][CLK_DDR]; extern void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps); #else extern u16 odt_dynamic[ODT_OPT][MAX_CS]; -extern u8 div_ratio1to1[CLK_CPU][CLK_DDR]; -extern u8 div_ratio2to1[CLK_CPU][CLK_DDR]; +extern u8 div_ratio1to1[CLK_VCO][CLK_DDR]; +extern u8 div_ratio2to1[CLK_VCO][CLK_DDR]; #endif extern u16 odt_static[ODT_OPT][MAX_CS]; diff --git a/drivers/ddr/marvell/axp/ddr3_sdram.c b/drivers/ddr/marvell/axp/ddr3_sdram.c index 3a266c6de4..0b150b20f3 100644 --- a/drivers/ddr/marvell/axp/ddr3_sdram.c +++ b/drivers/ddr/marvell/axp/ddr3_sdram.c @@ -21,7 +21,7 @@ extern u32 pbs_pattern_32b[2][LEN_PBS_PATTERN]; #if defined(MV88F78X60) extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN]; #endif -extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM]; +extern u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM]; #if defined(MV88F78X60) || defined(MV88F672X) /* PBS locked dq (per pup) */ diff --git a/drivers/ddr/marvell/axp/xor.c b/drivers/ddr/marvell/axp/xor.c index 17bfe6a7bf..76aea96682 100644 --- a/drivers/ddr/marvell/axp/xor.c +++ b/drivers/ddr/marvell/axp/xor.c @@ -152,8 +152,8 @@ static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl) return MV_OK; } -int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high, - u32 init_val_low) +int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long block_size, + u32 init_val_high, u32 init_val_low) { u32 tmp; diff --git a/drivers/ddr/marvell/axp/xor.h b/drivers/ddr/marvell/axp/xor.h index 97d1056432..a7c6ae840c 100644 --- a/drivers/ddr/marvell/axp/xor.h +++ b/drivers/ddr/marvell/axp/xor.h @@ -64,7 +64,7 @@ int mv_xor_state_get(u32 chan); void mv_sys_xor_init(MV_DRAM_INFO *dram_info); void mv_sys_xor_finish(void); int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr); -int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high, - u32 init_val_low); +int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long block_size, + u32 init_val_high, u32 init_val_low); #endif /* __XOR_H */ diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index b4e1b60240..3b9309f52c 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -105,6 +105,7 @@ #define LTSSM_SHIFT 24 #define LTSSM_MASK 0x3f #define LTSSM_L0 0x10 +#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -529,6 +530,15 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) reg |= (IS_RC_MSK << IS_RC_SHIFT); advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* + * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. + * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor + * id in high 16 bits. Updating this register changes readback value of + * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround + * for erratum 4.1: "The value of device and vendor ID is incorrect". + */ + advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG); + /* Set Advanced Error Capabilities and Control PF0 register */ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e793cd1169..819e362e5b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -43,7 +43,6 @@ CONFIG_ARC_MMU_VER CONFIG_ARMADA100 CONFIG_ARMADA100_FEC CONFIG_ARMADA168 -CONFIG_ARMADA_39X CONFIG_ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_MAX_SIZE CONFIG_ARMV7_SECURE_RESERVE_SIZE diff --git a/tools/Makefile b/tools/Makefile index 2d550432ba..62de7e6fe0 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -150,12 +150,12 @@ ifdef CONFIG_SYS_U_BOOT_OFFS HOSTCFLAGS_kwbimage.o += -DCONFIG_SYS_U_BOOT_OFFS=$(CONFIG_SYS_U_BOOT_OFFS) endif -ifneq ($(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),) +ifneq ($(CONFIG_ARMADA_38X),) HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE endif # MXSImage needs LibSSL -ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),) +ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),) HOSTCFLAGS_kwbimage.o += \ $(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "") HOSTLDLIBS_mkimage += \ |