diff options
45 files changed, 1576 insertions, 56 deletions
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 78383f0e89..4214ab5dc6 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -35,6 +35,10 @@ choice prompt "MX6 board select" optional +config TARGET_ADVANTECH_DMS_BA16 + bool "Advantech dms-ba16" + select MX6Q + config TARGET_ARISTAINETOS bool "aristainetos" @@ -200,6 +204,7 @@ config SYS_SOC default "mx6" source "board/ge/bx50v3/Kconfig" +source "board/advantech/dms-ba16/Kconfig" source "board/aristainetos/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/barco/platinum/Kconfig" diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index f151eec545..7beb7eabf7 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -1166,8 +1166,7 @@ void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo, mmdc0->mpzqhwctrl = val; /* Step 12: Configure and activate periodic refresh */ - mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */ - (3 << 11); /* REFR: Refresh Rate - 4 refreshes */ + mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x00000000; @@ -1472,8 +1471,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, MMDC1(mpzqhwctrl, val); /* Step 12: Configure and activate periodic refresh */ - mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */ - (7 << 11); /* REFR: Refresh Rate - 8 refreshes */ + mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x00000000; diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 12c30d274f..99224091ba 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -408,6 +408,8 @@ struct mx6_ddr_sysinfo { u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */ + u8 refsel; /* REF_SEL field of register MDREF */ + u8 refr; /* REFR field of register MDREF */ }; /* diff --git a/board/advantech/dms-ba16/Kconfig b/board/advantech/dms-ba16/Kconfig new file mode 100644 index 0000000000..040eb866b5 --- /dev/null +++ b/board/advantech/dms-ba16/Kconfig @@ -0,0 +1,31 @@ +if TARGET_ADVANTECH_DMS_BA16 + +choice + prompt "DDR Size" + default SYS_DDR_2G + +config SYS_DDR_1G + bool "1GiB" + +config SYS_DDR_2G + bool "2GiB" + +endchoice + +config IMX_CONFIG + default "board/advantech/dms-ba16/dms-ba16_2g.cfg" if SYS_DDR_2G + default "board/advantech/dms-ba16/dms-ba16_1g.cfg" if SYS_DDR_1G + +config SYS_BOARD + default "dms-ba16" + +config SYS_VENDOR + default "advantech" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "advantech_dms-ba16" + +endif diff --git a/board/advantech/dms-ba16/MAINTAINERS b/board/advantech/dms-ba16/MAINTAINERS new file mode 100644 index 0000000000..e8ea3dd7b3 --- /dev/null +++ b/board/advantech/dms-ba16/MAINTAINERS @@ -0,0 +1,8 @@ +ADVANTECH_DMS-BA16 BOARD +M: Akshay Bhat <akshaybhat@timesys.com> +M: Ken Lin <Ken.Lin@advantech.com.tw> +S: Maintained +F: board/advantech/dms-ba16/ +F: include/configs/advantech_dms-ba16.h +F: configs/dms-ba16_defconfig +F: configs/dms-ba16-1g_defconfig diff --git a/board/advantech/dms-ba16/Makefile b/board/advantech/dms-ba16/Makefile new file mode 100644 index 0000000000..ec9aaa8508 --- /dev/null +++ b/board/advantech/dms-ba16/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2016 Timesys Corporation +# Copyright 2016 Advantech Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := dms-ba16.o diff --git a/board/advantech/dms-ba16/clocks.cfg b/board/advantech/dms-ba16/clocks.cfg new file mode 100644 index 0000000000..abc769c4e5 --- /dev/null +++ b/board/advantech/dms-ba16/clocks.cfg @@ -0,0 +1,25 @@ +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en 1 --> CKO1 enabled + * cko1_div 111 --> divide by 8 + * cko1_sel 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/advantech/dms-ba16/ddr-setup.cfg b/board/advantech/dms-ba16/ddr-setup.cfg new file mode 100644 index 0000000000..4c43e648f7 --- /dev/null +++ b/board/advantech/dms-ba16/ddr-setup.cfg @@ -0,0 +1,39 @@ +/* DDR IO */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c new file mode 100644 index 0000000000..f0f1976597 --- /dev/null +++ b/board/advantech/dms-ba16/dms-ba16.c @@ -0,0 +1,570 @@ +/* + * Copyright 2016 Timesys Corporation + * Copyright 2016 Advantech Corporation + * Copyright 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <pwm.h> +DECLARE_GLOBAL_DATA_PTR; + +#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart3_pads[] = { + MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + /* AR8033 PHY Reset */ + MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset AR8033 PHY */ + gpio_direction_output(IMX_GPIO_NR(1, 28), 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 28), 1); +} + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +static struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; +} + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} +#endif + +static iomux_v3_cfg_t const pcie_pads[] = { + MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = 1; /* eMMC is always present */ + break; + case USDHC4_BASE_ADDR: + ret = !gpio_get_value(USDHC4_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + int i; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_direction_input(USDHC4_CD_GPIO); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers\n" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +static int mx6_rgmii_rework(struct phy_device *phydev) +{ + /* set device address 0x7 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + /* offset 0x8016: CLK_25M Clock Select */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + /* enable register write, no post increment, address 0x7 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + /* set to 125 MHz from local PLL source */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18); + /* set debug port address: SerDes Test and System Mode Control */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + /* enable rgmii tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +#if defined(CONFIG_VIDEO_IPUV3) +static iomux_v3_cfg_t const backlight_pads[] = { + /* Power for LVDS Display */ + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define LVDS_POWER_GP IMX_GPIO_NR(3, 22) + /* Backlight enable for LVDS display */ + MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0) + /* backlight PWM brightness control */ + MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +int board_cfb_skip(void) +{ + gpio_direction_output(LVDS_POWER_GP, 1); + + return 0; +} + +static int detect_baseboard(struct display_info_t const *dev) +{ + return 0 == dev->addr; +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_baseboard, + .enable = NULL, + .mode = { + .name = "SHARP-LQ156M1LG21", + .refresh = 60, + .xres = 1920, + .yres = 1080, + .pixclock = 7851, + .left_margin = 100, + .right_margin = 40, + .upper_margin = 30, + .lower_margin = 3, + .hsync_len = 10, + .vsync_len = 2, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 3, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + imx_setup_hdmi(); + + /* Set LDB_DI0 as clock source for IPU_DI0 */ + clrsetbits_le32(&mxc_ccm->chsccdr, + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, + (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); + + /* Turn on IPU LDB DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + enable_ipu_clock(); + + writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | + IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_SPLIT_MODE_EN_MASK | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | + IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + clrsetbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | + IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | + IOMUXC_GPR3_HDMI_MUX_CTL_MASK, + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)); + + /* backlights off until needed */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + + gpio_direction_input(LVDS_POWER_GP); + gpio_direction_input(LVDS_BACKLIGHT_GP); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + setup_pcie(); + + return cpu_eth_init(bis); +} + +static iomux_v3_cfg_t const misc_pads[] = { + MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL), + MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL), +}; +#define SUS_S3_OUT IMX_GPIO_NR(4, 11) +#define WIFI_EN IMX_GPIO_NR(6, 14) + +int setup_ba16_sata(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) + |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED + |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 + |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB + |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V + |IOMUXC_GPR13_SATA_PHY_1_SLOW); + + return 0; +} + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(misc_pads, + ARRAY_SIZE(misc_pads)); + + setup_iomux_uart(); + +#if defined(CONFIG_VIDEO_IPUV3) + /* Set LDB clock to PLL2 PFD0 */ + select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK); +#endif + return 0; +} + +int board_init(void) +{ + gpio_direction_output(SUS_S3_OUT, 1); + gpio_direction_output(WIFI_EN, 1); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + /* + * We need at least 200ms between power on and backlight on + * as per specifications from CHI MEI + */ + mdelay(250); + + /* enable backlight PWM 1 */ + pwm_init(0, 0, 0); + + /* duty cycle 5000000ns, period: 5000000ns */ + pwm_config(0, 5000000, 5000000); + + /* Backlight Power */ + gpio_direction_output(LVDS_BACKLIGHT_GP, 1); + + pwm_enable(0); + +#ifdef CONFIG_CMD_SATA + setup_ba16_sata(); +#endif + + return 0; +} + +int checkboard(void) +{ + printf("BOARD: %s\n", CONFIG_BOARD_NAME); + return 0; +} diff --git a/board/advantech/dms-ba16/dms-ba16_1g.cfg b/board/advantech/dms-ba16/dms-ba16_1g.cfg new file mode 100644 index 0000000000..d5de1fd751 --- /dev/null +++ b/board/advantech/dms-ba16/dms-ba16_1g.cfg @@ -0,0 +1,25 @@ +/* + * + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +IMAGE_VERSION 2 +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "micron-1g.cfg" +#include "clocks.cfg" diff --git a/board/advantech/dms-ba16/dms-ba16_2g.cfg b/board/advantech/dms-ba16/dms-ba16_2g.cfg new file mode 100644 index 0000000000..a731af60e8 --- /dev/null +++ b/board/advantech/dms-ba16/dms-ba16_2g.cfg @@ -0,0 +1,25 @@ +/* + * + * Copyright 2015 Timesys Corporation. + * Copyright 2015 General Electric Company + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +IMAGE_VERSION 2 +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "samsung-2g.cfg" +#include "clocks.cfg" diff --git a/board/advantech/dms-ba16/micron-1g.cfg b/board/advantech/dms-ba16/micron-1g.cfg new file mode 100644 index 0000000000..8cfefe28e2 --- /dev/null +++ b/board/advantech/dms-ba16/micron-1g.cfg @@ -0,0 +1,63 @@ +/* Calibrations */ +/* ZQ */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +/* write leveling */ +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F +/* Read DQS Gating calibration */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43480350 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x033C0340 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43480350 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03340314 +/* Read calibration */ +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x382E2C32 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363044 +/* Write calibration */ +DATA 4 MX6_MMDC_P0_MPWRDLCTL, 0x3A38403A +DATA 4 MX6_MMDC_P1_MPWRDLCTL, 0x4432483E +/* read data bit delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* MMDC init */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A79A5 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005a1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831a0000 + +/* Initialize memory */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048039 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00033337 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00033337 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/board/advantech/dms-ba16/samsung-2g.cfg b/board/advantech/dms-ba16/samsung-2g.cfg new file mode 100644 index 0000000000..4166cc9c57 --- /dev/null +++ b/board/advantech/dms-ba16/samsung-2g.cfg @@ -0,0 +1,63 @@ +/* Calibrations */ +/* ZQ */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +/* write leveling */ +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F +/* Read DQS Gating calibration */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C +/* Read calibration */ +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042 +/* Write calibration */ +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E +/* read data bit delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* MMDC init */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 +DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000 + +/* Initialize memory */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c index f651a40a49..9d28da4ba4 100644 --- a/board/bachmann/ot1200/ot1200_spl.c +++ b/board/bachmann/ot1200/ot1200_spl.c @@ -85,6 +85,8 @@ static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = { .bi_on = 1, /* Bank interleaving enabled */ /* war 1 */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; /* MT41K128M16JT-125 */ diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c index 098542fbd2..ec57cf1205 100644 --- a/board/barco/platinum/spl_picon.c +++ b/board/barco/platinum/spl_picon.c @@ -138,6 +138,8 @@ static void spl_dram_init(int width) .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c index a3a42551b0..d1ba85ab82 100644 --- a/board/barco/platinum/spl_titanium.c +++ b/board/barco/platinum/spl_titanium.c @@ -141,6 +141,8 @@ static void spl_dram_init(int width) .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); diff --git a/board/ccv/xpress/spl.c b/board/ccv/xpress/spl.c index d15b8429ba..bea837d430 100644 --- a/board/ccv/xpress/spl.c +++ b/board/ccv/xpress/spl.c @@ -60,6 +60,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = { .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; static struct mx6_ddr3_cfg mem_ddr = { diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 566c19b4c9..28e9a8f41f 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -588,7 +588,7 @@ struct node_info nodes[] = { /* * Both entries target the same flash chip. The st,m25p compatible * is used in the vendor device trees, while upstream uses (the - * documented) jedec,spi-nor comptatible. + * documented) jedec,spi-nor compatible. */ { "st,m25p", MTD_DEV_TYPE_NOR, }, { "jedec,spi-nor", MTD_DEV_TYPE_NOR, }, @@ -616,6 +616,8 @@ int ft_board_setup(void *blob, bd_t *bd) enetaddr, 6, 1); } + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + baseboard_rev = cl_eeprom_get_board_rev(0); err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0); if (err || baseboard_rev == 0) @@ -630,8 +632,6 @@ int ft_board_setup(void *blob, bd_t *bd) NULL, 0, 1); } - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - return 0; } #endif diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c index d8328fdadd..9442d09820 100644 --- a/board/compulab/cm_fx6/spl.c +++ b/board/compulab/cm_fx6/spl.c @@ -107,6 +107,8 @@ static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = { .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = { @@ -174,6 +176,8 @@ static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = { .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = { diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 3fbd3d2aaa..a4a602943e 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -1037,6 +1037,8 @@ static void spl_dram_init(int width) .bi_on = 1, .sde_to_rst = 0x0d, .rst_to_cke = 0x20, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) { diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c index 3b0fb323bd..7856b84341 100644 --- a/board/el/el6x/el6x.c +++ b/board/el/el6x/el6x.c @@ -604,6 +604,8 @@ static void spl_dram_init(void) .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 0cf68097f4..f836ecbf27 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -854,6 +854,8 @@ static void spl_dram_init(void) .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; if (is_mx6dqp()) { diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index f978e5044e..96c0e8cfc7 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -494,6 +494,8 @@ static void spl_dram_init(void) .sde_to_rst = 0, /* LPDDR2 does not need this field */ .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ .ddr_type = DDR_TYPE_LPDDR2, + .refsel = 0, /* Refresh cycles at 64KHz */ + .refr = 3, /* 4 refresh commands per refresh cycle */ }; mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 8d95c51aaf..965e511166 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -637,6 +637,8 @@ static void spl_dram_init(void) .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 66d679556b..399bad215f 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -193,9 +193,7 @@ int power_init_board(void) reg, rev_id); /* disable Low Power Mode during standby mode */ - pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); - reg |= 0x1; - pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); /* SW1B step ramp up time from 2us to 4us/25mV */ reg = 0x40; @@ -277,18 +275,16 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; -static iomux_v3_cfg_t const usdhc2_cd_pads[] = { - /* - * The evk board uses DAT3 to detect CD card plugin, - * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. - */ - MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), -}; +/* + * The evk board uses DAT3 to detect CD card plugin, + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. + */ +static iomux_v3_cfg_t const usdhc2_cd_pad = + MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL); -static iomux_v3_cfg_t const usdhc2_dat3_pads[] = { +static iomux_v3_cfg_t const usdhc2_dat3_pad = MX6_PAD_NAND_DATA03__USDHC2_DATA3 | - MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), -}; + MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL); #endif static void setup_iomux_uart(void) @@ -351,8 +347,7 @@ int board_mmc_getcd(struct mmc *mmc) #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) ret = 1; #else - imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads, - ARRAY_SIZE(usdhc2_cd_pads)); + imx_iomux_v3_setup_pad(usdhc2_cd_pad); gpio_direction_input(USDHC2_CD_GPIO); /* @@ -361,8 +356,7 @@ int board_mmc_getcd(struct mmc *mmc) */ ret = gpio_get_value(USDHC2_CD_GPIO); - imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads, - ARRAY_SIZE(usdhc2_dat3_pads)); + imx_iomux_v3_setup_pad(usdhc2_dat3_pad); #endif break; } @@ -770,6 +764,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = { .sde_to_rst = 0, /* LPDDR2 does not need this field */ .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ .ddr_type = DDR_TYPE_LPDDR2, + .refsel = 0, /* Refresh cycles at 64KHz */ + .refr = 3, /* 4 refresh commands per refresh cycle */ }; #else @@ -781,17 +777,17 @@ static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { .dram_odt0 = 0x00000030, .dram_odt1 = 0x00000030, .dram_sdba2 = 0x00000000, - .dram_sdclk_0 = 0x00000008, - .dram_sdqs0 = 0x00000038, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, .dram_sdqs1 = 0x00000030, .dram_reset = 0x00000030, }; static struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00070007, - .p0_mpdgctrl0 = 0x41490145, - .p0_mprddlctl = 0x40404546, - .p0_mpwrdlctl = 0x4040524D, + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41570155, + .p0_mprddlctl = 0x4040474A, + .p0_mpwrdlctl = 0x40405550, }; struct mx6_ddr_sysinfo ddr_sysinfo = { @@ -801,13 +797,15 @@ struct mx6_ddr_sysinfo ddr_sysinfo = { .cs1_mirror = 0, .rtt_wr = 2, .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ - .walat = 1, /* Write additional latency */ + .walat = 0, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, + .refsel = 0, /* Refresh cycles at 64KHz */ + .refr = 1, /* 2 refresh commands per refresh cycle */ }; static struct mx6_ddr3_cfg mem_ddr = { @@ -846,11 +844,11 @@ static void spl_dram_init(void) void board_init_f(ulong dummy) { + ccgr_init(); + /* setup AIPS and disable watchdog */ arch_cpu_init(); - ccgr_init(); - /* iomux and setup of i2c */ board_early_init_f(); diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 1f4fc03c8f..b9365445e8 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -578,9 +578,7 @@ int power_init_board(void) printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); /* disable Low Power Mode during standby mode */ - pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); - reg |= 0x1; - pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); + pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1); return 0; } @@ -609,7 +607,14 @@ int board_late_init(void) int checkboard(void) { - puts("Board: i.MX7D SABRESD\n"); + char *mode; + + if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) + mode = "secure"; + else + mode = "non-secure"; + + printf("Board: i.MX7D SABRESD in %s mode\n", mode); return 0; } diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index e7f699a2b5..b610e06f1d 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -394,6 +394,8 @@ static void spl_dram_init(int width, int size_mb, int board_model) .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .pd_fast_exit = 1, /* enable precharge power-down fast exit */ .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; /* diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index f779bb484a..92c61aebb1 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -520,6 +520,8 @@ static struct mx6_ddr_sysinfo novena_ddr_info = { .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; static struct mx6_ddr3_cfg elpida_4gib_1600 = { diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c index 0ba4a2e268..4e2122f6f9 100644 --- a/board/phytec/pcm058/pcm058.c +++ b/board/phytec/pcm058/pcm058.c @@ -521,6 +521,8 @@ static void spl_dram_init(void) .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index cafa348150..3a1ce240b8 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -605,6 +605,8 @@ static void spl_dram_init(int width) .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; if (is_mx6dq()) diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c index 5cbf803e7e..49aeb80327 100644 --- a/board/technexion/pico-imx6ul/pico-imx6ul.c +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c @@ -231,9 +231,7 @@ int power_init_board(void) printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); /* disable Low Power Mode during standby mode */ - pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); - reg |= 0x1; - pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); /* SW1B step ramp up time from 2us to 4us/25mV */ pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40); diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c index a1154edf69..592e69b0d7 100644 --- a/board/udoo/udoo_spl.c +++ b/board/udoo/udoo_spl.c @@ -193,6 +193,8 @@ static struct mx6_ddr_sysinfo mem_qdl = { .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; static void ccgr_init(void) diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 77afae7afd..085095c646 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -187,6 +187,8 @@ static struct mx6_ddr_sysinfo mem_q = { .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { @@ -228,6 +230,8 @@ static struct mx6_ddr_sysinfo mem_dl = { .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; /* DDR 32bit 512MB */ @@ -245,6 +249,8 @@ static struct mx6_ddr_sysinfo mem_s = { .mif3_mode = 3, .rst_to_cke = 0x23, .sde_to_rst = 0x10, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ }; static void ccgr_init(void) diff --git a/board/warp/imximage.cfg b/board/warp/imximage.cfg new file mode 100644 index 0000000000..7b1d6b7b01 --- /dev/null +++ b/board/warp/imximage.cfg @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020c4018 0x00260324 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020e0344 0x00003030 +DATA 4 0x020e0348 0x00003030 +DATA 4 0x020e034c 0x00003030 +DATA 4 0x020e0350 0x00003030 +DATA 4 0x020e030c 0x00000030 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0318 0x00000030 +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e031c 0x00000030 +DATA 4 0x020e0338 0x00000028 +DATA 4 0x020e0320 0x00000030 +DATA 4 0x020e032c 0x00000000 +DATA 4 0x020e033c 0x00000008 +DATA 4 0x020e0340 0x00000008 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x020e05cc 0x00000030 +DATA 4 0x020e05d4 0x00000030 +DATA 4 0x020e05d8 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05c8 0x00000030 +DATA 4 0x020e05b0 0x00020000 +DATA 4 0x020e05b4 0x00000000 +DATA 4 0x020e05c0 0x00020000 +DATA 4 0x020e05d0 0x00080000 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b0848 0x4241444a +DATA 4 0x021b0850 0x3030312b +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b08c0 0x24911492 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A82 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001688 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x009f0e10 +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0x83110000 +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x02038030 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x02038038 +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x00025564 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 27e31f35d5..da9afb4ccd 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -11,12 +11,17 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> #include <asm/io.h> #include <common.h> #include <fsl_esdhc.h> +#include <i2c.h> #include <mmc.h> #include <asm/arch/crm_regs.h> #include <usb.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include "../freescale/common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +30,26 @@ DECLARE_GLOBAL_DATA_PTR; #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, + .gp = IMX_GPIO_NR(4, 8), + }, + .sda = { + .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, + .gp = IMX_GPIO_NR(4, 9), + }, +}; +#endif + int dram_init(void) { gd->ram_size = PHYS_SDRAM_SIZE; @@ -85,17 +110,56 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE3000"); + ret = pmic_probe(pfuze); + if (ret) + return ret; + + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); + + return 0; +} +#endif + int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + #ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + #endif + return 0; } int checkboard(void) { - puts("Board: WARP7\n"); + char *mode; + + if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) + mode = "secure"; + else + mode = "non-secure"; + + printf("Board: WARP7 in %s mode\n", mode); return 0; } diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig new file mode 100644 index 0000000000..a579af440c --- /dev/null +++ b/configs/dms-ba16-1g_defconfig @@ -0,0 +1,34 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_ADVANTECH_DMS_BA16=y +CONFIG_SYS_DDR_1G=y +CONFIG_HUSH_PARSER=y +CONFIG_BOOTDELAY=1 +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Advantech" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig new file mode 100644 index 0000000000..365d05c345 --- /dev/null +++ b/configs/dms-ba16_defconfig @@ -0,0 +1,33 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_ADVANTECH_DMS_BA16=y +CONFIG_HUSH_PARSER=y +CONFIG_BOOTDELAY=1 +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Advantech" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 diff --git a/configs/warp7_secure_defconfig b/configs/warp7_secure_defconfig new file mode 100644 index 0000000000..34fcdea1e3 --- /dev/null +++ b/configs/warp7_secure_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_WARP7=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="FSL" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_OF_LIBFDT=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index 389bb7fd8f..786d7e8bc7 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_WARP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp/imximage.cfg,MX6SL" CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 94fc5c18a0..4bf564e4f5 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -37,7 +37,12 @@ #endif #define MXS_NAND_METADATA_SIZE 10 #define MXS_NAND_BITS_PER_ECC_LEVEL 13 + +#if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32 #define MXS_NAND_COMMAND_BUFFER_SIZE 32 +#else +#define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE +#endif #define MXS_NAND_BCH_TIMEOUT 10000 diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h new file mode 100644 index 0000000000..992948ad4a --- /dev/null +++ b/include/configs/advantech_dms-ba16.h @@ -0,0 +1,315 @@ +/* + * Copyright (C) 2016 Timesys Corporation + * Copyright (C) 2016 Advantech Corporation + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ADVANTECH_DMSBA16_CONFIG_H +#define __ADVANTECH_DMSBA16_CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +#define CONFIG_BOARD_NAME "Advantech DMS-BA16" +#define CONFIG_DEFAULT_FDT_FILE "imx6q-dms-ba16.dtb" + +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONFIG_CONSOLE_DEV "ttymxc3" +#define CONFIG_EXTRA_BOOTARGS "panic=10" + +#define CONFIG_BOOT_DIR "" +#define CONFIG_LOADCMD "fatload" +#define CONFIG_RFSPART "2" + +#define CONFIG_SUPPORT_EMMC_BOOT + +#include "mx6_common.h" +#include <linux/sizes.h> + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_GPIO +#define CONFIG_MXC_UART + +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +/* SATA Configs */ +#define CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_DOS_PARTITION + +/* USB Configs */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP + +#define CONFIG_USBD_HS +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +/* Networking Configs */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 4 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* Serial Flash */ +#ifdef CONFIG_CMD_SF +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#define CONFIG_CMD_BMODE + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=" CONFIG_BOOT_DIR "/uImage\0" \ + "uboot=u-boot.imx\0" \ + "fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x18000000\0" \ + "boot_fdt=yes\0" \ + "ip_dyn=yes\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "sddev=0\0" \ + "emmcdev=1\0" \ + "partnum=1\0" \ + "loadcmd=" CONFIG_LOADCMD "\0" \ + "rfspart=" CONFIG_RFSPART "\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "update_sf_uboot=" \ + "if tftp $loadaddr $uboot; then " \ + "sf probe; " \ + "sf erase 0 0xC0000; " \ + "sf write $loadaddr 0x400 $filesize; " \ + "echo 'U-Boot upgraded. Please reset'; " \ + "fi\0" \ + "setargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \ + "loadbootscript=" \ + "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \ + " source\0" \ + "loadimage=" \ + "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ + "loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \ + "tryboot=" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run doboot; " \ + "fi; " \ + "fi;\0" \ + "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \ + "run setargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "usb start; " \ + "setenv dev usb; " \ + "setenv devnum 0; " \ + "setenv rootdev sda${rfspart}; " \ + "run tryboot; " \ + \ + "setenv dev mmc; " \ + "setenv rootdev mmcblk0p${rfspart}; " \ + \ + "setenv devnum ${sddev}; " \ + "if mmc dev ${devnum}; then " \ + "run tryboot; " \ + "fi; " \ + \ + "setenv devnum ${emmcdev}; " \ + "setenv rootdev mmcblk${emmcdev}p${rfspart}; " \ + "if mmc dev ${devnum}; then " \ + "run tryboot; " \ + "fi; " \ + \ + "bmode usb; " \ + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED + +#ifndef CONFIG_SYS_DCACHE_OFF +#endif + +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#define CONFIG_PWM_IMX +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#undef CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) +#endif + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_MXC_I2C2 +#define CONFIG_SYS_I2C_MXC_I2C3 + +#endif /* __ADVANTECH_DMSBA16_CONFIG_H */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 1bd13fe6de..61242a12c5 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -191,15 +191,15 @@ #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_CMD_HDMIDETECT #define CONFIG_CONSOLE_MUX #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_HIDE_LOGO_VERSION /* Custom config to hide U-boot version */ /* Miscellaneous configurable options */ #define CONFIG_HWCONFIG @@ -274,6 +274,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ "pcidisable=1\0" \ + "splashpos=m,m\0" \ "usb_pgood_delay=2000\0" \ "console=ttymxc1\0" \ "bootdevs=usb mmc sata flash\0" \ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index ec0bf05084..640bce4b0a 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -129,9 +129,9 @@ #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE #define CONFIG_SYS_STDIO_DEREGISTER #define CONFIG_PREBOOT \ + "usb start; " \ "if hdmidet; then " \ - "usb start; " \ - "run set_con_usb_hdmi; " \ + "run set_con_hdmi; " \ "else " \ "run set_con_serial; " \ "fi;" @@ -181,12 +181,13 @@ "bootm 0x10800000 0x10d00000\0" \ "console=ttymxc0\0" \ "fan=gpio set 92\0" \ - "set_con_serial=setenv stdin serial; " \ - "setenv stdout serial; " \ + "set_con_serial=setenv stdout serial; " \ "setenv stderr serial;\0" \ - "set_con_usb_hdmi=setenv stdin serial,usbkbd; " \ - "setenv stdout serial,vga; " \ - "setenv stderr serial,vga;\0" + "set_con_hdmi=setenv stdout serial,vga; " \ + "setenv stderr serial,vga;\0" \ + "stderr=serial,vga;\0" \ + "stdin=serial,usbkbd;\0" \ + "stdout=serial,vga;\0" #define CONFIG_BOOTCOMMAND \ "mmc rescan; " \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index e59b16c379..5cbc2c4d37 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -29,6 +29,9 @@ #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ @@ -39,15 +42,15 @@ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx7d-warp.dtb\0" \ + "fdt_file=imx7s-warp.dtb\0" \ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "finduuid=part uuid mmc 0:2 uuid\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ + "root=PARTUUID=${uuid} rootwait rw\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ @@ -55,6 +58,7 @@ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ @@ -103,6 +107,18 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +/* I2C configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_SIZE SZ_8K @@ -113,7 +129,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 0 -#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USB Configs */ #define CONFIG_USB_STORAGE diff --git a/tools/logos/gateworks.bmp b/tools/logos/gateworks.bmp Binary files differnew file mode 100644 index 0000000000..01edb7cedf --- /dev/null +++ b/tools/logos/gateworks.bmp |
