diff options
259 files changed, 2339 insertions, 561 deletions
@@ -147,7 +147,9 @@ config SYS_MALLOC_F_LEN default 0x1000 if AM33XX default 0x2800 if SANDBOX default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \ - ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5) + ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \ + ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \ + ARCH_LS1046A) default 0x400 help Before relocation, memory is very limited on many platforms. Still, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index e2b92f0eab..275c66d992 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -16,8 +16,8 @@ config ARCH_LS1012A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C1 if !DM_I2C + select SYS_I2C_MXC_I2C2 if !DM_I2C imply PANIC_HANG config ARCH_LS1028A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 8a6eecab22..accad6e8ae 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -72,9 +72,11 @@ void board_init_f(ulong dummy) preloader_console_init(); spl_set_bd(); +#ifdef CONFIG_SYS_I2C #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init_all(); #endif +#endif #ifdef CONFIG_VID init_func_vid(); #endif diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts index 5d143ba077..3fd37beedf 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dts +++ b/arch/arm/dts/fsl-ls1028a-qds.dts @@ -13,6 +13,10 @@ / { model = "NXP Layerscape 1028a QDS Board"; compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; + aliases { + spi0 = &fspi; + }; + }; &dspi0 { @@ -36,6 +40,18 @@ }; +&fspi { + status = "okay"; + + mt35xu02g0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + &i2c0 { status = "okay"; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 3d5e8ade21..a8f40855b6 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -13,6 +13,9 @@ / { model = "NXP Layerscape 1028a RDB Board"; compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; + aliases { + spi0 = &fspi; + }; }; &dspi0 { @@ -36,6 +39,18 @@ mmc-hs200-1_8v; }; +&fspi { + status = "okay"; + + mt35xu02g0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + &i2c0 { status = "okay"; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 43a154e8e7..5365bfb1a8 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -6,6 +6,8 @@ * */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + / { compatible = "fsl,ls1028a"; interrupt-parent = <&gic>; @@ -38,25 +40,32 @@ <0x0 0x06040000 0 0x40000>; #interrupt-cells = <3>; interrupt-controller; - interrupts = <1 9 0x4>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | + IRQ_TYPE_LEVEL_LOW)>; }; timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ - <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ - <1 11 0x8>, /* Virtual PPI, active-low */ - <1 10 0x8>; /* Hypervisor PPI, active-low */ + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>; }; - fspi: flexspi@20C0000 { - compatible = "nxp,dn-fspi"; + fspi: flexspi@20c0000 { + compatible = "nxp,lx2160a-fspi"; #address-cells = <1>; #size-cells = <0>; - reg = <0x0 0x20C0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/ - reg-names = "FSPI", "FSPI-memory"; - num-cs = <1>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "fspi_en", "fspi"; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -64,7 +73,7 @@ device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; - interrupts = <0 32 0x1>; /* edge triggered */ + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -72,7 +81,7 @@ device_type = "serial"; compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; - interrupts = <0 32 0x1>; /* edge triggered */ + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -148,7 +157,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 0x4>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; clocks = <&clockgen 4 0>; status = "disabled"; @@ -159,7 +168,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 0x4>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; clocks = <&clockgen 4 0>; status = "disabled"; @@ -170,7 +179,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 0x4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; clocks = <&clockgen 4 0>; status = "disabled"; @@ -181,7 +190,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 0x4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; clocks = <&clockgen 4 0>; status = "disabled"; @@ -192,7 +201,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2040000 0x0 0x10000>; - interrupts = <0 74 0x4>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; clocks = <&clockgen 4 0>; status = "disabled"; @@ -203,7 +212,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2050000 0x0 0x10000>; - interrupts = <0 74 0x4>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; clocks = <&clockgen 4 0>; status = "disabled"; @@ -214,7 +223,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2060000 0x0 0x10000>; - interrupts = <0 75 0x4>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; clocks = <&clockgen 4 0>; status = "disabled"; @@ -225,7 +234,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2070000 0x0 0x10000>; - interrupts = <0 75 0x4>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; clocks = <&clockgen 4 0>; status = "disabled"; @@ -234,7 +243,7 @@ usb1: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 0x4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; status = "disabled"; }; @@ -242,7 +251,7 @@ usb2: usb3@3110000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 0x4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; status = "disabled"; }; @@ -252,7 +261,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 26 0x4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; clocks = <&clockgen 4 0>; num-cs = <5>; @@ -265,7 +274,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = <0 26 0x4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; clocks = <&clockgen 4 0>; num-cs = <5>; @@ -278,7 +287,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2120000 0x0 0x10000>; - interrupts = <0 26 0x4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; clocks = <&clockgen 4 0>; num-cs = <5>; @@ -289,7 +298,7 @@ esdhc0: esdhc@2140000 { compatible = "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; big-endian; bus-width = <4>; status = "disabled"; @@ -298,7 +307,7 @@ esdhc1: esdhc@2150000 { compatible = "fsl,esdhc"; reg = <0x0 0x2150000 0x0 0x10000>; - interrupts = <0 63 0x4>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; big-endian; non-removable; bus-width = <4>; @@ -310,7 +319,7 @@ reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ reg-names = "sata-base", "ecc-addr"; - interrupts = <0 133 4>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index 46a9239c25..e542c6992a 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -16,7 +16,9 @@ / { model = "NXP Layerscape LX2160ARDB Board"; compatible = "fsl,lx2160ardb", "fsl,lx2160a"; - + aliases { + spi0 = &fspi; + }; }; &esdhc0 { @@ -28,6 +30,26 @@ mmc-hs200-1_8v; }; +&fspi { + status = "okay"; + + mt35xu512aba0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + + mt35xu512aba1: flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; + &i2c0 { status = "okay"; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 9d018cad1c..42ce4379ec 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -6,6 +6,8 @@ * */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + / { compatible = "fsl,lx2160a"; interrupt-parent = <&gic>; @@ -49,6 +51,19 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; + fspi: flexspi@20c0000 { + compatible = "nxp,lx2160a-fspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "fspi_en", "fspi"; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 44bedd8b67..2e4468e8d8 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -56,3 +56,7 @@ &portc { bank-name = "portc"; }; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index 38855aecd7..a903040d60 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -31,3 +31,7 @@ &sysmgr { u-boot,dm-pre-reloc; }; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index acb7ea9a3e..39ffc18e29 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -4,6 +4,7 @@ !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \ !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ + !defined(CONFIG_ARCH_LS1012A) && \ !defined(CONFIG_ARCH_U8500) #include <asm/arch/gpio.h> #endif diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 3b5f45b431..9966d6c833 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -42,9 +42,9 @@ static struct mm_region bcm2711_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .virt = 0xfe000000UL, - .phys = 0xfe000000UL, - .size = 0x01800000UL, + .virt = 0xfc000000UL, + .phys = 0xfc000000UL, + .size = 0x03800000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h index c41208591a..8818a6b967 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h @@ -146,24 +146,51 @@ struct socfpga_sdram_rw_mgr_config { u8 lfsr_wr_rd_dm_bank_0_nop; u8 lfsr_wr_rd_dm_bank_0_wait; u8 lfsr_wr_rd_dm_bank_0_wl_1; - u8 mrs0_dll_reset; - u8 mrs0_dll_reset_mirr; - u8 mrs0_user; - u8 mrs0_user_mirr; - u8 mrs1; + union { + u8 mrs0_dll_reset; + u8 mr_dll_reset; + }; + union { + u8 mrs0_dll_reset_mirr; + u8 emr_ocd_enable; + }; + union { + u8 mrs0_user; + u8 mr_user; + }; + union { + u8 mrs0_user_mirr; + u8 mr_calib; + }; + union { + u8 mrs1; + u8 emr; + }; + union { + u8 mrs2; + u8 emr2; + }; + union { + u8 mrs3; + u8 emr3; + }; u8 mrs1_mirr; - u8 mrs2; u8 mrs2_mirr; - u8 mrs3; u8 mrs3_mirr; u8 precharge_all; u8 read_b2b; u8 read_b2b_wait1; u8 read_b2b_wait2; - u8 refresh_all; + union { + u8 refresh; + u8 refresh_all; + }; u8 rreturn; u8 sgle_read; - u8 zqcl; + union { + u8 zqcl; + u8 nop; + }; u8 true_mem_data_mask_width; u8 mem_address_mirroring; @@ -199,6 +226,7 @@ struct socfpga_sdram_io_config { struct socfpga_sdram_misc_config { u32 reg_file_init_seq_signature; + u16 afi_clk_freq; u8 afi_rate_ratio; u8 calib_lfifo_offset; u8 calib_vfifo_offset; diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh index 3a442bc5d8..a49cd1b68a 100755 --- a/arch/arm/mach-socfpga/qts-filter.sh +++ b/arch/arm/mach-socfpga/qts-filter.sh @@ -128,7 +128,7 @@ EOF # Filter out only the macros which are actually used by the code # grep_sdram_config() { - egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]" + egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]" } # diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 70f8455ddc..a01e2a5cb9 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -138,10 +138,7 @@ void board_init_f(ulong dummy) debug("Reset init failed: %d\n", ret); #ifdef CONFIG_SPL_NAND_DENALI - struct socfpga_reset_manager *reset_manager_base = - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; - - clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4)); + clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4)); #endif /* enable console uart printing */ diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index 2b072cc65e..4ea32e72c7 100644 --- a/arch/arm/mach-socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -80,13 +80,15 @@ static const struct socfpga_sdram_config sdram_config = { SDR_CTRLGRP_DRAMODT_READ_LSB) | (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << SDR_CTRLGRP_DRAMODT_WRITE_LSB), +#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */ .extratime1 = - (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR << - SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC << - SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) | -(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP << - SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB), + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR << + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC << + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP << + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB), +#endif .dram_addrw = (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | @@ -190,7 +192,6 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { .activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1, .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1, .activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2, - .activate_1 = RW_MGR_ACTIVATE_1, .clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE, .guaranteed_read = RW_MGR_GUARANTEED_READ, .guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT, @@ -199,11 +200,41 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { .guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1, .guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2, .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3, - .idle = RW_MGR_IDLE, .idle_loop1 = RW_MGR_IDLE_LOOP1, .idle_loop2 = RW_MGR_IDLE_LOOP2, +#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */ + .emr = RW_MGR_EMR, + .emr2 = RW_MGR_EMR2, + .emr3 = RW_MGR_EMR3, + .init_reset_0_cke_0 = RW_MGR_INIT_CKE_0, + .nop = RW_MGR_NOP, + .refresh = RW_MGR_REFRESH, + .mr_calib = RW_MGR_MR_CALIB, + .mr_user = RW_MGR_MR_USER, + .mr_dll_reset = RW_MGR_MR_DLL_RESET, + .emr_ocd_enable = RW_MGR_EMR_OCD_ENABLE, +#elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */ + .activate_1 = RW_MGR_ACTIVATE_1, + .idle = RW_MGR_IDLE, .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0, .init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0, + .mrs1 = RW_MGR_MRS1, + .mrs1_mirr = RW_MGR_MRS1_MIRR, + .mrs2 = RW_MGR_MRS2, + .mrs2_mirr = RW_MGR_MRS2_MIRR, + .mrs3 = RW_MGR_MRS3, + .mrs3_mirr = RW_MGR_MRS3_MIRR, + .refresh_all = RW_MGR_REFRESH_ALL, + .rreturn = RW_MGR_RETURN, + .sgle_read = RW_MGR_SGLE_READ, + .zqcl = RW_MGR_ZQCL, + .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET, + .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR, + .mrs0_user = RW_MGR_MRS0_USER, + .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR, +#else +#error LPDDR2 and other DRAM types are not yet supported +#endif .lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0, .lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA, .lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS, @@ -216,24 +247,10 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { .lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, .lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1, - .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET, - .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR, - .mrs0_user = RW_MGR_MRS0_USER, - .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR, - .mrs1 = RW_MGR_MRS1, - .mrs1_mirr = RW_MGR_MRS1_MIRR, - .mrs2 = RW_MGR_MRS2, - .mrs2_mirr = RW_MGR_MRS2_MIRR, - .mrs3 = RW_MGR_MRS3, - .mrs3_mirr = RW_MGR_MRS3_MIRR, .precharge_all = RW_MGR_PRECHARGE_ALL, .read_b2b = RW_MGR_READ_B2B, .read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1, .read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2, - .refresh_all = RW_MGR_REFRESH_ALL, - .rreturn = RW_MGR_RETURN, - .sgle_read = RW_MGR_SGLE_READ, - .zqcl = RW_MGR_ZQCL, .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH, .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING, @@ -270,6 +287,9 @@ static const struct socfpga_sdram_io_config io_config = { }; static const struct socfpga_sdram_misc_config misc_config = { +#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */ + .afi_clk_freq = AFI_CLK_FREQ, +#endif .afi_rate_ratio = AFI_RATE_RATIO, .calib_lfifo_offset = CALIB_LFIFO_OFFSET, .calib_vfifo_offset = CALIB_VFIFO_OFFSET, diff --git a/board/freescale/common/dcu_sii9022a.c b/board/freescale/common/dcu_sii9022a.c index 3bf71abf55..832ae258f1 100644 --- a/board/freescale/common/dcu_sii9022a.c +++ b/board/freescale/common/dcu_sii9022a.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include <asm/io.h> @@ -63,7 +64,101 @@ int dcu_set_dvi_encoder(struct fb_videomode *videomode) u8 temp; u16 temp1, temp2; u32 temp3; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM, + CONFIG_SYS_I2C_DVI_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + CONFIG_SYS_I2C_DVI_BUS_NUM); + return ret; + } + /* Enable TPI transmitter mode */ + temp = TPI_TRANS_MODE_ENABLE; + dm_i2c_write(dev, TPI_TRANS_MODE_REG, &temp, 1); + + /* Enter into D0 state, full operation */ + dm_i2c_read(dev, TPI_PWR_STAT_REG, &temp, 1); + temp &= ~TPI_PWR_STAT_MASK; + temp |= TPI_PWR_STAT_D0; + dm_i2c_write(dev, TPI_PWR_STAT_REG, &temp, 1); + + /* Enable source termination */ + temp = TPI_SET_PAGE_SII9022A; + dm_i2c_write(dev, TPI_SET_PAGE_REG, &temp, 1); + temp = TPI_SET_OFFSET_SII9022A; + dm_i2c_write(dev, TPI_SET_OFFSET_REG, &temp, 1); + + dm_i2c_read(dev, TPI_RW_ACCESS_REG, &temp, 1); + temp |= TPI_RW_EN_SRC_TERMIN; + dm_i2c_write(dev, TPI_RW_ACCESS_REG, &temp, 1); + + /* Set TPI system control */ + temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE; + dm_i2c_write(dev, TPI_SYS_CTRL_REG, &temp, 1); + + /* Set pixel clock */ + temp1 = PICOS2KHZ(videomode->pixclock) / 10; + temp = (u8)(temp1 & 0xFF); + dm_i2c_write(dev, PIXEL_CLK_LSB_REG, &temp, 1); + temp = (u8)(temp1 >> 8); + dm_i2c_write(dev, PIXEL_CLK_MSB_REG, &temp, 1); + + /* Set total pixels per line */ + temp1 = videomode->hsync_len + videomode->left_margin + + videomode->xres + videomode->right_margin; + temp = (u8)(temp1 & 0xFF); + dm_i2c_write(dev, TOTAL_PIXELS_LSB_REG, &temp, 1); + temp = (u8)(temp1 >> 8); + dm_i2c_write(dev, TOTAL_PIXELS_MSB_REG, &temp, 1); + + /* Set total lines */ + temp2 = videomode->vsync_len + videomode->upper_margin + + videomode->yres + videomode->lower_margin; + temp = (u8)(temp2 & 0xFF); + dm_i2c_write(dev, TOTAL_LINES_LSB_REG, &temp, 1); + temp = (u8)(temp2 >> 8); + dm_i2c_write(dev, TOTAL_LINES_MSB_REG, &temp, 1); + + /* Set vertical frequency in Hz */ + temp3 = temp1 * temp2; + temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3; + temp1 = (u16)temp3 * 100; + temp = (u8)(temp1 & 0xFF); + dm_i2c_write(dev, VERT_FREQ_LSB_REG, &temp, 1); + temp = (u8)(temp1 >> 8); + dm_i2c_write(dev, VERT_FREQ_MSB_REG, &temp, 1); + + /* Set TPI input bus and pixel repetition data */ + temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE | + TPI_INBUS_RISING_EDGE; + dm_i2c_write(dev, TPI_INBUS_FMT_REG, &temp, 1); + + /* Set TPI AVI Input format data */ + temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO | + TPI_INPUT_CLR_RGB; + dm_i2c_write(dev, TPI_INPUT_FMT_REG, &temp, 1); + + /* Set TPI AVI Output format data */ + temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO | + TPI_OUTPUT_CLR_HDMI_RGB; + dm_i2c_write(dev, TPI_OUTPUT_FMT_REG, &temp, 1); + + /* Set TPI audio configuration write data */ + temp = TPI_AUDIO_PASS_BASIC; + dm_i2c_write(dev, TPI_AUDIO_HANDING_REG, &temp, 1); + + temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL | + TPI_AUDIO_TYPE_PCM; + dm_i2c_write(dev, TPI_AUDIO_INTF_REG, &temp, 1); + + temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K; + dm_i2c_write(dev, TPI_AUDIO_FREQ_REG, &temp, 1); +#else i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); /* Enable TPI transmitter mode */ @@ -147,6 +242,7 @@ int dcu_set_dvi_encoder(struct fb_videomode *videomode) temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K; i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1); +#endif return 0; } diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c index 435b4a3f1a..7f11123e6f 100644 --- a/board/freescale/common/diu_ch7301.c +++ b/board/freescale/common/diu_ch7301.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * Authors: Priyanka Jain <Priyanka.Jain@freescale.com> * Wang Dongsheng <dongsheng.wang@freescale.com> * @@ -51,6 +52,85 @@ int diu_set_dvi_encoder(unsigned int pixclock) u8 temp; temp = I2C_DVI_TEST_PATTERN_VAL; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM, + CONFIG_SYS_I2C_DVI_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + CONFIG_SYS_I2C_DVI_BUS_NUM); + return ret; + } + ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select proper dvi test pattern\n"); + return ret; + } + temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; + ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi input data format\n"); + return ret; + } + + /* Set Sync polarity register */ + temp = I2C_DVI_SYNC_POLARITY_VAL; + ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi syc polarity\n"); + return ret; + } + + /* Set PLL registers based on pixel clock rate*/ + if (pixclock > 65000000) { + temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } else { + temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; + ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } + + temp = I2C_DVI_POWER_MGMT_VAL; + ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi power mgmt\n"); + return ret; + } +#else ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, &temp, 1); if (ret) { @@ -128,6 +208,7 @@ int diu_set_dvi_encoder(unsigned int pixclock) puts("I2C: failed to select dvi power mgmt\n"); return ret; } +#endif udelay(500); diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 716c93b2c2..dd1ee90b3c 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2011 Freescale Semiconductor + * Copyright 2020 NXP * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com> * * This file provides support for the QIXIS of some Freescale reference boards. @@ -287,7 +288,9 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar #ifdef QIXIS_LBMAP_EMMC QIXIS_WRITE(rst_ctl, 0x30); QIXIS_WRITE(rcfg_ctl, 0); +#ifndef NON_EXTENDED_DUTCFG set_lbmap(QIXIS_LBMAP_EMMC); +#endif set_rcw_src(QIXIS_RCW_SRC_EMMC); QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); @@ -365,6 +368,7 @@ U_BOOT_CMD( "qixis watchdog <watchdog_period> - set the watchdog period\n" " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" "qixis_reset dump - display the QIXIS registers\n" + "qixis_reset emmc - reset to emmc\n" "qixis_reset switch - display switch\n" ); #endif diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 86c72ee357..30bf1047d5 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -107,10 +107,26 @@ int board_early_init_f(void) int misc_init_r(void) { u8 mux_sdhc_cd = 0x80; - - i2c_set_bus_num(0); + int bus_num = 0; + +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1); +#else + i2c_set_bus_num(bus_num); i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); +#endif + return 0; } #endif diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 51efd0fa37..639353a94b 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -82,8 +82,8 @@ if FSL_PFE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select PHYLIB - imply CONFIG_PHYLIB_10G - imply CONFIG_PHY_AQUANTIA + imply PHYLIB_10G + imply PHY_AQUANTIA config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c index 3cc0a65cb9..5edcfcf1ce 100644 --- a/board/freescale/ls1012ardb/eth.c +++ b/board/freescale/ls1012ardb/eth.c @@ -28,12 +28,47 @@ static inline void ls1012ardb_reset_phy(void) { #ifdef CONFIG_TARGET_LS1012ARDB /* Through reset IO expander reset both RGMII and SGMII PHYs */ +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + /* + * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0). + */ + ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + 0); + return; + } + /* Config port 0 + * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B + * are enabled as an output. + */ + dm_i2c_reg_write(dev, 6, __PHY_MASK); + + /* + * Set port 0 output a value to reset ETH2 interface + * - pin IOXP_RST_ETH2_B output 0b0 + */ + dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK); + mdelay(10); + dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK); + /* + * Set port 0 output a value to reset ETH1 interface + * - pin IOXP_RST_ETH1_B output 0b0 + */ + mdelay(10); + dm_i2c_reg_write(dev, 2, 0xFF); +#else i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK); i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK); mdelay(10); i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK); mdelay(10); i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF); +#endif mdelay(50); #endif } diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 0f665c7bc6..ab83ef11a0 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -34,13 +34,27 @@ int checkboard(void) { #ifdef CONFIG_TARGET_LS1012ARDB u8 in1; + int ret, bus_num = 0; puts("Board: LS1012ARDB "); /* Initialize i2c early for Serial flash bank information */ - i2c_set_bus_num(0); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; - if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) { + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1); +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1); +#endif + if (ret < 0) { printf("Error reading i2c boot information!\n"); return 0; /* Don't want to hang() on this error */ } @@ -175,11 +189,25 @@ int esdhc_status_fixup(void *blob, const char *compat) bool sdhc2_en = false; u8 mux_sdhc2; u8 io = 0; + int ret, bus_num = 0; - i2c_set_bus_num(0); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1); +#else + i2c_set_bus_num(bus_num); /* IO1[7:3] is the field of board revision info. */ - if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) { + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1); +#endif + if (ret < 0) { printf("Error reading i2c boot information!\n"); return 0; } @@ -202,7 +230,12 @@ int esdhc_status_fixup(void *blob, const char *compat) * 10 - eMMC Memory * 11 - SPI */ - if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) { +#if defined(CONFIG_DM_I2C) + ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1); +#else + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1); +#endif + if (ret < 0) { printf("Error reading i2c boot information!\n"); return 0; } @@ -233,16 +266,63 @@ int ft_board_setup(void *blob, bd_t *bd) static int switch_to_bank1(void) { - u8 data; - int ret; + u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03; + int ret, bus_num = 0; - i2c_set_bus_num(0); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, chip_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + /* + * -------------------------------------------------------------------- + * |bus |I2C address| Device | Notes | + * -------------------------------------------------------------------- + * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General | + * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output| + * | | | KW41GPIO) - NXP | (GPIO) expansion for the | + * | | | PCAL9555AHF | I2C bus | + * ----- -------------------------------------------------------------- + * - mount three IO expander(PCAL9555AHF) on I2C1 + * + * PCAL9555A device address + * slave address + * -------------------------------------- + * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W | + * -------------------------------------- + * | fixed | hardware selectable| + * + * Output port 1(Pinter register bits = 0x03) + * + * P1_[7~0] = 0xf4 + * P1_0 <---> CFG_MUX_QSPI_S0 + * P1_1 <---> CFG_MUX_QSPI_S1 + * CFG_MUX_QSPI_S[1:0] = 0b00 + * + * QSPI chip-select demultiplexer select + * --------------------------------------------------------------------- + * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values + * --------------------------------------------------------------------- + * 0 | 0 |CS routed to SPI memory bank1(default) + * --------------------------------------------------------------------- + * 0 | 1 |CS routed to SPI memory bank2 + * --------------------------------------------------------------------- + * + */ + ret = dm_i2c_write(dev, offset_addr, &data, 1); +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); + ret = i2c_write(chip_addr, offset_addr, 1, &data, 1); +#endif - data = 0xf4; - ret = i2c_write(0x24, 0x3, 1, &data, 1); if (ret) { printf("i2c write error to chip : %u, addr : %u, data : %u\n", - 0x24, 0x3, data); + chip_addr, offset_addr, data); } return ret; @@ -250,25 +330,45 @@ static int switch_to_bank1(void) static int switch_to_bank2(void) { - u8 data; - int ret; + u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3}; + u8 chip_addr = 0x24; + int ret, i, bus_num = 0; - i2c_set_bus_num(0); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; - data = 0xfc; - ret = i2c_write(0x24, 0x7, 1, &data, 1); + ret = i2c_get_chip_for_busnum(bus_num, chip_addr, + 1, &dev); if (ret) { - printf("i2c write error to chip : %u, addr : %u, data : %u\n", - 0x24, 0x7, data); - goto err; + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; } +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); +#endif - data = 0xf5; - ret = i2c_write(0x24, 0x3, 1, &data, 1); - if (ret) { - printf("i2c write error to chip : %u, addr : %u, data : %u\n", - 0x24, 0x3, data); + /* + * 1th step: config port 1 + * - the port 1 pin is enabled as an output + * 2th step: output port 1 + * - P1_[7:0] output 0xf5, + * then CFG_MUX_QSPI_S[1:0] equal to 0b01, + * CS routed to SPI memory bank2 + */ + for (i = 0; i < sizeof(data); i++) { +#if defined(CONFIG_DM_I2C) + ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1); +#else /* Non DM I2C support - will be removed */ + ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1); +#endif + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + chip_addr, offset_addr[i], data[i]); + goto err; + } } + err: return ret; } diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c index c4eac5e302..b648a7872b 100644 --- a/board/freescale/ls1021aqds/dcu.c +++ b/board/freescale/ls1021aqds/dcu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * * FSL DCU Framebuffer driver */ @@ -15,11 +16,23 @@ DECLARE_GLOBAL_DATA_PTR; -static int select_i2c_ch_pca9547(u8 ch) +static int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -51,6 +64,28 @@ int platform_dcu_init(struct fb_info *fbinfo, u8 ch; /* Mux I2C3+I2C4 as HSYNC+VSYNC */ +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + /* QIXIS device mount on I2C1 bus*/ + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + 0); + return ret; + } + ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1); + if (ret) { + printf("Error: failed to read I2C @%02x\n", + CONFIG_SYS_I2C_QIXIS_ADDR); + return ret; + } + ch &= 0x1F; + ch |= 0xA0; + ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1); + +#else ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, 1, &ch, 1); if (ret) { @@ -62,6 +97,7 @@ int platform_dcu_init(struct fb_info *fbinfo, ch |= 0xA0; ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, 1, &ch, 1); +#endif if (ret) { printf("Error: failed to write I2C @%02x\n", CONFIG_SYS_I2C_QIXIS_ADDR); @@ -76,10 +112,14 @@ int platform_dcu_init(struct fb_info *fbinfo, pixval = 1000000000 / dcu_fb_videomode->pixclock; pixval *= 1000; +#ifndef CONFIG_DM_I2C i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); - select_i2c_ch_pca9547(I2C_MUX_CH_CH7301); +#endif + select_i2c_ch_pca9547(I2C_MUX_CH_CH7301, + CONFIG_SYS_I2C_DVI_BUS_NUM); diu_set_dvi_encoder(pixval); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, + CONFIG_SYS_I2C_DVI_BUS_NUM); } else { return 0; } diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index b7f8f1d578..1ae822e510 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include <common.h> @@ -139,11 +140,23 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -158,8 +171,10 @@ int dram_init(void) * When resuming from deep sleep, the I2C channel may not be * in the default channel. So, switch to the default channel * before accessing DDR SPD. + * + * PCA9547(0x77) mount on I2C1 bus */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return fsl_initdram(); } @@ -408,7 +423,7 @@ int board_init(void) erratum_a009942_check_cpo(); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 497dce5f0f..d1ff7b8ba6 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include <common.h> @@ -447,14 +448,37 @@ void board_init_f(ulong dummy) /* program the regulator (MC34VR500) to support deep sleep */ void ls1twr_program_regulator(void) { - unsigned int i2c_bus; u8 i2c_device_id; #define LS1TWR_I2C_BUS_MC34VR500 1 #define MC34VR500_ADDR 0x8 #define MC34VR500_DEVICEID 0x4 #define MC34VR500_DEVICEID_MASK 0x0f +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + LS1TWR_I2C_BUS_MC34VR500); + return; + } + i2c_device_id = dm_i2c_reg_read(dev, 0x0) & + MC34VR500_DEVICEID_MASK; + if (i2c_device_id != MC34VR500_DEVICEID) { + printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); + return; + } + dm_i2c_reg_write(dev, 0x31, 0x4); + dm_i2c_reg_write(dev, 0x4d, 0x4); + dm_i2c_reg_write(dev, 0x6d, 0x38); + dm_i2c_reg_write(dev, 0x6f, 0x37); + dm_i2c_reg_write(dev, 0x71, 0x30); +#else + unsigned int i2c_bus; i2c_bus = i2c_get_bus_num(); i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & @@ -471,6 +495,7 @@ void ls1twr_program_regulator(void) i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); i2c_set_bus_num(i2c_bus); +#endif } #endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 6555b5ad3a..103b0cc659 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -306,6 +306,8 @@ int checkboard(void) if (src == BOOT_SOURCE_SD_MMC) { puts("SD\n"); + } else if (src == BOOT_SOURCE_SD_MMC2) { + puts("eMMC\n"); } else { sw = QIXIS_READ(brdcfg[0]); sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index bbf931329c..31a37e9675 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -7,6 +7,8 @@ CONFIG_DRAM_CLK=576 CONFIG_MACPWR="PA17" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_USB1_VBUS_PIN="PH23" +CONFIG_USB2_VBUS_PIN="PH23" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y @@ -21,6 +23,4 @@ CONFIG_AXP_ELDO3_VOLT=1200 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_USB1_VBUS_PIN="PH23" -CONFIG_USB2_VBUS_PIN="PH23" CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index d5eee0fdfa..12fe9895ed 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -90,7 +90,8 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y CONFIG_FAT_WRITE=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 1c21747b4d..64f7fffd0d 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -69,5 +69,6 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 0d31d733a8..12542b2f89 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -66,5 +66,6 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index a0ebf2ab2b..4a3918cc04 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -67,5 +67,6 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index b1334a2861..792d46f514 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -68,5 +68,6 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index 654974e47d..9b028783a1 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 CONFIG_MMC0_CD_PIN="PH13" +CONFIG_USB1_VBUS_PIN="PH23" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y @@ -12,12 +13,11 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y +CONFIG_RGMII=y +CONFIG_SUN8I_EMAC=y CONFIG_AXP_DLDO4_VOLT=2500 CONFIG_AXP_ELDO3_VOLT=1200 CONFIG_SCSI=y -CONFIG_SUN8I_EMAC=y -CONFIG_RGMII=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_USB1_VBUS_PIN="PH23" CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/bcm968360bg_ram_defconfig b/configs/bcm968360bg_ram_defconfig index 4a4c1fd1c7..bc3134ff29 100644 --- a/configs/bcm968360bg_ram_defconfig +++ b/configs/bcm968360bg_ram_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_BCM68360=y CONFIG_SYS_TEXT_BASE=0x10000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_BCM968360BG=y CONFIG_ENV_VARS_UBOOT_CONFIG=y @@ -26,7 +27,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set CONFIG_BLK=y CONFIG_CLK=y -CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y CONFIG_LED_BCM6858=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index 3f744913ca..9f88023836 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -8,8 +8,8 @@ CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_ENV_OFFSET=0x300000 CONFIG_DM_GPIO=y CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_ADDR=0xEFFFFF0 +CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_DEBUG_UART=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 73e81ac4f0..1ee4a2fd3a 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -6,9 +6,10 @@ CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c CONFIG_TARGET_BK4R1=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg" @@ -41,7 +42,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_VYBRID_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig index 0fce6e5a70..f94ea28376 100644 --- a/configs/brppt2_defconfig +++ b/configs/brppt2_defconfig @@ -13,10 +13,10 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x20000 CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y # CONFIG_CMD_BMODE is not set diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 07ba6b9a3e..a0b1c8d87e 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -91,8 +91,7 @@ CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 5892044487..7ba0c9566a 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -96,8 +96,7 @@ CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_CONSOLE_TRUETYPE=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index c8bcda007c..46e1c183a2 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -96,8 +96,7 @@ CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 3b8a68e619..34cf727abc 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -91,8 +91,7 @@ CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_CONSOLE_TRUETYPE=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index e33236904a..c9005a7d07 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -84,8 +84,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index d76d58dd4f..82f71ecf7c 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -88,7 +88,8 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y CONFIG_FAT_WRITE=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index a0511eafea..e434a77400 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -83,8 +83,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 88a0dd57e2..814667adf9 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -78,8 +78,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 56e993dd10..cf3e4e0beb 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -66,8 +66,7 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDEO_TEGRA20=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index f24a0dc749..91afabe543 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -91,7 +91,8 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 0353c6d03f..3b46a4bdaa 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -12,9 +12,9 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_DM_GPIO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y -CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_AHCI=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index a1156f6617..163fb52e56 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -15,11 +15,12 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x120000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0x00908000 @@ -78,7 +79,6 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_OFFSET_REDUND=0x130000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 CONFIG_SYS_I2C_MXC=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 70b4378db8..cbed7a3f3b 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_DRACO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SPL_FS_FAT=y @@ -64,7 +65,6 @@ CONFIG_ENV_OFFSET_REDUND=0x2E0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_DFU_NAND=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 3d543f7adc..5d9dd88204 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_ETAMIN=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SPL_FS_FAT=y @@ -65,7 +66,6 @@ CONFIG_ENV_OFFSET_REDUND=0xB80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_DFU_NAND=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 912ea95223..b5ba75cc6e 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -97,9 +97,6 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_DISPLAY=y CONFIG_LCD=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 178f67b4dd..350189fc63 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -78,8 +78,7 @@ CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 14da0c56e9..431daf357b 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -53,8 +53,7 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 2c730efd29..0907b0d4bb 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -80,8 +80,7 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig index c3cf40eb08..0704f70e05 100644 --- a/configs/gardena-smart-gateway-mt7688-ram_defconfig +++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig @@ -3,9 +3,9 @@ CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0xA0000 +CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c CONFIG_ARCH_MTMIPS=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index cb30884fd4..99389995a0 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -3,9 +3,9 @@ CONFIG_SYS_TEXT_BASE=0x9c000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0xA0000 +CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c CONFIG_ARCH_MTMIPS=y CONFIG_BOOT_ROM=y CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index ea7d2f4686..44b412118c 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -193,9 +193,6 @@ CONFIG_TPM_ATMEL_TWI=y CONFIG_TPM_AUTH_SESSIONS=y # CONFIG_TPM_V2 is not set CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_DISPLAY=y CONFIG_LOGICORE_DP_TX=y CONFIG_OSD=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 37bcf061ea..33579ce8c2 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -10,8 +10,9 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0xC0000 CONFIG_DM_GPIO=y -CONFIG_NR_DRAM_BANKS=1 +CONFIG_BOOTCOUNT_BOOTLIMIT=10 CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000 +CONFIG_NR_DRAM_BANKS=1 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -48,7 +49,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_EXT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=10 CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5" CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y @@ -77,7 +77,8 @@ CONFIG_MXC_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y CONFIG_WATCHDOG_TIMEOUT_MSECS=6000 diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index 048afed65a..a5d51ce610 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -40,6 +40,5 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP32 is not set CONFIG_CMD_DHRYSTONE=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 11800dadae..197add3945 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -55,7 +55,6 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDEO_TEGRA20=y CONFIG_CONSOLE_SCROLL_LINES=10 diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index 43a927f539..ebc6194578 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -4,9 +4,9 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_HIGHBANK=y CONFIG_SYS_TEXT_BASE=0x00008000 CONFIG_ENV_SIZE=0x2000 +CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c CONFIG_NR_DRAM_BANKS=0 CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index 418390a22c..6d62022ec9 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -56,6 +56,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index e58da91893..a0baab14d1 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -57,6 +57,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index a924815059..e82a06e429 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -8,10 +8,11 @@ CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024 CONFIG_DEBUG_UART_BASE=0x021f0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_LIBDISK_SUPPORT=y @@ -55,7 +56,6 @@ CONFIG_OF_LIST="imx6q-icore imx6dl-icore" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y @@ -72,7 +72,8 @@ CONFIG_DEBUG_UART_MXC=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index e58da91893..a0baab14d1 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -57,6 +57,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 8355abbaa7..f53f1ede7f 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -8,6 +8,7 @@ CONFIG_SOC_K3_J721E=y CONFIG_TARGET_J721E_A72_EVM=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_DM_GPIO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y @@ -43,8 +44,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPT=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y @@ -91,7 +92,6 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_TI_SCI_PROTOCOL=y -CONFIG_DM_GPIO=y CONFIG_DA8XX_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index c1f2bf3c71..2470037f18 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_IDENT_STRING="\nKeymile Kirkwood 128M16" CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16" CONFIG_MISC_INIT_R=y @@ -38,7 +39,6 @@ CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index f5f1ad0daa..283b117a28 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_IDENT_STRING="\nKeymile Kirkwood" CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD" CONFIG_MISC_INIT_R=y @@ -38,7 +39,6 @@ CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index a6050f1d55..1fa0312d08 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -7,6 +7,7 @@ CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_KM_FPGA_CONFIG=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_IDENT_STRING="\nKeymile Kirkwood PCI" CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI" CONFIG_MISC_INIT_R=y @@ -39,7 +40,6 @@ CONFIG_ENV_OFFSET_REDUND=0x2000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig index 79a73fdb5a..6b85928ff6 100644 --- a/configs/kmcoge4_defconfig +++ b/configs/kmcoge4_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xfff40000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020 CONFIG_MPC85xx=y CONFIG_TARGET_KMP204X=y @@ -45,7 +46,6 @@ CONFIG_ENV_OFFSET_REDUND=0x110000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 7622565969..363099212e 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_KM_DEF_NETDEV="eth1" CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y @@ -186,7 +187,6 @@ CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index 6a7d32dd01..f712193b0d 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -10,6 +10,7 @@ CONFIG_KM_PIGGY4_88E6352=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_IDENT_STRING="\nKeymile COGE5UN" CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN" CONFIG_MISC_INIT_R=y @@ -42,7 +43,6 @@ CONFIG_ENV_OFFSET_REDUND=0xD0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index abf44f3d25..97c75dc68c 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_KM_DEF_NETDEV="eth2" CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y @@ -149,7 +150,6 @@ CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index fd521e960b..b5167e736e 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -10,6 +10,7 @@ CONFIG_KM_PIGGY4_88E6352=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0xC0000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_IDENT_STRING="\nKeymile NUSA" CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA" CONFIG_MISC_INIT_R=y @@ -42,7 +43,6 @@ CONFIG_ENV_OFFSET_REDUND=0xD0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index ab66d5662b..4b0f0e7521 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y @@ -168,7 +169,6 @@ CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index f24055757c..2e8c2d32f2 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y @@ -148,7 +149,6 @@ CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmsuse2_defconfig b/configs/kmsuse2_defconfig index e6726ebd0c..442e15ef7b 100644 --- a/configs/kmsuse2_defconfig +++ b/configs/kmsuse2_defconfig @@ -9,8 +9,9 @@ CONFIG_KM_FPGA_FORCE_CONFIG=y CONFIG_KM_FPGA_NO_RESET=y CONFIG_KM_ENV_IS_IN_SPI_NOR=y CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xC0000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_IDENT_STRING="\nABB SUSE2" CONFIG_SYS_EXTRA_OPTIONS="KM_SUSE2" CONFIG_MISC_INIT_R=y @@ -43,13 +44,12 @@ CONFIG_ENV_OFFSET_REDUND=0xD0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y CONFIG_MVGBE=y CONFIG_MII=y CONFIG_SYS_NS16550=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 65798297cb..dc09d238ec 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_KM_DEF_NETDEV="eth1" CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y @@ -150,7 +151,6 @@ CONFIG_ENV_ADDR=0xF0100000 CONFIG_ENV_ADDR_REDUND=0xF0120000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 2b7813783e..6159425bba 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y @@ -168,7 +169,6 @@ CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index 92c7d6fb0c..09b87c54d5 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -70,7 +70,8 @@ CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_DWC3=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_MESON=y CONFIG_VIDEO_DT_SIMPLEFB=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index bec15cd766..7c257b33b3 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -52,7 +52,8 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_DWC3=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_MESON=y CONFIG_VIDEO_DT_SIMPLEFB=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index be8b2e51ef..b1cf8ef7c5 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 @@ -35,6 +36,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -43,6 +45,7 @@ CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index 0a035a83fa..a978580952 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x500000 +CONFIG_DM_GPIO=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -35,6 +36,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -43,6 +45,7 @@ CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 7258d47dfc..11d0cee39a 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 @@ -32,6 +33,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y @@ -44,6 +46,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 85f87ba238..2818bdf0d2 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x500000 +CONFIG_DM_GPIO=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -32,6 +33,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_DM_I2C=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y @@ -44,6 +46,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index a3c6fe7d8f..cc5ee71638 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1012AFRWY=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NXP_ESBC=y CONFIG_ENV_SIZE=0x10000 +CONFIG_DM_GPIO=y CONFIG_FSL_LS_PPA=y CONFIG_NR_DRAM_BANKS=2 CONFIG_AHCI=y @@ -30,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -43,6 +45,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index eb732a1964..bee093694c 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x1D0000 +CONFIG_DM_GPIO=y CONFIG_FSL_LS_PPA=y CONFIG_NR_DRAM_BANKS=2 CONFIG_AHCI=y @@ -34,6 +35,7 @@ CONFIG_ENV_ADDR=0x401D0000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -46,6 +48,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 92d85994a3..a983c30042 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -4,6 +4,7 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NXP_ESBC=y CONFIG_ENV_SIZE=0x10000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y @@ -30,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -43,6 +45,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y @@ -53,5 +56,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y -CONFIG_CMD_SETEXPR=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index ca732c4b48..f8ca4483f2 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x1D0000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y @@ -34,6 +35,7 @@ CONFIG_ENV_ADDR=0x401D0000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -47,6 +49,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y @@ -55,8 +58,8 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y -CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_RTL8152=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 1d6bcc51c4..fd4fba5cc4 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 @@ -34,7 +35,6 @@ CONFIG_DEFAULT_SPI_BUS=1 CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -49,6 +49,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -65,6 +66,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index f525544ccf..23dea4ce23 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -4,6 +4,7 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NXP_ESBC=y CONFIG_ENV_SIZE=0x40000 +CONFIG_DM_GPIO=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -30,15 +31,14 @@ CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_DEFAULT_SPI_BUS=1 CONFIG_CMD_USB=y -CONFIG_CMD_SETEXPR=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -55,6 +55,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 656de21adb..974cedc0f4 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x500000 +CONFIG_DM_GPIO=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -34,7 +35,6 @@ CONFIG_DEFAULT_SPI_BUS=1 CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -49,6 +49,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -65,6 +66,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index a2d8e9dd6d..5ad4e0d6bd 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1012ARDB=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_NXP_ESBC=y CONFIG_ENV_SIZE=0x40000 +CONFIG_DM_GPIO=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 @@ -31,9 +32,11 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -45,6 +48,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index d734e2ed6f..98057a944c 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 @@ -33,9 +34,11 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x40300000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -49,6 +52,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index fa137834ff..2f48da82e4 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -4,6 +4,7 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_NXP_ESBC=y CONFIG_ENV_SIZE=0x40000 +CONFIG_DM_GPIO=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -27,13 +28,14 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y -CONFIG_CMD_SETEXPR=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y @@ -45,6 +47,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 3f0e19d792..4dec4181b7 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x500000 +CONFIG_DM_GPIO=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -33,9 +34,11 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x40500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_FSL_ESDHC=y @@ -50,6 +53,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index c3376e106c..7ba0c47a5b 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" @@ -22,6 +23,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index a7a340076f..4cd4c319b5 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021AIOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 +CONFIG_DM_GPIO=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y @@ -28,6 +29,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 70f7053ed0..d29b6ebc74 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_FIT=y @@ -39,6 +40,7 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index eaa26ceee9..62c3bccbfe 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_FIT=y @@ -40,6 +41,7 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index c7c701de9e..a940c74de7 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x140000 +CONFIG_DM_GPIO=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 @@ -57,6 +58,7 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 3f99035553..73fd8c2cc8 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NXP_ESBC=y CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_F is not set @@ -38,6 +39,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 6fe62a713d..b75b0c08d2 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_FIT=y @@ -40,6 +41,7 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index ad222eb9ef..83daeb1374 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_FIT=y @@ -41,6 +42,7 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index e643242b14..497ee52d59 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_FIT=y @@ -42,6 +43,7 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 2c28b9efba..3d12ceb27f 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y @@ -55,6 +56,7 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index d8065e7242..22be8e6e91 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y @@ -54,6 +55,7 @@ CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index c30e89d959..b7e754cf19 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -29,6 +30,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 3d3d743c87..5245540978 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 @@ -40,6 +41,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index dbd9d0e070..9af9912600 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_NXP_ESBC=y CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -32,6 +33,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_DM=y CONFIG_SATA_CEVA=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 7fcd4de2d0..3e63933ea2 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -34,6 +35,7 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 0303d49045..01b5205df4 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -36,6 +37,7 @@ CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 50b7eedcc2..0fcd675f3a 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -38,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index c909f40bd1..2f2a9fff37 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NXP_ESBC=y CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y @@ -48,6 +49,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_DM_I2C=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 97e6a4747f..7a98c26bcc 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 @@ -49,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 3ad24eae2f..110631da12 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x300000 +CONFIG_DM_GPIO=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 @@ -49,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 019ecfd9b1..c5f0bd85da 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -69,6 +69,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y @@ -76,6 +77,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_RSA=y -CONFIG_CMD_SETEXPR=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 435f36446b..7085be77fe 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -75,6 +75,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 27a9ab131f..6fa14af6af 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -66,6 +66,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y @@ -73,6 +74,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_RSA=y -CONFIG_CMD_SETEXPR=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index eff794e2cd..3ef5520969 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -73,6 +73,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 4ba5a8dd95..0ece698350 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -62,5 +62,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_CMD_SETEXPR=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 83bfca078b..94ca502f3b 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -56,4 +56,3 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_CMD_SETEXPR=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 96efee6736..2c258785d1 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -56,9 +56,9 @@ CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y -CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_RTL8152=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index c50e525fd3..e173747923 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -61,4 +61,3 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_CMD_SETEXPR=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 43a123625c..1dde0ae73b 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -54,4 +54,3 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_CMD_SETEXPR=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 3d5d8a2e04..0086039e52 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y -CONFIG_CMD_SETEXPR=y CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 829dcc6052..a7908e95b5 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -72,8 +72,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y +CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y -CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_RTL8152=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 5ba20e5f64..c0d0a99c8a 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -28,7 +28,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y -CONFIG_CMD_SETEXPR=y CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 698954366e..7c3b82700d 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -56,8 +56,8 @@ CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y @@ -73,4 +73,3 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_CMD_SETEXPR=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index c9a6ffb284..449b3cbcf1 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -57,8 +57,8 @@ CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 5517a7d8e9..d1fffb399e 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -52,8 +52,8 @@ CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y @@ -68,4 +68,3 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -CONFIG_CMD_SETEXPR=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index b998cb64dd..93f3e200c0 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -56,8 +56,8 @@ CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 21a8989db0..0a8d9ecea7 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -10,10 +10,11 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DM_GPIO=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C # CONFIG_CMD_BMODE is not set CONFIG_SPL_TEXT_BASE=0x70008000 CONFIG_FIT=y @@ -64,7 +65,6 @@ CONFIG_ENV_OFFSET_REDUND=0x180000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 CONFIG_DM_MMC=y CONFIG_FSL_ESDHC_IMX=y @@ -92,7 +92,8 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index 3bba587430..bfca54d857 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -42,6 +42,5 @@ CONFIG_USB_EHCI_TEGRA=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDEO_TEGRA20=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index de6f01f2cc..edba9da31b 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -76,8 +76,7 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index 50219dd446..943c1b2577 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -21,9 +21,9 @@ CONFIG_CLK=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x56000000 CONFIG_FASTBOOT_BUF_SIZE=0x1E00000 -CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y CONFIG_DM_MMC=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index 3b24baf6ed..4e03532942 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -35,6 +35,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_MX5=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 6cfb5266bd..b0d3f50aad 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -7,8 +7,9 @@ CONFIG_SYS_VPD_EEPROM_I2C_BUS=2 CONFIG_SYS_VPD_EEPROM_SIZE=1024 CONFIG_ENV_SIZE=0x2800 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_NR_DRAM_BANKS=2 +CONFIG_BOOTCOUNT_BOOTLIMIT=10 CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000 +CONFIG_NR_DRAM_BANKS=2 CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg" @@ -39,7 +40,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_EXT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=10 CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5" CONFIG_DM_MMC=y CONFIG_FSL_ESDHC_IMX=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 3846bf39b2..723e1c32d8 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -93,6 +93,7 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index a5a34ec32e..c6cd1e3cb1 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -100,6 +100,7 @@ CONFIG_CI_UDC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 4fd311d2fb..60484e24f6 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -70,7 +70,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 5f3658ffbd..c02f71f566 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -73,7 +73,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index f14f82b9a6..295ab891bb 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -75,7 +75,8 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y CONFIG_FAT_WRITE=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 34a48af5ba..8c08ee6233 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -84,7 +84,8 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_TEGRA124=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index bb674de66b..57fe10ed33 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -100,7 +100,8 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index bdc116d969..bcf74580b5 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -3,8 +3,8 @@ CONFIG_ARCH_SUNXI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y -CONFIG_MACPWR="PD14" CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y +CONFIG_MACPWR="PD14" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index e57d1408ae..8536c64fc0 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -37,7 +37,6 @@ CONFIG_USB_EHCI_TEGRA=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDEO_TEGRA20=y CONFIG_CONSOLE_SCROLL_LINES=10 diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 099ab7c873..6efca9b08e 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -73,8 +73,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_HOST_ETHER=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index ba7a0eb40c..216ec90efa 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -72,8 +72,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_HOST_ETHER=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 44a23146bb..8a1e15de65 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -77,7 +77,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index e79513daa9..830fddeee9 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -77,7 +77,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index fe2e3e8ea4..2836edc64b 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -70,8 +70,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 3a0df428b0..545acd2c89 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -77,7 +77,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 44a23146bb..8a1e15de65 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -77,7 +77,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 9e2f629343..c9e6abc7d2 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -77,7 +77,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index 571bed0dcf..44fef1100a 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -59,6 +59,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP32 is not set CONFIG_LCD=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index c4952d1a62..8ec432a5d0 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -57,6 +57,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP32 is not set CONFIG_LCD=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index a76e0e4469..d4cf8453f5 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -85,8 +85,7 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 6d120a7e29..7253341460 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_MPUCLK=720 CONFIG_TARGET_PXM2=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SPL_FS_FAT=y @@ -64,7 +65,6 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_DFU_NAND=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 665f8b3c1a..273c71289f 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_RASTABAN=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SPL_FS_FAT=y @@ -64,7 +65,6 @@ CONFIG_ENV_OFFSET_REDUND=0x2E0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_DFU_NAND=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 8204e00253..81e94fe943 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -30,6 +30,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y @@ -40,9 +41,8 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYSRESET=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 95e943f1d5..bb12b32a21 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -75,8 +75,7 @@ CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index de0cf5d6a2..8074e4665a 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -34,6 +34,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y @@ -44,9 +45,8 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_SYSRESET=y -CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 75c6c9c447..cecc16cbfc 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -38,7 +38,8 @@ CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 4e8204ef88..762a72a574 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -38,7 +38,8 @@ CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index d50953287c..5ca31648f9 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -41,7 +41,8 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_LAN78XX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index e76821450f..4f0332023d 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -41,7 +41,8 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_LAN78XX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index c0c0955131..51d5a717d5 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -41,7 +41,8 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_LAN78XX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 00f80f71ad..72cda5d949 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -12,6 +12,7 @@ CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_FS_UUID=y @@ -20,15 +21,28 @@ CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DFU_MMC=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y +CONFIG_DM_ETH=y +CONFIG_BCMGENET=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 8cf1bb81ff..6d148dab07 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -12,6 +12,7 @@ CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_FS_UUID=y @@ -20,15 +21,28 @@ CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DFU_MMC=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y +CONFIG_DM_ETH=y +CONFIG_BCMGENET=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 10fbe0db92..fea86be8b0 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -24,8 +24,8 @@ CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y -CONFIG_PHYLIB=y CONFIG_DM_ETH=y +CONFIG_BCMGENET=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set @@ -37,7 +37,8 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_LAN78XX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 2f4c7da6dc..dbbc818e14 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -38,7 +38,8 @@ CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 514e91b6ef..22572ef09d 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_MPUCLK=600 CONFIG_TARGET_RUT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SPL_FS_FAT=y @@ -65,7 +66,6 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_DFU_NAND=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 1f8d29176e..b64064856f 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -94,7 +94,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 20b25cd338..dfd8047041 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -94,7 +94,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index 2fcb10b4db..6c2336369c 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -102,7 +102,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 7337c184c5..a22dcf1a01 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -98,7 +98,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index f95710db66..31a7edfb43 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -109,7 +109,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index e7f789ae3a..64b23db492 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -93,7 +93,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 5033945118..12571ff517 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -95,7 +95,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig index 66b3b2d455..e64f1b6b83 100644 --- a/configs/sama5d2_xplained_qspiflash_defconfig +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -94,7 +94,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 12c76d9823..6da9bd3c56 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -95,7 +95,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index 4a0c68122e..fec1595755 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -63,5 +63,6 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index 2eb0a37f18..dc0609421d 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -64,6 +64,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_FAT_WRITE=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 1d0604afca..024ac65b12 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_SPI=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_FAT_WRITE=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 2d8a6a2c65..a5fc191918 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -96,7 +96,4 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_ATMEL_HLCD=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 6c522f4a53..fd06a93d98 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -93,8 +93,5 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_ATMEL_HLCD=y CONFIG_FAT_WRITE=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index c4e5c37068..6c7cc2e16b 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -94,8 +94,5 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_ATMEL_HLCD=y CONFIG_FAT_WRITE=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index e4f25c9130..bca732c911 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -89,7 +89,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index cf32e0f340..88483d11bf 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -86,7 +86,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 45d2a7bba4..d833962c3b 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -90,7 +90,8 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y CONFIG_W1=y CONFIG_W1_GPIO=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 11adfe2093..b0486edd80 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -87,5 +87,6 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 4951357d13..7bda22eada 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -86,5 +86,6 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index d24550ae52..13243a796c 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -87,5 +87,6 @@ CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_ATMEL_HLCD=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 7b80033c3b..941b1fd2c7 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -189,7 +189,6 @@ CONFIG_DM_USB=y CONFIG_USB_EMUL=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 790dcb0592..7b02b8de7c 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -210,7 +210,6 @@ CONFIG_DM_USB=y CONFIG_USB_EMUL=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 2c90639ecb..0049da3d48 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -168,7 +168,6 @@ CONFIG_DM_USB=y CONFIG_USB_EMUL=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index b78115af61..f55692c2b5 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -188,7 +188,6 @@ CONFIG_DM_USB=y CONFIG_USB_EMUL=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 2cb8db96a7..9c285b96aa 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -48,8 +48,7 @@ CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDEO_TEGRA20=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_AES=y diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig index b58bf8bb22..79777e3262 100644 --- a/configs/sei510_defconfig +++ b/configs/sei510_defconfig @@ -72,7 +72,8 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xfada CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_MESON=y CONFIG_VIDEO_DT_SIMPLEFB=y diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig index 614abd1c20..bfcba34336 100644 --- a/configs/sei610_defconfig +++ b/configs/sei610_defconfig @@ -72,7 +72,8 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xfada CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_MESON=y CONFIG_VIDEO_DT_SIMPLEFB=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index e37423fc28..81dc72938c 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -84,8 +84,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 9b77bf5bec..ec1abbcc3d 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -4,8 +4,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DM_GPIO=y -CONFIG_TARGET_SOCFPGA_IS1=y CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 +CONFIG_TARGET_SOCFPGA_IS1=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index ad816b0be0..1883d1f9ac 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -4,8 +4,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_DM_GPIO=y -CONFIG_TARGET_SOCFPGA_SR1500=y CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 +CONFIG_TARGET_SOCFPGA_SR1500=y CONFIG_SPL_TEXT_BASE=0xFFFF0000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index c7286d5519..26db40ffe3 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -58,4 +58,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 5b2801beda..0dcae8199a 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -96,4 +96,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -# CONFIG_SPL_WDT is not set +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index a5f6778eb7..ceddbf8f7e 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -85,8 +85,7 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_DISPLAY=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index cfc5b619b1..c9e22563a3 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -55,9 +55,6 @@ CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_VIDEO_STM32=y CONFIG_VIDEO_STM32_MAX_XRES=480 CONFIG_VIDEO_STM32_MAX_YRES=640 diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 1ec1bc9d31..19a7493d00 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -55,9 +55,6 @@ CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_STM32=y CONFIG_VIDEO_STM32_DSI=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 59d04f09a2..f691306800 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -137,9 +137,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y CONFIG_VIDEO_STM32=y diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig index 633822a0d6..521b24e2cb 100644 --- a/configs/stm32mp15_optee_defconfig +++ b/configs/stm32mp15_optee_defconfig @@ -121,9 +121,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y CONFIG_VIDEO_STM32=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index c5f18174df..c8b328d01a 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -120,9 +120,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y -CONFIG_VIDEO_BPP8=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y CONFIG_VIDEO_STM32=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index bcc255bf02..9908ca04a6 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y @@ -169,7 +170,6 @@ CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index be20e6980b..fd7b1b6267 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -42,6 +42,5 @@ CONFIG_USB_EHCI_TEGRA=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDEO_TEGRA20=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index 512862c38b..fb12e841cb 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -81,5 +81,6 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_VIDEO_MVEBU=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index c606cdff9c..0d813999dd 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_MPUCLK=300 CONFIG_TARGET_THUBAN=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SPL_FS_FAT=y @@ -64,7 +65,6 @@ CONFIG_ENV_OFFSET_REDUND=0x2E0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_DFU_NAND=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 6215aa2d61..ab192cf4e4 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -81,8 +81,7 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig index b83c8f6916..3a351301a1 100644 --- a/configs/tqma6s_wru4_mmc_defconfig +++ b/configs/tqma6s_wru4_mmc_defconfig @@ -6,8 +6,8 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_TQMA6S=y CONFIG_WRU4=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000 +CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index f109eccd52..93ff5f0361 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y @@ -148,7 +149,6 @@ CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 01392cc49f..2e27dc6b3f 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y @@ -170,7 +171,6 @@ CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 59b6141059..bb94e23ad5 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -41,7 +41,6 @@ CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_VIDEO_TEGRA20=y CONFIG_CONSOLE_SCROLL_LINES=10 diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index acf0207858..9e6a0c1e7a 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -77,8 +77,7 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y -CONFIG_VIDEO_BPP32=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 0843fccf1d..82e517b90f 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -72,6 +72,7 @@ CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_BPP16=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig index cb37f5254b..bbe392339c 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -10,9 +10,9 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y -CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8 CONFIG_IDENT_STRING="-SPEAr" CONFIG_SPL_TEXT_BASE=0xd2800b00 CONFIG_BOOTDELAY=3 diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index a3b914fdfc..3ea5a7c0c0 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -434,8 +434,10 @@ static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl, debug("Configuring DRAMODT\n"); writel(cfg->dram_odt, &sdr_ctrl->dram_odt); - debug("Configuring EXTRATIME1\n"); - writel(cfg->extratime1, &sdr_ctrl->extratime1); + if (dram_is_ddr(3)) { + debug("Configuring EXTRATIME1\n"); + writel(cfg->extratime1, &sdr_ctrl->extratime1); + } } /** diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index b85b56efe5..35bda9b34c 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -7,6 +7,7 @@ #include <asm/io.h> #include <asm/arch/sdram.h> #include <errno.h> +#include <hang.h> #include "sequencer.h" static const struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = @@ -54,6 +55,21 @@ static const struct socfpga_sdr_ctrl *sdr_ctrl = #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \ ((non_skip_value) & seq->skip_delay_mask) +bool dram_is_ddr(const u8 ddr) +{ + const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); + const u8 type = (cfg->ctrl_cfg >> SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) & + SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK; + + if (ddr == 2 && type == 1) /* DDR2 */ + return true; + + if (ddr == 3 && type == 2) /* DDR3 */ + return true; + + return false; +} + static void set_failing_group_stage(struct socfpga_sdrseq *seq, u32 group, u32 stage, u32 substage) { @@ -164,6 +180,8 @@ static void set_rank_and_odt_mask(struct socfpga_sdrseq *seq, */ odt_mask_0 = 0x3 & ~(1 << rank); odt_mask_1 = 0x3; + if (dram_is_ddr(2)) + odt_mask_1 &= ~(1 << rank); } else { /* * - Single-Slot , Dual-Rank (2 CS per DIMM) @@ -176,10 +194,11 @@ static void set_rank_and_odt_mask(struct socfpga_sdrseq *seq, } break; case 4: /* 4 Ranks */ - /* Read: + /* + * DDR3 Read, DDR2 Read/Write: * ----------+-----------------------+ * | ODT | - * Read From +-----------------------+ + * +-----------------------+ * Rank | 3 | 2 | 1 | 0 | * ----------+-----+-----+-----+-----+ * 0 | 0 | 1 | 0 | 0 | @@ -188,7 +207,7 @@ static void set_rank_and_odt_mask(struct socfpga_sdrseq *seq, * 3 | 0 | 0 | 1 | 0 | * ----------+-----+-----+-----+-----+ * - * Write: + * DDR3 Write: * ----------+-----------------------+ * | ODT | * Write To +-----------------------+ @@ -203,19 +222,31 @@ static void set_rank_and_odt_mask(struct socfpga_sdrseq *seq, switch (rank) { case 0: odt_mask_0 = 0x4; - odt_mask_1 = 0x5; + if (dram_is_ddr(2)) + odt_mask_1 = 0x4; + else if (dram_is_ddr(3)) + odt_mask_1 = 0x5; break; case 1: odt_mask_0 = 0x8; - odt_mask_1 = 0xA; + if (dram_is_ddr(2)) + odt_mask_1 = 0x8; + else if (dram_is_ddr(3)) + odt_mask_1 = 0xA; break; case 2: odt_mask_0 = 0x1; - odt_mask_1 = 0x5; + if (dram_is_ddr(2)) + odt_mask_1 = 0x1; + else if (dram_is_ddr(3)) + odt_mask_1 = 0x5; break; case 3: odt_mask_0 = 0x2; - odt_mask_1 = 0xA; + if (dram_is_ddr(2)) + odt_mask_1 = 0x2; + else if (dram_is_ddr(3)) + odt_mask_1 = 0xA; break; } break; @@ -839,6 +870,12 @@ static void delay_for_n_mem_clocks(struct socfpga_sdrseq *seq, debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks); } +static void delay_for_n_ns(struct socfpga_sdrseq *seq, const u32 ns) +{ + delay_for_n_mem_clocks(seq, (ns * seq->misccfg->afi_clk_freq * + seq->misccfg->afi_rate_ratio) / 1000); +} + /** * rw_mgr_mem_init_load_regs() - Load instruction registers * @cntr0: Counter 0 value @@ -872,14 +909,59 @@ static void rw_mgr_mem_init_load_regs(struct socfpga_sdrseq *seq, } /** - * rw_mgr_mem_load_user() - Load user calibration values + * rw_mgr_mem_load_user_ddr2() - Load user calibration values for DDR2 + * @handoff: Indicate whether this is initialization or handoff phase + * + * Load user calibration values and optionally precharge the banks. + */ +static void rw_mgr_mem_load_user_ddr2(struct socfpga_sdrseq *seq, + const int handoff) +{ + u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | + RW_MGR_RUN_SINGLE_GROUP_OFFSET; + u32 r; + + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) { + /* set rank */ + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF); + + /* precharge all banks ... */ + writel(seq->rwcfg->precharge_all, grpaddr); + + writel(seq->rwcfg->emr2, grpaddr); + writel(seq->rwcfg->emr3, grpaddr); + writel(seq->rwcfg->emr, grpaddr); + + if (handoff) { + writel(seq->rwcfg->mr_user, grpaddr); + continue; + } + + writel(seq->rwcfg->mr_dll_reset, grpaddr); + + writel(seq->rwcfg->precharge_all, grpaddr); + + writel(seq->rwcfg->refresh, grpaddr); + delay_for_n_ns(seq, 200); + writel(seq->rwcfg->refresh, grpaddr); + delay_for_n_ns(seq, 200); + + writel(seq->rwcfg->mr_calib, grpaddr); + writel(/*seq->rwcfg->*/0x0b, grpaddr); // EMR_OCD_ENABLE + writel(seq->rwcfg->emr, grpaddr); + delay_for_n_mem_clocks(seq, 200); + } +} + +/** + * rw_mgr_mem_load_user_ddr3() - Load user calibration values * @fin1: Final instruction 1 * @fin2: Final instruction 2 * @precharge: If 1, precharge the banks at the end * * Load user calibration values and optionally precharge the banks. */ -static void rw_mgr_mem_load_user(struct socfpga_sdrseq *seq, +static void rw_mgr_mem_load_user_ddr3(struct socfpga_sdrseq *seq, const u32 fin1, const u32 fin2, const int precharge) { @@ -936,6 +1018,25 @@ static void rw_mgr_mem_load_user(struct socfpga_sdrseq *seq, } /** + * rw_mgr_mem_load_user() - Load user calibration values + * @fin1: Final instruction 1 + * @fin2: Final instruction 2 + * @precharge: If 1, precharge the banks at the end + * + * Load user calibration values and optionally precharge the banks. + */ +static void rw_mgr_mem_load_user(struct socfpga_sdrseq *seq, + const u32 fin1, const u32 fin2, + const int precharge) +{ + if (dram_is_ddr(2)) + rw_mgr_mem_load_user_ddr2(seq, precharge); + else if (dram_is_ddr(3)) + rw_mgr_mem_load_user_ddr3(seq, fin1, fin2, precharge); + else + hang(); +} +/** * rw_mgr_mem_initialize() - Initialize RW Manager * * Initialize RW Manager. @@ -945,8 +1046,10 @@ static void rw_mgr_mem_initialize(struct socfpga_sdrseq *seq) debug("%s:%d\n", __func__, __LINE__); /* The reset / cke part of initialization is broadcasted to all ranks */ - writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS | - RW_MGR_SET_CS_AND_ODT_MASK_OFFSET); + if (dram_is_ddr(3)) { + writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS | + RW_MGR_SET_CS_AND_ODT_MASK_OFFSET); + } /* * Here's how you load register for a loop @@ -979,29 +1082,38 @@ static void rw_mgr_mem_initialize(struct socfpga_sdrseq *seq) /* Indicate that memory is stable. */ writel(1, &phy_mgr_cfg->reset_mem_stbl); - /* - * transition the RESET to high - * Wait for 500us - */ + if (dram_is_ddr(2)) { + writel(seq->rwcfg->nop, SDR_PHYGRP_RWMGRGRP_ADDRESS | + RW_MGR_RUN_SINGLE_GROUP_OFFSET); - /* - * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles - * If a and b are the number of iteration in 2 nested loops - * it takes the following number of cycles to complete the operation - * number_of_cycles = ((2 + n) * a + 2) * b - * where n is the number of instruction in the inner loop - * One possible solution is n = 2 , a = 131 , b = 256 => a = 83, - * b = FF - */ - rw_mgr_mem_init_load_regs(seq, seq->misccfg->treset_cntr0_val, - seq->misccfg->treset_cntr1_val, - seq->misccfg->treset_cntr2_val, - seq->rwcfg->init_reset_1_cke_0); + /* Bring up clock enable. */ - /* Bring up clock enable. */ + /* tXRP < 400 ck cycles */ + delay_for_n_ns(seq, 400); + } else if (dram_is_ddr(3)) { + /* + * transition the RESET to high + * Wait for 500us + */ + + /* + * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles + * If a and b are the number of iteration in 2 nested loops + * it takes the following number of cycles to complete the + * operation number_of_cycles = ((2 + n) * a + 2) * b + * where n is the number of instruction in the inner loop + * One possible solution is + * n = 2 , a = 131 , b = 256 => a = 83, b = FF + */ + rw_mgr_mem_init_load_regs(seq, seq->misccfg->treset_cntr0_val, + seq->misccfg->treset_cntr1_val, + seq->misccfg->treset_cntr2_val, + seq->rwcfg->init_reset_1_cke_0); + /* Bring up clock enable. */ - /* tXRP < 250 ck cycles */ - delay_for_n_mem_clocks(seq, 250); + /* tXRP < 250 ck cycles */ + delay_for_n_mem_clocks(seq, 250); + } rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_dll_reset_mirr, seq->rwcfg->mrs0_dll_reset, 0); @@ -3769,16 +3881,26 @@ static void initialize_tracking(struct socfpga_sdrseq *seq) &sdr_reg_file->delays); /* mux delay */ - writel((seq->rwcfg->idle << 24) | (seq->rwcfg->activate_1 << 16) | - (seq->rwcfg->sgle_read << 8) | (seq->rwcfg->precharge_all << 0), - &sdr_reg_file->trk_rw_mgr_addr); + if (dram_is_ddr(2)) { + writel(0, &sdr_reg_file->trk_rw_mgr_addr); + } else if (dram_is_ddr(3)) { + writel((seq->rwcfg->idle << 24) | + (seq->rwcfg->activate_1 << 16) | + (seq->rwcfg->sgle_read << 8) | + (seq->rwcfg->precharge_all << 0), + &sdr_reg_file->trk_rw_mgr_addr); + } writel(seq->rwcfg->mem_if_read_dqs_width, &sdr_reg_file->trk_read_dqs_width); /* trefi [7:0] */ - writel((seq->rwcfg->refresh_all << 24) | (1000 << 0), - &sdr_reg_file->trk_rfsh); + if (dram_is_ddr(2)) { + writel(1000 << 0, &sdr_reg_file->trk_rfsh); + } else if (dram_is_ddr(3)) { + writel((seq->rwcfg->refresh_all << 24) | (1000 << 0), + &sdr_reg_file->trk_rfsh); + } } int sdram_calibration_full(struct socfpga_sdr *sdr) diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index 4a03c3fdf9..c72a683ffe 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -279,5 +279,6 @@ struct socfpga_sdrseq { }; int sdram_calibration_full(struct socfpga_sdr *sdr); +bool dram_is_ddr(const u8 ddr); #endif /* _SEQUENCER_H_ */ diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 5b551f6ae1..0d495a785b 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -17,7 +17,7 @@ static unsigned char *dfu_file_buf; static u64 dfu_file_buf_len; -static long dfu_file_buf_filled; +static u64 dfu_file_buf_offset; static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len) @@ -91,22 +91,8 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, return 0; } -static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len) -{ - if (dfu_file_buf_len + *len > CONFIG_SYS_DFU_MAX_FILE_SIZE) { - dfu_file_buf_len = 0; - return -EINVAL; - } - - /* Add to the current buffer. */ - memcpy(dfu_file_buf + dfu_file_buf_len, buf, *len); - dfu_file_buf_len += *len; - - return 0; -} - static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, - void *buf, u64 *len) + u64 offset, void *buf, u64 *len) { char dev_part_str[8]; int ret; @@ -137,7 +123,7 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, switch (op) { case DFU_OP_READ: - ret = fs_read(dfu->name, (size_t)buf, 0, 0, &size); + ret = fs_read(dfu->name, (size_t)buf, offset, *len, &size); if (ret) { puts("dfu: fs_read error!\n"); return ret; @@ -145,7 +131,7 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, *len = size; break; case DFU_OP_WRITE: - ret = fs_write(dfu->name, (size_t)buf, 0, *len, &size); + ret = fs_write(dfu->name, (size_t)buf, offset, *len, &size); if (ret) { puts("dfu: fs_write error!\n"); return ret; @@ -166,6 +152,43 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, return ret; } +static int mmc_file_buf_write(struct dfu_entity *dfu, u64 offset, void *buf, long *len) +{ + int ret = 0; + + if (offset == 0) { + dfu_file_buf_len = 0; + dfu_file_buf_offset = 0; + } + + /* Add to the current buffer. */ + if (dfu_file_buf_len + *len > CONFIG_SYS_DFU_MAX_FILE_SIZE) + *len = CONFIG_SYS_DFU_MAX_FILE_SIZE - dfu_file_buf_len; + memcpy(dfu_file_buf + dfu_file_buf_len, buf, *len); + dfu_file_buf_len += *len; + + if (dfu_file_buf_len == CONFIG_SYS_DFU_MAX_FILE_SIZE) { + ret = mmc_file_op(DFU_OP_WRITE, dfu, dfu_file_buf_offset, + dfu_file_buf, &dfu_file_buf_len); + dfu_file_buf_offset += dfu_file_buf_len; + dfu_file_buf_len = 0; + } + + return ret; +} + +static int mmc_file_buf_write_finish(struct dfu_entity *dfu) +{ + int ret = mmc_file_op(DFU_OP_WRITE, dfu, dfu_file_buf_offset, + dfu_file_buf, &dfu_file_buf_len); + + /* Now that we're done */ + dfu_file_buf_len = 0; + dfu_file_buf_offset = 0; + + return ret; +} + int dfu_write_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, long *len) { @@ -177,7 +200,7 @@ int dfu_write_medium_mmc(struct dfu_entity *dfu, break; case DFU_FS_FAT: case DFU_FS_EXT4: - ret = mmc_file_buffer(dfu, buf, len); + ret = mmc_file_buf_write(dfu, offset, buf, len); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -193,11 +216,7 @@ int dfu_flush_medium_mmc(struct dfu_entity *dfu) if (dfu->layout != DFU_RAW_ADDR) { /* Do stuff here. */ - ret = mmc_file_op(DFU_OP_WRITE, dfu, dfu_file_buf, - &dfu_file_buf_len); - - /* Now that we're done */ - dfu_file_buf_len = 0; + ret = mmc_file_buf_write_finish(dfu); } return ret; @@ -213,12 +232,9 @@ int dfu_get_medium_size_mmc(struct dfu_entity *dfu, u64 *size) return 0; case DFU_FS_FAT: case DFU_FS_EXT4: - dfu_file_buf_filled = -1; - ret = mmc_file_op(DFU_OP_SIZE, dfu, NULL, size); + ret = mmc_file_op(DFU_OP_SIZE, dfu, 0, NULL, size); if (ret < 0) return ret; - if (*size > CONFIG_SYS_DFU_MAX_FILE_SIZE) - return -1; return 0; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -227,23 +243,28 @@ int dfu_get_medium_size_mmc(struct dfu_entity *dfu, u64 *size) } } -static int mmc_file_unbuffer(struct dfu_entity *dfu, u64 offset, void *buf, + +static int mmc_file_buf_read(struct dfu_entity *dfu, u64 offset, void *buf, long *len) { int ret; - u64 file_len; - if (dfu_file_buf_filled == -1) { - ret = mmc_file_op(DFU_OP_READ, dfu, dfu_file_buf, &file_len); + if (offset == 0 || offset >= dfu_file_buf_offset + dfu_file_buf_len || + offset + *len < dfu_file_buf_offset) { + u64 file_len = CONFIG_SYS_DFU_MAX_FILE_SIZE; + + ret = mmc_file_op(DFU_OP_READ, dfu, offset, dfu_file_buf, + &file_len); if (ret < 0) return ret; - dfu_file_buf_filled = file_len; + dfu_file_buf_len = file_len; + dfu_file_buf_offset = offset; } - if (offset + *len > dfu_file_buf_filled) + if (offset + *len > dfu_file_buf_offset + dfu_file_buf_len) return -EINVAL; /* Add to the current buffer. */ - memcpy(buf, dfu_file_buf + offset, *len); + memcpy(buf, dfu_file_buf + offset - dfu_file_buf_offset, *len); return 0; } @@ -259,7 +280,7 @@ int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, break; case DFU_FS_FAT: case DFU_FS_EXT4: - ret = mmc_file_unbuffer(dfu, offset, buf, len); + ret = mmc_file_buf_read(dfu, offset, buf, len); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 786b5a2226..6b7ce985b3 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -1049,5 +1049,6 @@ U_BOOT_DRIVER(i2c_mxc) = { .probe = mxc_i2c_probe, .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus), .ops = &mxc_i2c_ops, + .flags = DM_FLAG_PRE_RELOC, }; #endif diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 01d087f229..4d1013c984 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -136,6 +136,13 @@ config BCM6368_ETH help This driver supports the BCM6368 Ethernet MAC. +config BCMGENET + bool "BCMGENET V5 support" + depends on DM_ETH + select PHYLIB + help + This driver supports the BCMGENET Ethernet MAC. + config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" depends on DM_ETH diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 30991834ec..6e0a68834d 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o +obj-$(CONFIG_BCMGENET) += bcmgenet.o obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o obj-$(CONFIG_DRIVER_AX88180) += ax88180.o obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c new file mode 100644 index 0000000000..8f4848aec6 --- /dev/null +++ b/drivers/net/bcmgenet.c @@ -0,0 +1,729 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com> + * + * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4) + * This driver is based on the Linux driver: + * drivers/net/ethernet/broadcom/genet/bcmgenet.c + * which is: Copyright (c) 2014-2017 Broadcom + * + * The hardware supports multiple queues (16 priority queues and one + * default queue), both for RX and TX. There are 256 DMA descriptors (both + * for TX and RX), and they live in MMIO registers. The hardware allows + * assigning descriptor ranges to queues, but we choose the most simple setup: + * All 256 descriptors are assigned to the default queue (#16). + * Also the Linux driver supports multiple generations of the MAC, whereas + * we only support v5, as used in the Raspberry Pi 4. + */ + +#include <asm/io.h> +#include <clk.h> +#include <cpu_func.h> +#include <dm.h> +#include <fdt_support.h> +#include <linux/err.h> +#include <malloc.h> +#include <miiphy.h> +#include <net.h> +#include <dm/of_access.h> +#include <dm/ofnode.h> +#include <linux/iopoll.h> +#include <linux/sizes.h> +#include <asm/dma-mapping.h> +#include <wait_bit.h> + +/* Register definitions derived from Linux source */ +#define SYS_REV_CTRL 0x00 + +#define SYS_PORT_CTRL 0x04 +#define PORT_MODE_EXT_GPHY 3 + +#define GENET_SYS_OFF 0x0000 +#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) +#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) + +#define GENET_EXT_OFF 0x0080 +#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) +#define RGMII_LINK BIT(4) +#define OOB_DISABLE BIT(5) +#define RGMII_MODE_EN BIT(6) +#define ID_MODE_DIS BIT(16) + +#define GENET_RBUF_OFF 0x0300 +#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) +#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) +#define RBUF_ALIGN_2B BIT(1) + +#define GENET_UMAC_OFF 0x0800 +#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) +#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) +#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) +#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) +#define UMAC_CMD (GENET_UMAC_OFF + 0x008) +#define MDIO_CMD (GENET_UMAC_OFF + 0x614) +#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) +#define MDIO_START_BUSY BIT(29) +#define MDIO_READ_FAIL BIT(28) +#define MDIO_RD (2 << 26) +#define MDIO_WR BIT(26) +#define MDIO_PMD_SHIFT 21 +#define MDIO_PMD_MASK 0x1f +#define MDIO_REG_SHIFT 16 +#define MDIO_REG_MASK 0x1f + +#define CMD_TX_EN BIT(0) +#define CMD_RX_EN BIT(1) +#define UMAC_SPEED_10 0 +#define UMAC_SPEED_100 1 +#define UMAC_SPEED_1000 2 +#define UMAC_SPEED_2500 3 +#define CMD_SPEED_SHIFT 2 +#define CMD_SPEED_MASK 3 +#define CMD_SW_RESET BIT(13) +#define CMD_LCL_LOOP_EN BIT(15) +#define CMD_TX_EN BIT(0) +#define CMD_RX_EN BIT(1) + +#define MIB_RESET_RX BIT(0) +#define MIB_RESET_RUNT BIT(1) +#define MIB_RESET_TX BIT(2) + +/* total number of Buffer Descriptors, same for Rx/Tx */ +#define TOTAL_DESCS 256 +#define RX_DESCS TOTAL_DESCS +#define TX_DESCS TOTAL_DESCS + +#define DEFAULT_Q 0x10 + +/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. + * 1536 is multiple of 256 bytes + */ +#define ENET_BRCM_TAG_LEN 6 +#define ENET_PAD 8 +#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ + VLAN_HLEN + ENET_BRCM_TAG_LEN + \ + ETH_FCS_LEN + ENET_PAD) + +/* Tx/Rx Dma Descriptor common bits */ +#define DMA_EN BIT(0) +#define DMA_RING_BUF_EN_SHIFT 0x01 +#define DMA_RING_BUF_EN_MASK 0xffff +#define DMA_BUFLENGTH_MASK 0x0fff +#define DMA_BUFLENGTH_SHIFT 16 +#define DMA_RING_SIZE_SHIFT 16 +#define DMA_OWN 0x8000 +#define DMA_EOP 0x4000 +#define DMA_SOP 0x2000 +#define DMA_WRAP 0x1000 +#define DMA_MAX_BURST_LENGTH 0x8 +/* Tx specific DMA descriptor bits */ +#define DMA_TX_UNDERRUN 0x0200 +#define DMA_TX_APPEND_CRC 0x0040 +#define DMA_TX_OW_CRC 0x0020 +#define DMA_TX_DO_CSUM 0x0010 +#define DMA_TX_QTAG_SHIFT 7 + +/* DMA rings size */ +#define DMA_RING_SIZE 0x40 +#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) + +/* DMA descriptor */ +#define DMA_DESC_LENGTH_STATUS 0x00 +#define DMA_DESC_ADDRESS_LO 0x04 +#define DMA_DESC_ADDRESS_HI 0x08 +#define DMA_DESC_SIZE 12 + +#define GENET_RX_OFF 0x2000 +#define GENET_RDMA_REG_OFF \ + (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) +#define GENET_TX_OFF 0x4000 +#define GENET_TDMA_REG_OFF \ + (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) + +#define DMA_FC_THRESH_HI (RX_DESCS >> 4) +#define DMA_FC_THRESH_LO 5 +#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ + DMA_FC_THRESH_HI) + +#define DMA_XOFF_THRESHOLD_SHIFT 16 + +#define TDMA_RING_REG_BASE \ + (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) +#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) +#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) +#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) +#define DMA_RING_BUF_SIZE 0x10 +#define DMA_START_ADDR 0x14 +#define DMA_END_ADDR 0x1c +#define DMA_MBUF_DONE_THRESH 0x24 +#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) +#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) + +#define RDMA_RING_REG_BASE \ + (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) +#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) +#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) +#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) +#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) +#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) + +#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) +#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) +#define DMA_RING_CFG 0x00 +#define DMA_CTRL 0x04 +#define DMA_SCB_BURST_SIZE 0x0c + +#define RX_BUF_LENGTH 2048 +#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) +#define RX_BUF_OFFSET 2 + +struct bcmgenet_eth_priv { + char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + void *mac_reg; + void *tx_desc_base; + void *rx_desc_base; + int tx_index; + int rx_index; + int c_index; + int phyaddr; + u32 interface; + u32 speed; + struct phy_device *phydev; + struct mii_dev *bus; +}; + +static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv) +{ + u32 reg; + + reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL); + reg |= BIT(1); + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); + udelay(10); + + reg &= ~BIT(1); + writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); + udelay(10); + + writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); + udelay(10); + + writel(0, priv->mac_reg + UMAC_CMD); + + writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); + udelay(2); + writel(0, priv->mac_reg + UMAC_CMD); + + /* clear tx/rx counter */ + writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, + priv->mac_reg + UMAC_MIB_CTRL); + writel(0, priv->mac_reg + UMAC_MIB_CTRL); + + writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN); + + /* init rx registers, enable ip header optimization */ + reg = readl(priv->mac_reg + RBUF_CTRL); + reg |= RBUF_ALIGN_2B; + writel(reg, (priv->mac_reg + RBUF_CTRL)); + + writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL)); +} + +static int bcmgenet_gmac_write_hwaddr(struct udevice *dev) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + uchar *addr = pdata->enetaddr; + u32 reg; + + reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; + writel_relaxed(reg, priv->mac_reg + UMAC_MAC0); + + reg = addr[4] << 8 | addr[5]; + writel_relaxed(reg, priv->mac_reg + UMAC_MAC1); + + return 0; +} + +static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv) +{ + clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN); + clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN); + + writel(1, priv->mac_reg + UMAC_TX_FLUSH); + udelay(10); + writel(0, priv->mac_reg + UMAC_TX_FLUSH); +} + +static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv) +{ + u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; + + writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL); + + setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl); +} + +static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE; + u32 len_stat = length << DMA_BUFLENGTH_SHIFT; + ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN); + u32 prod_index, cons; + u32 tries = 100; + + prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX); + + /* There is actually no reason for the rounding here, but the ARMv7 + * implementation of flush_dcache_range() checks for aligned + * boundaries of the flushed range. + * Adjust them here to pass that check and avoid misleading messages. + */ + flush_dcache_range(packet_aligned, + packet_aligned + roundup(length, ARCH_DMA_MINALIGN)); + + len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; + len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; + + /* Set-up packet for transmission */ + writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO)); + writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI)); + writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS)); + + /* Increment index and start transmission */ + if (++priv->tx_index >= TX_DESCS) + priv->tx_index = 0; + + prod_index++; + + /* Start Transmisson */ + writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX); + + do { + cons = readl(priv->mac_reg + TDMA_CONS_INDEX); + } while ((cons & 0xffff) < prod_index && --tries); + if (!tries) + return -ETIMEDOUT; + + return 0; +} + +/* Check whether all cache lines affected by an invalidate are within + * the buffer, to make sure we don't accidentally lose unrelated dirty + * data stored nearby. + * Alignment of the buffer start address will be checked in the implementation + * of invalidate_dcache_range(). + */ +static void invalidate_dcache_check(unsigned long addr, size_t size, + size_t buffer_size) +{ + size_t inval_size = roundup(size, ARCH_DMA_MINALIGN); + + if (unlikely(inval_size > buffer_size)) + printf("WARNING: Cache invalidate area exceeds buffer size\n"); + + invalidate_dcache_range(addr, addr + inval_size); +} + +static int bcmgenet_gmac_eth_recv(struct udevice *dev, + int flags, uchar **packetp) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; + u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX); + u32 length, addr; + + if (prod_index == priv->c_index) + return -EAGAIN; + + length = readl(desc_base + DMA_DESC_LENGTH_STATUS); + length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; + addr = readl(desc_base + DMA_DESC_ADDRESS_LO); + + invalidate_dcache_check(addr, length, RX_BUF_LENGTH); + + /* To cater for the IP header alignment the hardware does. + * This would actually not be needed if we don't program + * RBUF_ALIGN_2B + */ + *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET; + + return length - RX_BUF_OFFSET; +} + +static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + + /* Tell the MAC we have consumed that last receive buffer. */ + priv->c_index = (priv->c_index + 1) & 0xFFFF; + writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); + + /* Forward our descriptor pointer, wrapping around if needed. */ + if (++priv->rx_index >= RX_DESCS) + priv->rx_index = 0; + + return 0; +} + +static void rx_descs_init(struct bcmgenet_eth_priv *priv) +{ + char *rxbuffs = &priv->rxbuffer[0]; + u32 len_stat, i; + void *desc_base = priv->rx_desc_base; + + priv->c_index = 0; + + len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; + + for (i = 0; i < RX_DESCS; i++) { + writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO); + writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), + desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI); + writel(len_stat, + desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS); + } +} + +static void rx_ring_init(struct bcmgenet_eth_priv *priv) +{ + writel(DMA_MAX_BURST_LENGTH, + priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE); + + writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR); + writel(0x0, priv->mac_reg + RDMA_READ_PTR); + writel(0x0, priv->mac_reg + RDMA_WRITE_PTR); + writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1, + priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR); + + writel(0x0, priv->mac_reg + RDMA_PROD_INDEX); + writel(0x0, priv->mac_reg + RDMA_CONS_INDEX); + writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, + priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); + writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH); + writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG); +} + +static void tx_ring_init(struct bcmgenet_eth_priv *priv) +{ + writel(DMA_MAX_BURST_LENGTH, + priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE); + + writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR); + writel(0x0, priv->mac_reg + TDMA_READ_PTR); + writel(0x0, priv->mac_reg + TDMA_WRITE_PTR); + writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1, + priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR); + writel(0x0, priv->mac_reg + TDMA_PROD_INDEX); + writel(0x0, priv->mac_reg + TDMA_CONS_INDEX); + writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH); + writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD); + writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, + priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); + + writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG); +} + +static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv) +{ + struct phy_device *phy_dev = priv->phydev; + u32 speed; + + switch (phy_dev->speed) { + case SPEED_1000: + speed = UMAC_SPEED_1000; + break; + case SPEED_100: + speed = UMAC_SPEED_100; + break; + case SPEED_10: + speed = UMAC_SPEED_10; + break; + default: + printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed); + return -EINVAL; + } + + clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, + RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); + + writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); + + return 0; +} + +static int bcmgenet_gmac_eth_start(struct udevice *dev) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + int ret; + + priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF; + priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF; + priv->tx_index = 0x0; + priv->rx_index = 0x0; + + bcmgenet_umac_reset(priv); + + bcmgenet_gmac_write_hwaddr(dev); + + /* Disable RX/TX DMA and flush TX queues */ + bcmgenet_disable_dma(priv); + + rx_ring_init(priv); + rx_descs_init(priv); + + tx_ring_init(priv); + + /* Enable RX/TX DMA */ + bcmgenet_enable_dma(priv); + + /* read PHY properties over the wire from generic PHY set-up */ + ret = phy_startup(priv->phydev); + if (ret) { + printf("bcmgenet: PHY startup failed: %d\n", ret); + return ret; + } + + /* Update MAC registers based on PHY property */ + ret = bcmgenet_adjust_link(priv); + if (ret) { + printf("bcmgenet: adjust PHY link failed: %d\n", ret); + return ret; + } + + /* Enable Rx/Tx */ + setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); + + return 0; +} + +static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev) +{ + struct phy_device *phydev; + int ret; + + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); + if (!phydev) + return -ENODEV; + + phydev->supported &= PHY_GBIT_FEATURES; + if (priv->speed) { + ret = phy_set_supported(priv->phydev, priv->speed); + if (ret) + return ret; + } + phydev->advertising = phydev->supported; + + phy_connect_dev(phydev, dev); + + priv->phydev = phydev; + phy_config(priv->phydev); + + return 0; +} + +static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv) +{ + setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY); +} + +static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) +{ + struct udevice *dev = bus->priv; + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + u32 val; + + /* Prepare the read operation */ + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | + (reg << MDIO_REG_SHIFT) | (0xffff & value); + writel_relaxed(val, priv->mac_reg + MDIO_CMD); + + /* Start MDIO transaction */ + bcmgenet_mdio_start(priv); + + return wait_for_bit_32(priv->mac_reg + MDIO_CMD, + MDIO_START_BUSY, false, 20, true); +} + +static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct udevice *dev = bus->priv; + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + u32 val; + int ret; + + /* Prepare the read operation */ + val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); + writel_relaxed(val, priv->mac_reg + MDIO_CMD); + + /* Start MDIO transaction */ + bcmgenet_mdio_start(priv); + + ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD, + MDIO_START_BUSY, false, 20, true); + if (ret) + return ret; + + val = readl_relaxed(priv->mac_reg + MDIO_CMD); + + return val & 0xffff; +} + +static int bcmgenet_mdio_init(const char *name, struct udevice *priv) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + debug("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = bcmgenet_mdio_read; + bus->write = bcmgenet_mdio_write; + snprintf(bus->name, sizeof(bus->name), name); + bus->priv = (void *)priv; + + return mdio_register(bus); +} + +/* We only support RGMII (as used on the RPi4). */ +static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv) +{ + phy_interface_t phy_mode = priv->interface; + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL); + break; + default: + printf("unknown phy mode: %d\n", priv->interface); + return -EINVAL; + } + + return 0; +} + +static int bcmgenet_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + ofnode mdio_node; + const char *name; + u32 reg; + int ret; + u8 major; + + priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE); + priv->interface = pdata->phy_interface; + priv->speed = pdata->max_speed; + + /* Read GENET HW version */ + reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL); + major = (reg >> 24) & 0x0f; + if (major != 6) { + if (major == 5) + major = 4; + else if (major == 0) + major = 1; + + printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f); + return -ENODEV; + } + + ret = bcmgenet_interface_set(priv); + if (ret) + return ret; + + writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL); + udelay(10); + /* disable MAC while updating its registers */ + writel(0, priv->mac_reg + UMAC_CMD); + /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ + writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); + + mdio_node = dev_read_first_subnode(dev); + name = ofnode_get_name(mdio_node); + + ret = bcmgenet_mdio_init(name, dev); + if (ret) + return ret; + + priv->bus = miiphy_get_dev_by_name(name); + + return bcmgenet_phy_init(priv, dev); +} + +static void bcmgenet_gmac_eth_stop(struct udevice *dev) +{ + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + + clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); + + bcmgenet_disable_dma(priv); +} + +static const struct eth_ops bcmgenet_gmac_eth_ops = { + .start = bcmgenet_gmac_eth_start, + .write_hwaddr = bcmgenet_gmac_write_hwaddr, + .send = bcmgenet_gmac_eth_send, + .recv = bcmgenet_gmac_eth_recv, + .free_pkt = bcmgenet_gmac_free_pkt, + .stop = bcmgenet_gmac_eth_stop, +}; + +static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args phy_node; + const char *phy_mode; + int ret; + + pdata->iobase = dev_read_addr(dev); + + /* Get phy mode from DT */ + pdata->phy_interface = -1; + phy_mode = dev_read_string(dev, "phy-mode"); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phy_node); + if (!ret) { + ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr); + ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed); + } + + return 0; +} + +/* The BCM2711 implementation has a limited burst length compared to a generic + * GENETv5 version, but we go with that shorter value (8) in both cases, for + * the sake of simplicity. + */ +static const struct udevice_id bcmgenet_eth_ids[] = { + {.compatible = "brcm,genet-v5"}, + {.compatible = "brcm,bcm2711-genet-v5"}, + {} +}; + +U_BOOT_DRIVER(eth_bcmgenet) = { + .name = "eth_bcmgenet", + .id = UCLASS_ETH, + .of_match = bcmgenet_eth_ids, + .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata, + .probe = bcmgenet_eth_probe, + .ops = &bcmgenet_gmac_eth_ops, + .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 93ec9cfdb6..105ce94c71 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -18,6 +18,7 @@ #include <dm/of_access.h> #include <env.h> #include <reset-uclass.h> +#include <wait_bit.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> @@ -80,7 +81,10 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) int offset = id % (reg_width * BITS_PER_BYTE); clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); - return 0; + + return wait_for_bit_le32(data->modrst_base + (bank * BANK_INCREMENT), + BIT(offset), + false, 500, false); } static int socfpga_reset_request(struct reset_ctl *reset_ctl) diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index a839d6cc98..84f2b231c2 100644 --- a/drivers/rtc/pcf8563.c +++ b/drivers/rtc/pcf8563.c @@ -12,9 +12,11 @@ #include <common.h> #include <command.h> +#include <dm.h> #include <rtc.h> #include <i2c.h> +#if !CONFIG_IS_ENABLED(DM_RTC) static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); @@ -115,3 +117,108 @@ static void rtc_write (uchar reg, uchar val) { i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } +#else +static int pcf8563_rtc_get(struct udevice *dev, struct rtc_time *tmp) +{ + int rel = 0; + uchar sec, min, hour, mday, wday, mon_cent, year; + + sec = dm_i2c_reg_read(dev, 0x02); + min = dm_i2c_reg_read(dev, 0x03); + hour = dm_i2c_reg_read(dev, 0x04); + mday = dm_i2c_reg_read(dev, 0x05); + wday = dm_i2c_reg_read(dev, 0x06); + mon_cent = dm_i2c_reg_read(dev, 0x07); + year = dm_i2c_reg_read(dev, 0x08); + + debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x ", + year, mon_cent, mday, wday); + debug("hr: %02x min: %02x sec: %02x\n", + hour, min, sec); + debug("Alarms: wday: %02x day: %02x hour: %02x min: %02x\n", + dm_i2c_reg_read(dev, 0x0C), + dm_i2c_reg_read(dev, 0x0B), + dm_i2c_reg_read(dev, 0x0A), + dm_i2c_reg_read(dev, 0x09)); + + if (sec & 0x80) { + puts("### Warning: RTC Low Voltage - date/time not reliable\n"); + rel = -1; + } + + tmp->tm_sec = bcd2bin(sec & 0x7F); + tmp->tm_min = bcd2bin(min & 0x7F); + tmp->tm_hour = bcd2bin(hour & 0x3F); + tmp->tm_mday = bcd2bin(mday & 0x3F); + tmp->tm_mon = bcd2bin(mon_cent & 0x1F); + tmp->tm_year = bcd2bin(year) + ((mon_cent & 0x80) ? 1900 : 2000); + tmp->tm_wday = bcd2bin(wday & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + + debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; +} + +static int pcf8563_rtc_set(struct udevice *dev, const struct rtc_time *tmp) +{ + uchar century; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + dm_i2c_reg_write(dev, 0x08, bin2bcd(tmp->tm_year % 100)); + + century = (tmp->tm_year >= 2000) ? 0 : 0x80; + dm_i2c_reg_write(dev, 0x07, bin2bcd(tmp->tm_mon) | century); + + dm_i2c_reg_write(dev, 0x06, bin2bcd(tmp->tm_wday)); + dm_i2c_reg_write(dev, 0x05, bin2bcd(tmp->tm_mday)); + dm_i2c_reg_write(dev, 0x04, bin2bcd(tmp->tm_hour)); + dm_i2c_reg_write(dev, 0x03, bin2bcd(tmp->tm_min)); + dm_i2c_reg_write(dev, 0x02, bin2bcd(tmp->tm_sec)); + + return 0; +} + +static int pcf8563_rtc_reset(struct udevice *dev) +{ + /* clear all control & status registers */ + dm_i2c_reg_write(dev, 0x00, 0x00); + dm_i2c_reg_write(dev, 0x01, 0x00); + dm_i2c_reg_write(dev, 0x0D, 0x00); + + /* clear Voltage Low bit */ + dm_i2c_reg_write(dev, 0x02, dm_i2c_reg_read(dev, 0x02) & 0x7F); + + /* reset all alarms */ + dm_i2c_reg_write(dev, 0x09, 0x00); + dm_i2c_reg_write(dev, 0x0A, 0x00); + dm_i2c_reg_write(dev, 0x0B, 0x00); + dm_i2c_reg_write(dev, 0x0C, 0x00); + + return 0; +} + +static const struct rtc_ops pcf8563_rtc_ops = { + .get = pcf8563_rtc_get, + .set = pcf8563_rtc_set, + .reset = pcf8563_rtc_reset, +}; + +static const struct udevice_id pcf8563_rtc_ids[] = { + { .compatible = "nxp,pcf8563" }, + { } +}; + +U_BOOT_DRIVER(rtc_pcf8563) = { + .name = "rtc-pcf8563", + .id = UCLASS_RTC, + .of_match = pcf8563_rtc_ids, + .ops = &pcf8563_rtc_ops, +}; +#endif diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index 35f4147840..49f342eb21 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -31,6 +31,7 @@ #include <linux/usb/otg.h> #include <linux/usb/gadget.h> +#include <phys2bus.h> #include <asm/byteorder.h> #include <asm/unaligned.h> #include <asm/io.h> @@ -1213,6 +1214,7 @@ static int dwc2_udc_otg_remove(struct udevice *dev) static const struct udevice_id dwc2_udc_otg_ids[] = { { .compatible = "snps,dwc2" }, + { .compatible = "brcm,bcm2835-usb" }, { .compatible = "st,stm32mp1-hsotg", .data = (ulong)dwc2_set_stm32mp1_hsotg_params }, {}, diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index b68c2b2686..d4fbb75cc9 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -31,7 +31,7 @@ static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev) { u32 ep_ctrl; - writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); + writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz); ep_ctrl = readl(®->in_endp[EP0_CON].diepctl); @@ -52,7 +52,7 @@ static void dwc2_udc_pre_setup(void) writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), ®->out_endp[EP0_CON].doeptsiz); - writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); + writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), ®->out_endp[EP0_CON].doepdma); ep_ctrl = readl(®->out_endp[EP0_CON].doepctl); writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl); @@ -78,7 +78,7 @@ static inline void dwc2_ep0_complete_out(void) writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), ®->out_endp[EP0_CON].doeptsiz); - writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); + writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), ®->out_endp[EP0_CON].doepdma); ep_ctrl = readl(®->out_endp[EP0_CON].doepctl); writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, @@ -116,7 +116,7 @@ static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req) (unsigned long) ep->dma_buf + ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); - writel((unsigned long) ep->dma_buf, ®->out_endp[ep_num].doepdma); + writel(phys_to_bus((unsigned long)ep->dma_buf), ®->out_endp[ep_num].doepdma); writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), ®->out_endp[ep_num].doeptsiz); writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl); @@ -164,7 +164,7 @@ static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req) while (readl(®->grstctl) & TX_FIFO_FLUSH) ; - writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma); + writel(phys_to_bus((unsigned long)ep->dma_buf), ®->in_endp[ep_num].diepdma); writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length), ®->in_endp[ep_num].dieptsiz); @@ -924,7 +924,7 @@ static int dwc2_udc_get_status(struct dwc2_udc *dev, (unsigned long) usb_ctrl + ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE)); - writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); + writel(phys_to_bus(usb_ctrl_dma_addr), ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2), ®->in_endp[EP0_CON].dieptsiz); diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 50ab3650ee..4c93369702 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -38,6 +38,7 @@ config BACKLIGHT_GPIO config VIDEO_BPP8 bool "Support 8-bit-per-pixel displays" depends on DM_VIDEO + default y help Support drawing text and bitmaps onto a 8-bit-per-pixel display. Enabling this will include code to support this display. Without @@ -47,6 +48,7 @@ config VIDEO_BPP8 config VIDEO_BPP16 bool "Support 16-bit-per-pixel displays" depends on DM_VIDEO + default y help Support drawing text and bitmaps onto a 16-bit-per-pixel display. Enabling this will include code to support this display. Without @@ -56,7 +58,7 @@ config VIDEO_BPP16 config VIDEO_BPP32 bool "Support 32-bit-per-pixel displays" depends on DM_VIDEO - default y if X86 + default y help Support drawing text and bitmaps onto a 32-bit-per-pixel display. Enabling this will include code to support this display. Without @@ -66,6 +68,7 @@ config VIDEO_BPP32 config VIDEO_ANSI bool "Support ANSI escape sequences in video console" depends on DM_VIDEO + default y help Enable ANSI escape sequence decoding for a more fully functional console. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 2b8064dfae..77354ad209 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -45,6 +45,13 @@ config ULP_WATCHDOG help Say Y here to enable i.MX7ULP watchdog driver. +config DESIGNWARE_WATCHDOG + bool "Designware watchdog timer support" + select HW_WATCHDOG if !WDT + help + Enable this to support Designware Watchdog Timer IP, present e.g. + on Altera SoCFPGA SoCs. + config WDT bool "Enable driver model for watchdog timer drivers" depends on DM diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index c668567c66..1024a04596 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -3,8 +3,11 @@ * Copyright (C) 2013 Altera Corporation <www.altera.com> */ +#include <clk.h> #include <common.h> -#include <watchdog.h> +#include <dm.h> +#include <reset.h> +#include <wdt.h> #include <asm/io.h> #include <asm/utils.h> @@ -14,49 +17,52 @@ #define DW_WDT_CR_EN_OFFSET 0x00 #define DW_WDT_CR_RMOD_OFFSET 0x01 -#define DW_WDT_CR_RMOD_VAL 0x00 #define DW_WDT_CRR_RESTART_VAL 0x76 +struct designware_wdt_priv { + void __iomem *base; + unsigned int clk_khz; +}; + /* * Set the watchdog time interval. * Counter is 32 bit. */ -static int designware_wdt_settimeout(unsigned int timeout) +static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz, + unsigned int timeout) { signed int i; /* calculate the timeout range value */ - i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16; - if (i > 15) - i = 15; - if (i < 0) - i = 0; + i = log_2_n_round_up(timeout * clk_khz) - 16; + i = clamp(i, 0, 15); + + writel(i | (i << 4), base + DW_WDT_TORR); - writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR)); return 0; } -static void designware_wdt_enable(void) +static void designware_wdt_enable(void __iomem *base) { - writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | - (0x1 << DW_WDT_CR_EN_OFFSET)), - (CONFIG_DW_WDT_BASE + DW_WDT_CR)); + writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR); } -static unsigned int designware_wdt_is_enabled(void) +static unsigned int designware_wdt_is_enabled(void __iomem *base) { - unsigned long val; - val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR)); - return val & 0x1; + return readl(base + DW_WDT_CR) & BIT(0); } -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) +static void designware_wdt_reset_common(void __iomem *base) { - if (designware_wdt_is_enabled()) + if (designware_wdt_is_enabled(base)) /* restart the watchdog counter */ - writel(DW_WDT_CRR_RESTART_VAL, - (CONFIG_DW_WDT_BASE + DW_WDT_CRR)); + writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR); +} + +#if !CONFIG_IS_ENABLED(WDT) +void hw_watchdog_reset(void) +{ + designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE); } void hw_watchdog_init(void) @@ -64,10 +70,106 @@ void hw_watchdog_init(void) /* reset to disable the watchdog */ hw_watchdog_reset(); /* set timer in miliseconds */ - designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS); + designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE, + CONFIG_DW_WDT_CLOCK_KHZ, + CONFIG_WATCHDOG_TIMEOUT_MSECS); /* enable the watchdog */ - designware_wdt_enable(); + designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE); /* reset the watchdog */ hw_watchdog_reset(); } +#else +static int designware_wdt_reset(struct udevice *dev) +{ + struct designware_wdt_priv *priv = dev_get_priv(dev); + + designware_wdt_reset_common(priv->base); + + return 0; +} + +static int designware_wdt_stop(struct udevice *dev) +{ + struct designware_wdt_priv *priv = dev_get_priv(dev); + + designware_wdt_reset(dev); + writel(0, priv->base + DW_WDT_CR); + + return 0; +} + +static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct designware_wdt_priv *priv = dev_get_priv(dev); + + designware_wdt_stop(dev); + + /* set timer in miliseconds */ + designware_wdt_settimeout(priv->base, priv->clk_khz, timeout); + + designware_wdt_enable(priv->base); + + /* reset the watchdog */ + return designware_wdt_reset(dev); +} + +static int designware_wdt_probe(struct udevice *dev) +{ + struct designware_wdt_priv *priv = dev_get_priv(dev); + __maybe_unused int ret; + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + priv->clk_khz = clk_get_rate(&clk); + if (!priv->clk_khz) + return -EINVAL; +#else + priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ; +#endif + +#if CONFIG_IS_ENABLED(DM_RESET) + struct reset_ctl_bulk resets; + + ret = reset_get_bulk(dev, &resets); + if (ret) + return ret; + + ret = reset_deassert_bulk(&resets); + if (ret) + return ret; +#endif + + /* reset to disable the watchdog */ + return designware_wdt_stop(dev); +} + +static const struct wdt_ops designware_wdt_ops = { + .start = designware_wdt_start, + .reset = designware_wdt_reset, + .stop = designware_wdt_stop, +}; + +static const struct udevice_id designware_wdt_ids[] = { + { .compatible = "snps,dw-wdt"}, + {} +}; + +U_BOOT_DRIVER(designware_wdt) = { + .name = "designware_wdt", + .id = UCLASS_WDT, + .of_match = designware_wdt_ids, + .priv_auto_alloc_size = sizeof(struct designware_wdt_priv), + .probe = designware_wdt_probe, + .ops = &designware_wdt_ops, + .flags = DM_FLAG_PRE_RELOC, +}; #endif diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 2579e2fb37..e9baa2a8b6 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -66,7 +66,12 @@ CONFIG_SYS_SCSI_MAX_LUN) /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index b419c46829..0738b243c4 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2020 NXP * Copyright 2016 Freescale Semiconductor, Inc. */ @@ -64,7 +65,7 @@ "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ - "kernelheader_addr=0x800000\0" \ + "kernelheader_addr=0x600000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 0b2d331b9b..1d218aa703 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #ifndef __CONFIG_H @@ -97,7 +98,13 @@ * I2C */ #define CONFIG_CMD_I2C + +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 8427be5adc..8bac2d2561 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #ifndef __CONFIG_H @@ -331,7 +332,12 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index bdb4273cf5..984df6249f 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 - * Copyright 2016-2018 NXP Semiconductors + * Copyright 2016-2019 NXP Semiconductors * Copyright 2019 Vladimir Oltean <olteanv@gmail.com> */ @@ -107,7 +107,12 @@ #define CONFIG_BAUDRATE 115200 /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 1919d1e14f..8e2784b14b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #ifndef __CONFIG_H @@ -209,7 +210,12 @@ /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ @@ -307,6 +313,8 @@ "kernel_size=0x2800000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ + "$othbootargs\0" \ + "othbootargs=cma=64M@0x0-0xb0000000\0" \ BOOTENV \ "boot_scripts=ls1021atwr_boot.scr\0" \ "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ @@ -367,6 +375,8 @@ "kernel_size_sd=0x14000\0" \ "kernelhdr_addr_sd=0x4000\0" \ "kernelhdr_size_sd=0x10\0" \ + "$othbootargs\0" \ + "othbootargs=cma=64M@0x0-0xb0000000\0" \ BOOTENV \ "boot_scripts=ls1021atwr_boot.scr\0" \ "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ @@ -446,6 +456,7 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#undef CONFIG_DM_I2C #else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 6543cfd868..3944f87794 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #ifndef __LS1046A_COMMON_H @@ -230,13 +230,13 @@ "fdt_addr_r=0x90000000\0" \ "ramdisk_addr_r=0xa0000000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ + "kernelheader_start=0x600000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ CONFIG_MTDPARTS_DEFAULT "\0" \ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index a5125c8f37..361c72fc8c 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2020 NXP */ #ifndef __LS1088A_QDS_H @@ -407,9 +407,9 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ - "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \ + "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \ "sf read 0xa0e00000 0xe00000 0x100000;" \ - "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \ + "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \ "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ "mcmemsize=0x70000000 \0" #else /* if !(CONFIG_NXP_ESBC) */ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index d02ad083e8..b48efcc119 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2020 NXP */ #ifndef __LS1088A_RDB_H @@ -296,19 +296,19 @@ "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ "sf read 0x80100000 0xE00000 0x100000;" \ "env exists secureboot && " \ - "sf read 0x80700000 0x700000 0x40000 && " \ - "sf read 0x80740000 0x740000 0x40000 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "sf read 0x80640000 0x640000 0x40000 && " \ + "sf read 0x80680000 0x680000 0x40000 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" #define SD_MC_INIT_CMD \ "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ "mmc read 0x80100000 0x7000 0x800;" \ "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x20 && " \ - "mmc read 0x80740000 0x3A00 0x20 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" #else #if defined(CONFIG_QSPI_BOOT) @@ -316,10 +316,10 @@ "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ "sf read 0x80100000 0xE00000 0x100000;" \ "env exists secureboot && " \ - "sf read 0x80700000 0x700000 0x40000 && " \ - "sf read 0x80740000 0x740000 0x40000 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "sf read 0x80640000 0x640000 0x40000 && " \ + "sf read 0x80680000 0x680000 0x40000 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000\0" #elif defined(CONFIG_SD_BOOT) @@ -327,10 +327,10 @@ "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ "mmc read 0x80100000 0x7000 0x800;" \ "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x20 && " \ - "mmc read 0x80740000 0x3A00 0x20 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000\0" #endif @@ -348,13 +348,13 @@ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernel_start=0x580100000\0" \ - "kernelheader_start=0x580800000\0" \ + "kernelheader_start=0x580600000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr=0x800000\0" \ + "kernelheader_addr=0x600000\0" \ "kernelheader_addr_r=0x80200000\0" \ "kernel_addr_r=0x81000000\0" \ "kernelheader_size=0x40000\0" \ @@ -417,13 +417,13 @@ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernel_start=0x580100000\0" \ "kernelheader_start=0x580800000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr=0x800000\0" \ + "kernelheader_addr=0x600000\0" \ "kernelheader_addr_r=0x80200000\0" \ "kernel_addr_r=0x81000000\0" \ "kernelheader_size=0x40000\0" \ @@ -480,8 +480,8 @@ #define QSPI_NOR_BOOTCOMMAND \ "sf read 0x80001000 0xd00000 0x100000;" \ "env exists mcinitcmd && env exists secureboot " \ - " && sf read 0x80780000 0x780000 0x100000 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && sf read 0x806C0000 0x6C0000 0x100000 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80001000;" \ "run distro_bootcmd;run qspi_bootcmd;" \ "env exists secureboot && esbc_halt;" @@ -489,8 +489,8 @@ "env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80001000 0x6800 0x800; " \ "env exists mcinitcmd && env exists secureboot " \ - " && mmc read 0x80780000 0x3C00 0x20 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80001000;" \ "run distro_bootcmd;run sd_bootcmd;" \ "env exists secureboot && esbc_halt;" @@ -500,8 +500,8 @@ #define CONFIG_BOOTCOMMAND \ "sf read 0x80001000 0xd00000 0x100000;" \ "env exists mcinitcmd && env exists secureboot " \ - " && sf read 0x80780000 0x780000 0x100000 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && sf read 0x806C0000 0x6C0000 0x100000 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80001000;" \ "run distro_bootcmd;run qspi_bootcmd;" \ "env exists secureboot && esbc_halt;" @@ -512,8 +512,8 @@ "env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80001000 0x6800 0x800; " \ "env exists mcinitcmd && env exists secureboot " \ - " && mmc read 0x80780000 0x3C00 0x20 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80001000;" \ "run distro_bootcmd;run sd_bootcmd;" \ "env exists secureboot && esbc_halt;" diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 9539e2a8db..88da69f36f 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017, 2019 NXP + * Copyright 2017, 2019-2020 NXP * Copyright 2015 Freescale Semiconductor */ @@ -349,8 +349,8 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcmemsize=0x40000000\0" \ - "mcinitcmd=esbc_validate 0x580700000;" \ - "esbc_validate 0x580740000;" \ + "mcinitcmd=esbc_validate 0x580640000;" \ + "esbc_validate 0x580680000;" \ "fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" #else @@ -378,7 +378,7 @@ unsigned long get_board_ddr_clk(void); "kernel_size=0x2800000\0" \ "kernel_size_sd=0x14000\0" \ "load_addr=0xa0000000\0" \ - "kernelheader_addr=0x580800000\0" \ + "kernelheader_addr=0x580600000\0" \ "kernelheader_addr_r=0x80200000\0" \ "kernelheader_size=0x40000\0" \ "BOARD=ls2088aqds\0" \ @@ -431,7 +431,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_TFABOOT #define SD_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ + "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ "&& esbc_validate $load_addr; " \ "env exists mcinitcmd && run mcinitcmd " \ "&& mmc read 0x80d00000 0x6800 0x800 " \ @@ -441,7 +441,7 @@ unsigned long get_board_ddr_clk(void); #define IFC_NOR_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x580780000; env exists mcinitcmd "\ + "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ "&& fsl_mc lazyapply dpl 0x580d00000;" \ "run nor_bootcmd; " \ "env exists secureboot && esbc_halt;" diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index de14fb4ac8..c1819d22a8 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017, 2019 NXP + * Copyright 2017, 2019-2020 NXP * Copyright 2015 Freescale Semiconductor */ @@ -323,46 +323,46 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_TFABOOT #define QSPI_MC_INIT_CMD \ "env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000;" \ + "esbc_validate 0x20640000 && " \ + "esbc_validate 0x20680000;" \ "fsl_mc start mc 0x20a00000 0x20e00000 \0" #define SD_MC_INIT_CMD \ "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ "mmc read 0x80e00000 0x7000 0x800;" \ "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x20 && " \ - "mmc read 0x80740000 0x3A00 0x20 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80a00000 0x80e00000\0" #define IFC_MC_INIT_CMD \ "env exists secureboot && " \ - "esbc_validate 0x580700000 && " \ - "esbc_validate 0x580740000; " \ + "esbc_validate 0x580640000 && " \ + "esbc_validate 0x580680000; " \ "fsl_mc start mc 0x580a00000 0x580e00000 \0" #else #ifdef CONFIG_QSPI_BOOT #define MC_INIT_CMD \ "mcinitcmd=env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000;" \ + "esbc_validate 0x20640000 && " \ + "esbc_validate 0x20680000;" \ "fsl_mc start mc 0x20a00000 0x20e00000 \0" #elif defined(CONFIG_SD_BOOT) #define MC_INIT_CMD \ "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ "mmc read 0x80100000 0x7000 0x800;" \ "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x20 && " \ - "mmc read 0x80740000 0x3A00 0x20 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" \ "mcmemsize=0x70000000\0" #else #define MC_INIT_CMD \ "mcinitcmd=env exists secureboot && " \ - "esbc_validate 0x580700000 && " \ - "esbc_validate 0x580740000; " \ + "esbc_validate 0x580640000 && " \ + "esbc_validate 0x580680000; " \ "fsl_mc start mc 0x580a00000 0x580e00000 \0" #endif #endif @@ -384,7 +384,7 @@ unsigned long get_board_sys_clk(void); "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ "kernelheader_addr_r=0x80200000\0" \ - "kernelheader_addr=0x580800000\0" \ + "kernelheader_addr=0x580600000\0" \ "kernel_addr_r=0x81000000\0" \ "kernelheader_size=0x40000\0" \ "fdt_addr_r=0x90000000\0" \ @@ -442,12 +442,12 @@ unsigned long get_board_sys_clk(void); "fdt_addr=0x64f00000\0" \ "kernel_addr=0x581000000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ + "kernelheader_start=0x600000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ "kernelheader_addr_r=0x80200000\0" \ - "kernelheader_addr=0x580800000\0" \ + "kernelheader_addr=0x580600000\0" \ "kernel_addr_r=0x81000000\0" \ "kernelheader_size=0x40000\0" \ "fdt_addr_r=0x90000000\0" \ @@ -501,7 +501,7 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_TFABOOT #define QSPI_NOR_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x20780000; " \ + "&& esbc_validate 0x206C0000; " \ "env exists mcinitcmd && " \ "fsl_mc lazyapply dpl 0x20d00000; " \ "run distro_bootcmd;run qspi_bootcmd; " \ @@ -510,7 +510,7 @@ unsigned long get_board_sys_clk(void); /* Try to boot an on-SD kernel first, then do normal distro boot */ #define SD_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ + "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ "&& esbc_validate $load_addr; " \ "env exists mcinitcmd && run mcinitcmd " \ "&& mmc read 0x80d00000 0x6800 0x800 " \ @@ -521,7 +521,7 @@ unsigned long get_board_sys_clk(void); /* Try to boot an on-NOR kernel first, then do normal distro boot */ #define IFC_NOR_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x580780000; env exists mcinitcmd "\ + "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ "&& fsl_mc lazyapply dpl 0x580d00000;" \ "run distro_bootcmd;run nor_bootcmd; " \ "env exists secureboot && esbc_halt;" @@ -531,7 +531,7 @@ unsigned long get_board_sys_clk(void); /* Try to boot an on-QSPI kernel first, then do normal distro boot */ #define CONFIG_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x20780000; " \ + "&& esbc_validate 0x206C0000; " \ "env exists mcinitcmd && " \ "fsl_mc lazyapply dpl 0x20d00000; " \ "run distro_bootcmd;run qspi_bootcmd; " \ @@ -540,7 +540,7 @@ unsigned long get_board_sys_clk(void); /* Try to boot an on-SD kernel first, then do normal distro boot */ #define CONFIG_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ + "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ "&& esbc_validate $load_addr; " \ "env exists mcinitcmd && run mcinitcmd " \ "&& mmc read 0x88000000 0x6800 0x800 " \ @@ -551,7 +551,7 @@ unsigned long get_board_sys_clk(void); /* Try to boot an on-NOR kernel first, then do normal distro boot */ #define CONFIG_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x580780000; env exists mcinitcmd "\ + "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ "&& fsl_mc lazyapply dpl 0x580d00000;" \ "run distro_bootcmd;run nor_bootcmd; " \ "env exists secureboot && esbc_halt;" diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 02cccff0c8..373daebfbc 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -189,18 +189,18 @@ unsigned long get_board_ddr_clk(void); /* Initial environment variables */ #define XSPI_MC_INIT_CMD \ "env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000 ;" \ + "esbc_validate 0x20640000 && " \ + "esbc_validate 0x20680000 ;" \ "fsl_mc start mc 0x20a00000 0x20e00000\0" #define SD_MC_INIT_CMD \ "mmc read 0x80a00000 0x5000 0x1200;" \ "mmc read 0x80e00000 0x7000 0x800;" \ "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x20 && " \ - "mmc read 0x80740000 0x3A00 0x20 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80a00000 0x80e00000\0" #define EXTRA_ENV_SETTINGS \ @@ -211,7 +211,7 @@ unsigned long get_board_ddr_clk(void); "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x7C0000\0" \ + "kernelheader_start=0x600000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ @@ -222,7 +222,7 @@ unsigned long get_board_ddr_clk(void); "load_addr=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernel_addr_sd=0x8000\0" \ - "kernelhdr_addr_sd=0x3E00\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernel_size_sd=0x1d000\0" \ "kernelhdr_size_sd=0x20\0" \ "console=ttyAMA0,38400n8\0" \ @@ -250,7 +250,7 @@ unsigned long get_board_ddr_clk(void); #define XSPI_NOR_BOOTCOMMAND \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x20780000; " \ + "&& esbc_validate 0x206C0000; " \ "env exists mcinitcmd && " \ "fsl_mc lazyapply dpl 0x20d00000; " \ "run distro_bootcmd;run xspi_bootcmd; " \ @@ -260,8 +260,8 @@ unsigned long get_board_ddr_clk(void); "env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80d00000 0x6800 0x800; " \ "env exists mcinitcmd && env exists secureboot " \ - " && mmc read 0x80780000 0x3C00 0x20 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80d00000;" \ "run distro_bootcmd;run sd_bootcmd;" \ "env exists secureboot && esbc_halt;" diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index f25cab18ae..1eb63d826f 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -22,7 +22,9 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SD +#define QIXIS_LBMAP_EMMC #define QIXIS_RCW_SRC_SD 0x08 +#define QIXIS_RCW_SRC_EMMC 0x09 #define NON_EXTENDED_DUTCFG #define QIXIS_SDID_MASK 0x07 #define QIXIS_ESDHC_NO_ADAPTER 0x7 diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index de385f82c8..82d49e53ab 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -22,7 +22,9 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SD +#define QIXIS_LBMAP_EMMC #define QIXIS_RCW_SRC_SD 0x08 +#define QIXIS_RCW_SRC_EMMC 0x09 #define NON_EXTENDED_DUTCFG /* VID */ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 83e258a6b9..b53a4b65d0 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -74,6 +74,25 @@ #define CONFIG_TFTP_TSIZE #endif +/* DFU over USB/UDC */ +#ifdef CONFIG_CMD_DFU +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M +#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_2M + +#ifdef CONFIG_ARM64 +#define KERNEL_FILENAME "Image" +#else +#define KERNEL_FILENAME "zImage" +#endif + +#define ENV_DFU_SETTINGS \ + "dfu_alt_info=u-boot.bin fat 0 1;uboot.env fat 0 1;" \ + "config.txt fat 0 1;" \ + KERNEL_FILENAME " fat 0 1\0" +#else +#define ENV_DFU_SETTINGS "" +#endif + /* Console configuration */ #define CONFIG_SYS_CBSIZE 1024 @@ -188,6 +207,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \ ENV_DEVICE_SETTINGS \ + ENV_DFU_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 05bfef75c0..8d10469e7c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -104,11 +104,8 @@ /* * L4 Watchdog */ -#ifdef CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 -#endif /* * MMC Driver diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 4afadafd35..87c73457a0 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -150,9 +150,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * L4 Watchdog */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG +#ifndef CONFIG_SPL_BUILD +#undef CONFIG_HW_WATCHDOG +#undef CONFIG_DESIGNWARE_WATCHDOG +#endif #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ @@ -162,7 +163,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); #else #define CONFIG_DW_WDT_CLOCK_KHZ 100000 #endif -#endif /* * SPL memory layout diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index cbc95029ff..874f268cb2 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -311,7 +311,6 @@ CONFIG_DEFAULT_IMMR CONFIG_DEF_HWCONFIG CONFIG_DELAY_ENVIRONMENT CONFIG_DESIGNWARE_ETH -CONFIG_DESIGNWARE_WATCHDOG CONFIG_DEVELOP CONFIG_DEVICE_TREE_LIST CONFIG_DFU_ALT |