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authorTom Rini <trini@konsulko.com>2018-05-11 11:45:28 -0400
committerTom Rini <trini@konsulko.com>2018-05-11 11:45:28 -0400
commit3b52847a451a81001b578353e793d7d9739b69d6 (patch)
tree37c62b1f1665262974d955078ce0d22485b1ab09 /tools/sunxi-spl-image-builder.c
parentc590e62d3b6f6dd72eae1183614f919e3fd7ffcb (diff)
parent4b87f2d500e94f877f38d9c11e4e47e1721f3fbe (diff)
downloadu-boot-3b52847a451a81001b578353e793d7d9739b69d6.tar.gz
Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup
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